xoviat
bbd12c9372
stm32: update metapac
2023-10-17 20:31:44 -05:00
Grant Miller
e7aeb9b29f
stm32f1: Keep flash prefetch enabled
2023-10-16 19:23:01 -05:00
xoviat
b24520579a
rcc: ahb/apb -> hclk/pclk
2023-10-15 19:51:35 -05:00
Dario Nieuwenhuis
b91d1eaca0
stm32/rcc: add LSE/LSI to all chips, add RTC to more chips.
2023-10-11 04:12:38 +02:00
xoviat
de2773afdd
stm32/rcc: convert bus prescalers to pac enums
2023-09-16 17:41:11 -05:00
xoviat
08415e001e
stm32/f3: add high res for hrtim and misc.
2023-09-10 13:33:17 -05:00
Dario Nieuwenhuis
e892014b65
Update stm32-metapac, includes chiptool changes to use real Rust enums now.
2023-06-29 02:01:33 +02:00
Marco Pastrello
db2bc8783e
Improve readability
2023-05-05 19:04:58 +02:00
Marco Pastrello
c37f86ff1c
removes unecessary braces
2023-05-05 00:12:32 +02:00
Marco Pastrello
2dcbe75cca
beautify
2023-05-04 23:51:42 +02:00
Marco Pastrello
5158014f3f
PPLXTPRE is a bool.
...
This flag for example permits the following clock tree
configuration on stm32f103r8
let mut config = Config::default();
config.rcc.hse = Some(Hertz(16_000_000));
config.rcc.sys_ck = Some(Hertz(72_000_000));
config.rcc.pclk1 = Some(Hertz(36_000_000));
config.rcc.pclk2 = Some(Hertz(72_000_000));
config.rcc.pllxtpre = true;
Init fails if pllxtpre is false.
2023-05-04 22:59:52 +02:00
Marco Pastrello
1cc61dc68a
Support PLLXTPRE switch.
...
See figure 2. Clock tree page 12 DS5319 Rev 18
https://www.st.com/resource/en/datasheet/stm32f103cb.pdf
2023-05-04 21:32:37 +02:00
chemicstry
1fd5022e72
Refactor IWDG to use LSI frequency from RCC
2022-07-10 20:59:36 +03:00
Dario Nieuwenhuis
397722c328
stm32: fix f100 build.
2022-06-26 23:52:38 +02:00
Dario Nieuwenhuis
39d06b59cd
Update stm32-data
2022-02-14 02:12:06 +01:00
Dario Nieuwenhuis
2eb0cc5df7
stm32/rcc: remove Rcc struct, RccExt trait.
...
All the RCC configuration is executed in init().
2022-01-05 00:00:44 +01:00
Dario Nieuwenhuis
b06e705a73
stm32/rcc: change family-specific code from dirs to single files.
...
Consistent with how other peripherals handle their versions.
2022-01-04 19:28:15 +01:00
