Commit Graph

1608 Commits

Author SHA1 Message Date
Dario Nieuwenhuis
cd9a65ba39 stm32/usb: use separate irq flags.
- Fixes race condition that could cause losing irqs (because `if flags != 0` was clearing all)
- Doesn't need CAS, which is nice for thumbv6.
2022-12-23 20:45:51 +01:00
Rasmus Melchior Jacobsen
47a0769fc2 Let repeated clock byte be singular pointer and not array pointer 2022-12-23 15:49:22 +01:00
Rasmus Melchior Jacobsen
e9a2c4a9e3 Let start_write_repeated accept pointer instead of slice 2022-12-23 15:40:09 +01:00
Rasmus Melchior Jacobsen
662bb5797f fix(stm32): Ensure that gpio speed is VeryHigh for all spi versions
This fixes #1095
2022-12-23 09:34:42 +01:00
Rasmus Melchior Jacobsen
2457fcaa35 fix(stm32): Align with updated dma::write_repeated signature 2022-12-23 09:33:34 +01:00
Rasmus Melchior Jacobsen
da9ee83756 fix(stm32): Fix write buffer lifetime for repeated writes 2022-12-23 09:32:18 +01:00
Dario Nieuwenhuis
3005ee0178 stm32/eth_v2: update to new embassy-net trait, remove PeripheralMutex. 2022-12-13 16:43:25 +01:00
Dario Nieuwenhuis
8f30652109 stm32/eth_v1: update to new embassy-net trait, remove PeripheralMutex. 2022-12-13 16:43:25 +01:00
Vincent Stakenburg
236d104844 embassy-stm32: add rs485 driver enable to uart 2022-12-09 14:26:09 +01:00
chemicstry
7bda01ec24 Fix comment 2022-12-06 23:31:58 +02:00
chemicstry
ef2b83cc03 Reset sdmmc clock on card init 2022-12-06 16:36:07 +02:00
bors[bot]
9f854110f2
Merge #1082 #1083
1082: stm32: Add basic support for DMA priority settings r=lulf a=matoushybl

This adds very basic support for specifying priority for DMA interrupts. Unfortunately, the patch now doesn't allow for specifying different priorities for DMA1/DMA2, or BDMA1/BDMA2, which I didn't know how to support.

1083: stm32: Fix H7 unaligned erase r=lulf a=matoushybl

This PR simplifies erasing sectors on the H7, which was buggy.

Co-authored-by: Matous Hybl <hyblmatous@gmail.com>
2022-12-01 13:49:59 +00:00
bors[bot]
d8ea297d6a
Merge #1088
1088: stm32: Enable fifo for buffered uart r=lulf a=matoushybl

This PR enables fifo for buffered uart where it is available. This should hopfully get rid of some overrun errors. I tried it in my application where it worked, but more intensive testing is probably required.

Co-authored-by: Matous Hybl <hyblmatous@gmail.com>
2022-12-01 13:34:52 +00:00
Matous Hybl
e1d7d8d841 stm32: Enable fifo for buffered uart 2022-11-30 22:17:51 +01:00
Guillaume MICHEL
e0ea5dfdb2 embassy-stm32: Allow SPI with DMA to implement blocking embbeded-hal traits 2022-11-30 09:26:16 +01:00
Matous Hybl
4cc0463123 stm32: Add basic support for DMA priority settings 2022-11-28 21:22:39 +01:00
Matous Hybl
2a35a09444 stm32: Fix H7 unaligned erase 2022-11-28 21:15:24 +01:00
Gabriel Smith
3ca14ba4e9 usb-driver: Remove unncessary lifetime 2022-11-27 16:28:24 -05:00
Dario Nieuwenhuis
1e2fb0459d Switch to async-fn-in-trait 2022-11-25 21:02:06 +01:00
Jaxter Kim
551b54ddcb stm32g0: Fix ADC for channels above 14 2022-11-15 12:56:47 +01:00
bors[bot]
d05979c708
Merge #1052 #1053
1052: stm32: Fix watchdog division by zero for 256 prescaler, add watchdog … r=lulf a=matoushybl

…example for H7

The problem is that `2u8.powi(8) == 0`, which causes division by zero.

1053: Disable MMC interrupts r=lulf a=matoushybl

MMC interrupts can cause firmware hangup - refer to: https://github.com/stm32-rs/stm32h7xx-hal/issues/275 for more information

Fixes #594 

Co-authored-by: Matous Hybl <hyblmatous@gmail.com>
2022-11-11 08:04:16 +00:00
Matous Hybl
99682d313b Disable MMC interrupts
MMC interrupts can cause firmware hangup - refer to: https://github.com/stm32-rs/stm32h7xx-hal/issues/275 for more information
2022-11-10 17:21:42 +01:00
Matous Hybl
cbc97758e3 stm32: Fix watchdog division by zero for 256 prescaler, add watchdog example for H7 2022-11-10 15:56:28 +01:00
Guillaume MICHEL
1365ce6ab8 embassy-stm32: Fix bug when Uart::read future is dropped and DMA request was not stopped
fixes issue #1045

regression was introduced with PR #1031
2022-11-07 17:46:32 +01:00
bors[bot]
1f246d0e37
Merge #1034
1034: stm32/usart: Fix bug where USART idle flag could end a `read` prematuraly r=Dirbaio a=guillaume-michel

on STM32, when setting USART `detect_previous_overrun = true`, the idle flag is not cleared and could result in premature end of the `read` method.

This PR fixes that.

Co-authored-by: Guillaume MICHEL <guillaume@squaremind.io>
2022-10-28 11:22:53 +00:00
Guillaume MICHEL
49e1091309 embassy-stm32: Fix bug where USART idle flag could end a read prematuraly 2022-10-28 10:49:59 +02:00
Guillaume MICHEL
79b49c6fae embassy-stm32: remove duplicated code for USART general configuration 2022-10-28 09:32:05 +02:00
Guillaume MICHEL
f053bf742c embassy-stm32: Add support for hardware flow control for BufferedUart 2022-10-28 09:04:36 +02:00
Guillaume MICHEL
9423987ac5 embassy-stm32: Add hardware flow control constructor for UartRx and UartTx 2022-10-28 09:04:36 +02:00
Grant Miller
171b764d82 Refactor: Use PeripheralRef 2022-10-26 18:36:04 -05:00
Grant Miller
08c8022583 Refactor: Reorder _version cfgs 2022-10-26 18:04:52 -05:00
Grant Miller
4f2dcca34b Refactor: Fix v4 RccPeripheral bounds 2022-10-26 17:59:44 -05:00
Grant Miller
9c30d565b9 Refactor: Factor out Adc struct declaration 2022-10-26 17:51:12 -05:00
Grant Miller
f363f6ce92 Refactor: Don't return references to pointers 2022-10-26 17:35:06 -05:00
Grant Miller
6bf24b4d1a Refactor: Remove unused Common trait 2022-10-26 17:35:01 -05:00
Grant Miller
88bbc238b7 Set resolution directly 2022-10-26 17:07:58 -05:00
Grant Miller
2cfe2439c9 Refactor: Impl From for SampleTime and Resolution 2022-10-26 17:07:58 -05:00
Grant Miller
7b38b95e10 Refactor: Factor out Resolution 2022-10-26 17:07:58 -05:00
Grant Miller
5142674786 Fix pre-existing SampleTime typos 2022-10-26 17:07:50 -05:00
Grant Miller
a5b1d2237f Refactor: Factor out SampleTime 2022-10-26 17:06:44 -05:00
bors[bot]
7f499f3edc
Merge #1024
1024: stm32/adc: Remove voltage and temperature conversions r=Dirbaio a=GrantM11235

The current conversion utilities are confusing and a bit of a footgun. (Two out of the three examples got it wrong! They didn't measure vref at all, so all the conversions are completely wrong if vcca isn't 3.3v)

I think we should eventually have some sort of conversion utilities in the HAL, but for now I think it is best to just remove it and let the users do their own math.

cc `@chemicstry` 

Co-authored-by: Grant Miller <GrantM11235@gmail.com>
2022-10-26 19:44:06 +00:00
bors[bot]
01e23bf9dd
Merge #1025
1025: Implement I2C timeouts, second attempt r=Dirbaio a=chemicstry

This is an alterrnative to #1022 as discussed there.

Timeouts are implemented using suggested `check_timeout: impl Fn() -> Result<(), Error>` function, which does not depend on `embassy-time` by default and is a noop for regular I2C.

This also adds `time` feature like in `embassy-nrf` to enable `embassy-time` dependencies. While at it, I also gated some other peripherals that depend on `embassy-time`, notably `usb` and (partially) `subghz`.

`TimeoutI2c` is currently only implemented for i2cv1, because i2cv2 has additional complications:
- Async methods still use a lot of busy waiting code in between DMA transfers, so simple `with_timeout()` will not work and it will have to use both types of timeouts. It could probably be rewritten to replace busy waits with IRQs, but that's outside the scope of this PR.
- I2C definition `I2c<'d, T, TXDMA, RXDMA>` is different from i2cv1 `I2c<'d, T>` making it hard to share single `TimeoutI2c` wrapper. A couple of options here:
  - Duplicate `TimeoutI2c` code
  - Add dummy `TXDMA`, `RXDMA` types to i2cv1 considering that in the future it should also support DMA

Co-authored-by: chemicstry <chemicstry@gmail.com>
2022-10-26 19:34:43 +00:00
bors[bot]
e5097a8866
Merge #959
959: Generic, executor-agnostic queue implementation r=ivmarkov a=ivmarkov

Hopefully relatively well documented.

Implementation relies on a fixed-size `SortedLinkedList` from `heapless`. (By default, for up to 128 timer schedules, but we can lower this number to - say - 64.)

As discussed earlier, on queue overflow, the `WakerRegistration` approach is utilized, whereas the waker that is ordered first in the queue is awoken to make room for the incoming one (which might be the waker that would be awoken after all!). Wakers are compared with `Waker::will_wake`, so the queue should actually not fill up that easily, if at all.

I've left provisions for the user to manually instantiate the queue using a dedicated macro - `generic_queue!` so that users willing to adjust the queue size, or users (like me) who have to use the queue in a complex "on-top-of-RTOS-but-the-timer-driver-calling-back-from-ISR" scenario can customize the mutex that protects the queue.

The one thing I'm not completely happy with is the need to call `{ embassy_time::queue::initialize() }` early on before any futures using embassy-time are polled, which is currently on the shoulders of the user. I'm open to any ideas where we can get rid of this and do it on the first call to `_embassy_time_schedule_wake`, without introducing very complex combinations of critical sections, atomics and whatnot.




Co-authored-by: ivmarkov <ivan.markov@gmail.com>
Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2022-10-26 19:14:12 +00:00
Guillaume MICHEL
9cac649fcf stm32: Add support for read_until_idle on UART 2022-10-26 19:06:18 +02:00
Dario Nieuwenhuis
eeb072d9cb Update Rust nightly. 2022-10-26 16:47:29 +02:00
Mathias
66611a80ca Introduce shared new_inner for uart instantiation 2022-10-26 11:51:37 +02:00
Mathias
d1eee52625 Merge branch 'master' of https://github.com/embassy-rs/embassy into embassy-stm32/uart-flowcontrol 2022-10-26 11:47:00 +02:00
chemicstry
52c03cf0a4 Add more docs 2022-10-24 22:48:40 +03:00
chemicstry
ac61e0ee9f fmt 2022-10-24 22:39:13 +03:00
chemicstry
33f75419e5 Unify i2cv1 definition with i2cv2 2022-10-24 22:34:10 +03:00
chemicstry
6062978d58 Remove weird async timeouts 2022-10-24 22:22:20 +03:00
chemicstry
ca8afacfd0 Implement TimeoutI2c for i2cv2 2022-10-24 22:11:15 +03:00
chemicstry
9ad7e85288 Merge branch 'i2c_timeout2_v2' into i2c_timeout2 2022-10-24 21:50:29 +03:00
chemicstry
9b209ffe1c Add docs 2022-10-24 12:39:47 +03:00
chemicstry
5f02bee388 Gate TimeoutI2c behind i2cv1 2022-10-24 12:34:55 +03:00
chemicstry
1bed02296c i2cv2 timeouts 2022-10-24 12:33:17 +03:00
Grant Miller
545cc9326b stm32/adc: Remove voltage and temperature conversions 2022-10-24 04:00:29 -05:00
chemicstry
d99841fea9 Implement time feature 2022-10-24 11:38:15 +03:00
ivmarkov
e3cf4255c6 Help compiler with type inference 2022-10-24 11:31:54 +03:00
chemicstry
4ce4131f8b Implement i2cv1 timeout 2022-10-24 11:30:04 +03:00
ivmarkov
f78c706b89 Address review feedback 2022-10-24 11:10:59 +03:00
ivmarkov
4d5550070f Change time Driver contract to never fire the alarm synchronously 2022-10-24 09:17:43 +03:00
Matous Hybl
6c5d81ada5 Add memory barriers to H7 flash driver to mitigate PGSERR errors
The stm32h7xx-hal uses only the ordering barrier, while the CubeMX uses the DSB and ISB instructions, to be on the safe side, both are used here.
2022-10-18 22:42:02 +02:00
Mathias
86113e199f Remove unused feature gate 2022-10-11 10:35:43 +02:00
Mathias
9223b67306 Fix RTC for v2l0 & v2l1 2022-10-11 10:28:28 +02:00
Mathias
aff265a7f5 Merge branch 'master' of https://github.com/embassy-rs/embassy into embassy-stm32/rtc 2022-10-11 09:19:55 +02:00
Mathias
79cee74151 Fix stm32wl55jc-cm4 RTC 2022-10-11 09:19:47 +02:00
chemicstry
322cfafed3 Fix adc_v4 compilation 2022-10-07 14:53:03 +03:00
chemicstry
df7174ecb0 Fix internal channel reading on adc_v2 2022-10-07 14:31:55 +03:00
chemicstry
9dca368c3d Use RccPeripheral for adc_v2 2022-10-07 13:29:56 +03:00
bors[bot]
aabc02506b
Merge #992
992: (embassy-stm32): remove flash lock/unlock public API from stm32 flash r=lulf a=MathiasKoch

Instead, perform the unlocking and locking automatically on erase and write operations.

This makes the `embedded-storage` abstraction actually useable in libraries, while still keeping the flash peripheral locked the majority of the time.

Co-authored-by: Mathias <mk@blackbird.online>
2022-09-30 11:32:27 +00:00
Mathias
62c0b18f10 Merge branch 'master' of https://github.com/embassy-rs/embassy into embassy-stm32/rtc 2022-09-30 06:15:12 +02:00
Mathias
a283c47557 Implement embedded-hal-nb for uart 2022-09-30 06:04:19 +02:00
Mathias
a7fdeac560 Remove flash lock/unlock public API from stm32 flash, and perform the unlocking and locking automatically on erase and write operations 2022-09-30 06:00:46 +02:00
Mathias
38faae26e5 Merge branch 'master' of https://github.com/embassy-rs/embassy into embassy-stm32/uart-flowcontrol 2022-09-29 12:58:38 +02:00
Mathias
a77e2c3512 Merge branch 'master' of https://github.com/embassy-rs/embassy into embassy-stm32/uart-eh1 2022-09-29 12:58:01 +02:00
Ulf Lilleengen
72c2e985bb Update embedded-hal versions and explicitly pin 2022-09-29 11:27:46 +02:00
Mathias
f9c62d4f1d Add flowcontrol to UART 2022-09-29 09:12:17 +02:00
Mathias
dc90006982 Remove code duplication on nb_read 2022-09-29 07:58:11 +02:00
Mathias
a83560c6b1 Implement RTC peripheral for all stm32 families with rtc 2022-09-29 07:49:32 +02:00
Mathias
823bd714fb Add E-H1 uart blocking & nb implementation 2022-09-28 05:19:43 +02:00
Dario Nieuwenhuis
17d8d11f73 usb: make HALs depend only on embassy-usb-driver. 2022-09-27 13:16:49 +02:00
Guillaume MICHEL
daf2744716 Rework STM32 BufferedUart internals so we can split into Rx and Tx like embassy-nrf 2022-09-26 15:32:29 +02:00
Dario Nieuwenhuis
7f7c14b7bc usb: split driver trait to separate crate. 2022-09-26 12:29:27 +02:00
bors[bot]
a9efbf18c6
Merge #960
960: Add non blocking Bxcan constructor r=Dirbaio a=andyblarblar

This PR adds a non-blocking constructor to the Bxcan Can wrapper struct. This allows for the creation of the Can periferal without blocking for a sync with the Can bus.

Co-authored-by: Andrew Ealovega <Andrew@Ealovega.dev>
2022-09-26 09:39:55 +00:00
Dario Nieuwenhuis
10d1ad2343 Replace futures::future::join -> embassy_futures::join::join. 2022-09-22 16:48:35 +02:00
Dario Nieuwenhuis
a0487380da Replace futures::future::poll_fn -> core::future::poll_fn. 2022-09-22 16:42:49 +02:00
Dario Nieuwenhuis
897b72c872 Update Rust nightly.
Removes feature(generic_associated_types)
2022-09-22 16:38:14 +02:00
Andrew Ealovega
5914d80968 Add non blocking Bxcan constructor.
Signed-off-by: Andrew Ealovega <Andrew@Ealovega.dev>
2022-09-21 22:29:57 -04:00
Vincent Stakenburg
c4d5c047d7 make State::new() const, consistent with others 2022-09-15 12:34:17 +02:00
bors[bot]
22c32b5d5c
Merge #939
939: time: add more tick rates, use 1mhz as default. r=Dirbaio a=Dirbaio



Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2022-09-04 22:13:34 +00:00
bors[bot]
6264fe39a5
Merge #839
839: Misc LoRaWAN improvements r=lulf a=timokroeger

Trying too get `embassy-lora` running on a [LoRa-E5 Dev Board](https://wiki.seeedstudio.com/LoRa_E5_Dev_Board/).
I can see the join message arriving in the The Things Network console but the device does not receive the accept message yet.
Opening this PR anyway because I think there are some nice things to decouple the lora crate from the nucleo board.

`@lulf` Could you test if this PR breaks your LoRa setup? Marking as draft for the time being.

Co-authored-by: Timo Kröger <timokroeger93@gmail.com>
Co-authored-by: Ulf Lilleengen <lulf@redhat.com>
2022-09-04 07:17:23 +00:00
Dario Nieuwenhuis
5327b9c289 time: add more tick rates, use 1mhz as default. 2022-09-02 00:59:34 +02:00
Dario Nieuwenhuis
8ba421f324 Do not use cfg_if for embedded-hal-async feature gates.
Old code used `cfg_if!` because rustc still parses code inside disabled cfg's, and Rust stable at that time couldn't parse the new GAT where-clause location. This is not the case anymore.
2022-08-31 03:11:21 +02:00
Timo Kröger
308ca4b8e3 Use pub(crate) visibility for internal SPI
SubGhz provides a public interface for the radio connected to internal SPI
`#[allow(dead_code)]` is required for CI to succeed
2022-08-26 15:44:58 +02:00
Timo Kröger
84240d49ea stm32wl: Fix RCC
* `MSIRGSEL = 1` was required for MSI accept the updated MSI range
* Reorder enable and clock switching to properly handle the jump from
the default 4MHz MSI to a higher MSI freuquency
2022-08-26 15:44:58 +02:00
Timo Kröger
61c666212f stm32wl: Do not require external SPI pins for SUBGHZ
For the Seeed Studio Lora-E5 those pins conflict with the radio frontend control GPIOS (PA4 and PA5).
2022-08-26 15:42:25 +02:00
Dario Nieuwenhuis
21072bee48 split embassy-util into embassy-futures, embassy-sync. 2022-08-22 22:18:13 +02:00
Vincent Stakenburg
51359e7d24 fix lpuart implementation when there isn't one present 2022-08-19 15:27:11 +02:00
Vincent Stakenburg
a833e02363 implement support for LPUART 2022-08-19 12:05:19 +02:00
Dario Nieuwenhuis
5daa173ce4 Split embassy-time from embassy-executor. 2022-08-18 01:22:30 +02:00
Dario Nieuwenhuis
fc6e1e06b3 Remove HAL initialization from #[embassy::main] macro. 2022-08-17 22:16:46 +02:00
Dario Nieuwenhuis
67edea4168 Update to critical-section 1.0, atomic-polyfill 1.0 2022-08-17 19:01:56 +02:00
Dario Nieuwenhuis
2649f13dc7 stm32/rcc: fix unnecessary parentheses 2022-08-17 15:03:23 +02:00
Dario Nieuwenhuis
72cd015c1a stm32/sdmmc: remove cast no longer allowed on latest nightly due to nonexhaustive enum. 2022-08-17 14:44:18 +02:00
chemicstry
936473b68a Make sda/scl pullups separate as in nRF HAL 2022-08-10 12:36:15 +03:00
chemicstry
6498324b58 Implement I2C pullup configuration 2022-08-09 22:13:35 +03:00
chemicstry
206b7fd8ed Use RccPeripheral for DAC and add a hackfix for H7 2022-08-04 03:31:47 +03:00
chemicstry
5f01e56728 Merge v1, v2 DAC and update register definitions 2022-08-04 03:02:57 +03:00
Dario Nieuwenhuis
a0f1b0ee01 Split embassy crate into embassy-executor, embassy-util. 2022-07-29 23:40:36 +02:00
chemicstry
42434c75bc Make vref units explicit 2022-07-27 14:13:59 +03:00
chemicstry
b1f0d6320e Improve set_vref docs 2022-07-27 01:30:32 +03:00
chemicstry
046778fc53 Improve ADC configuration options 2022-07-27 01:17:26 +03:00
Dario Nieuwenhuis
b5ff7c5d60 rename PwmPin::new_chX, update examples. 2022-07-23 16:16:29 +02:00
Ben Gamari
042e11960e embassy-stm32/pwm: Generalize channel selection
550da471be previously refactored the STM32
PWM logic in such a way to preclude use of non-contiguous channels (e.g.
channel 2 but not channel 1). Refactor it yet again to yet again allow
this sort of usage.
2022-07-23 15:57:13 +02:00
Dario Nieuwenhuis
19d1ef0e29 stm32/gpio: Add Peripheral<Self> bound to Pin. 2022-07-23 14:28:42 +02:00
Dario Nieuwenhuis
4901c34d9c Rename Unborrowed -> PeripheralRef, Unborrow -> Peripheral 2022-07-23 14:00:19 +02:00
Dario Nieuwenhuis
8a9d2f59af Update embassy-stm32 2022-07-23 02:40:13 +02:00
Dario Nieuwenhuis
be6408e202 Rename unsafe_impl_unborrow to impl_unborrow 2022-07-23 01:33:22 +02:00
bors[bot]
9d388d357a
Merge #866
866: F4 flash fixes r=Dirbaio a=chemicstry

This discontinuous flash sector layout is too cursed and I left some mistakes in last PR. Erasing last sector did not work and it wasn't possible to erase between memory banks for 1MB dual-bank devices. So I changed the erase function to iterate over memory addresses (which is continuous) instead of sector numbers.

It should also be possible to implement erase across memory banks for H7, but it requires special handling for write too. I don't have an H7 to test now so left it as is.

I wasn't sure how to add tests to `embassy-stm32` and it seems that there are none, except for `subghz`, but no test runner? Anyway, I tested the `get_sector` on playground: https://play.rust-lang.org/?version=stable&mode=debug&edition=2021&gist=13b59339fe6c70a3249e6183e81f869e

Also fixed erase alignment requirements on `Flash::blocking_erase()`, as it previously only checked alignment on size, but not on offsets.

P.S. the diff is a bit messed up, I recommend looking at files directly

Co-authored-by: chemicstry <chemicstry@gmail.com>
2022-07-15 06:19:05 +00:00
chemicstry
f0027c9fe0 Require erase address to be aligned to page size 2022-07-14 21:21:46 +03:00
chemicstry
5a265661bb Fix erasing across banks 2022-07-14 20:58:01 +03:00
chemicstry
039acda3a8 Fix writing to last sector of F4 flash 2022-07-14 19:41:39 +03:00
chemicstry
53e40860c1 Move all gpio logic to Flex 2022-07-13 02:45:37 +03:00
chemicstry
a335589f34 Change get_set_level to get_output_level 2022-07-13 02:25:09 +03:00
chemicstry
329955f718 Use Into conversions instead of matches 2022-07-13 02:08:31 +03:00
chemicstry
98dcce81ca Add more convenience GPIO functions 2022-07-13 01:43:22 +03:00
chemicstry
2df665da8a Revert "Make advanced timer trait not require general purpose timer trait as the timers are too different."
This reverts commit 4988dfe981.
2022-07-12 15:11:57 +03:00
bors[bot]
2adee4af38
Merge #858
858: embassy-stm32: Simplify time r=Dirbaio a=GrantM11235

- Remove unused `MilliSeconds`, `MicroSeconds`, and `NanoSeconds` types
- Remove `Bps`, `KiloHertz`, and `MegaHertz` types that were only used
for converting to `Hertz`
- Replace all instances of `impl Into<Hertz>` with `Hertz`
- Add `hz`, `khz`, and `mhz` methods to `Hertz`, as well as
free function shortcuts
- Remove `U32Ext` extension trait

Co-authored-by: Grant Miller <GrantM11235@gmail.com>
2022-07-11 02:51:06 +00:00
Grant Miller
5ecbe5c918 embassy-stm32: Simplify time
- Remove unused `MilliSeconds`, `MicroSeconds`, and `NanoSeconds` types
- Remove `Bps`, `KiloHertz`, and `MegaHertz` types that were only used
for converting to `Hertz`
- Replace all instances of `impl Into<Hertz>` with `Hertz`
- Add `hz`, `khz`, and `mhz` methods to `Hertz`, as well as
free function shortcuts
- Remove `U32Ext` extension trait
2022-07-10 21:46:45 -05:00
bors[bot]
99f4fd33b4
Merge #859
859: Add F4 flash driver r=Dirbaio a=chemicstry

Pending on https://github.com/embassy-rs/stm32-data/pull/152

Co-authored-by: chemicstry <chemicstry@gmail.com>
2022-07-11 01:37:19 +00:00
chemicstry
3271ba36e4 Fix cfg flags 2022-07-11 04:07:28 +03:00
chemicstry
734c38eb9c Add F4 flash driver 2022-07-11 03:57:46 +03:00
bors[bot]
9753f76794
Merge #810
810: Takes care of power for nRF USB devices r=Dirbaio a=huntc

Modifies the usb-serial example to illustrate how to setup USB for situations where the USB power can be detected and removed.

Gaps:

~~* No support for the nrf-softdevices as yet, although this should be possible via another constructor.~~
* No support for the nrf5340, although this should be possible via USBREG.

The change is tested and appears to work. Some notes:

* There's an existing field named self_powered as a UsbDevice field. It doesn't ever appear to get set. I'm wondering if this field is intended to signal that a device has the nRF VBUS power situation or not. I'm not presently using it.
* The new PowerDetected event is generated on the bus initially in situations where just new is used i.e. without power management, including on STM. We can therefore rely on this event always being generated.

Old description:

~~EnabledUsbDevice is a wrapper around the `UsbDevice` where its enablement is also subject to external events, such as `POWER` events for nRF. It is introduced generically to support other platforms should they also require external signaling for enablement.~~

Co-authored-by: huntc <huntchr@gmail.com>
2022-07-11 00:01:41 +00:00
bors[bot]
c6a11db39e
Merge #854
854: Implement IWDG timeout calculation r=Dirbaio a=chemicstry

Allow specifying `IndependentWatchdog` timeout as `Duration` instead of prescaler value.

Since IWDG is clocked from LSI, which differs between families, I standardized HSI/LSI definitions in RCC and used that.

Co-authored-by: chemicstry <chemicstry@gmail.com>
2022-07-10 21:45:34 +00:00
chemicstry
5a208d28d0 Fix g0 rcc build 2022-07-11 00:37:00 +03:00
bors[bot]
93e7d53e39
Merge #851
851: Gpio dynamic flex r=Dirbaio a=AntoineMugnier

Add Flex GPIO type for embassy-stm32 as it is the case for  embassy-nrf.


Co-authored-by: amugniere@gmail.com <antoine.mugnier@depixus.com>
2022-07-10 21:22:46 +00:00
chemicstry
d7d1e46a5f Use u32 instead of Duration for IWDG 2022-07-11 00:00:33 +03:00
amugniere@gmail.com
323b0d1a5c Have removed ANOTHER redondant ErrorType trait impl 2022-07-10 22:01:48 +02:00
amugniere@gmail.com
1eca026ebd Have removed redondant ErrorType trait impl 2022-07-10 21:36:04 +02:00
amugniere@gmail.com
e4a36e1d98 rustfmt on previously edited files 2022-07-10 21:08:12 +02:00
amugniere@gmail.com
53388d4576 have adapted access to pin() and port() methods of Sealed::Pin in exti.rs according to previous changes on Input struct 2022-07-10 20:55:04 +02:00
chemicstry
3bf1e1d4aa Fix f2, wl compilation 2022-07-10 21:46:14 +03:00
chemicstry
f43545f36e Fix warnings 2022-07-10 21:16:54 +03:00
chemicstry
85054a7233 Fix typo 2022-07-10 21:15:38 +03:00
chemicstry
1fd5022e72 Refactor IWDG to use LSI frequency from RCC 2022-07-10 20:59:36 +03:00
chemicstry
bd01e90bfa Implement IWDG timeout calculation 2022-07-10 20:38:30 +03:00
bors[bot]
5f43c1d37e
Merge #850
850: Shared buses with SetConfig r=Dirbaio a=kalkyl

Addresses issue #830 

Co-authored-by: Henrik Alsér <henrik@mindbite.se>
2022-07-10 00:03:44 +00:00
amugniere@gmail.com
fa3e1ab68a correction of the access to flex pin attribute in gpio_v2 2022-07-09 14:06:47 +02:00
Henrik Alsér
880b71a1e8 impl SetConfig for stm32 i2c and SPI 2022-07-09 02:28:05 +02:00
amugniere@gmail.com
39702d7624 set_as_input_output() and set_as_output() : Have added comments and made functions public 2022-07-08 21:46:16 +02:00
Henrik Alsér
43aec9083c Cleanup 2022-07-08 08:03:38 +02:00
Dario Nieuwenhuis
01ef03f446 stm32/i2c: impl ErrorType for all. 2022-07-07 15:46:30 +02:00
Henrik Alsér
399e7a4791 NoDma 2022-07-07 15:46:30 +02:00
Henrik Alsér
be731b222e Cleanup 2022-07-07 15:46:30 +02:00
Henrik Alsér
0fe818f4f8 v1 fix 2022-07-07 15:46:30 +02:00
Henrik Alsér
1ed5b387f9 v2 fix 2022-07-07 15:46:30 +02:00
Henrik Alsér
02812754ec rustfmt 2022-07-07 15:46:30 +02:00
Henrik Alsér
2460d21fa4 Add EH 1.0 impls for stm32 i2c 2022-07-07 15:46:30 +02:00
huntc
4a8f117f25 Puts in the machinery to handle power detected/removed 2022-07-07 10:08:57 +10:00
amugniere@gmail.com
4e54d09ab1 Have added OutputOpenDrain with Flex 2022-07-04 22:38:05 +02:00
amugniere@gmail.com
13b259d7cd Have added Flex to eh01 and eh2 2022-07-04 22:19:02 +02:00
amugniere@gmail.com
359fc4d124 Flex GPIO implementation : Output 2022-06-30 23:03:15 +02:00
amugniere@gmail.com
f05082b9a3 have reverted changed in mod eh1 from previous commit 2022-06-30 22:55:57 +02:00
amugniere@gmail.com
9b3c5af92a Flex GPIO implementation : Input 2022-06-30 22:50:53 +02:00
Vincent Stakenburg
d1d07cd9e3 fix case when chip has multiple iwdg 2022-06-28 13:22:43 +02:00
Vincent Stakenburg
f2ad9c2d9d rebase and fix unborrow 2022-06-28 12:51:08 +02:00
Vincent Stakenburg
74bbf5aa02 address review 2022-06-28 12:46:17 +02:00
Vincent Stakenburg
5cf3fbece4 initial independent watchdog implementation 2022-06-28 12:46:17 +02:00
Dario Nieuwenhuis
a855889f70 Update stm32-data 2022-06-27 02:10:01 +02:00
Dario Nieuwenhuis
397722c328 stm32: fix f100 build. 2022-06-26 23:52:38 +02:00
chemicstry
3cdd8c1aeb Fix PWM for advanced timers 2022-06-23 02:27:39 +03:00
Dario Nieuwenhuis
88e36a70bd
Update to 2021 edition. (#820) 2022-06-18 02:15:48 +02:00
Daniel Bevenius
9031b8f80a Fix doc comments for BpskPacketParams 2022-06-16 07:34:59 +02:00
Daniel Bevenius
d0edd171f8 Fix typo in LoRaPacketParams::new doc 2022-06-16 06:22:03 +02:00
Ulf Lilleengen
faa59efbf6 Cargo fmt 2022-06-15 09:01:22 +02:00
Ulf Lilleengen
3696226fe8 Sync subghz peripheral support with stm32wlxx-hal 2022-06-14 16:27:42 +02:00
Dario Nieuwenhuis
a8703b7598 Run rustfmt. 2022-06-12 22:22:31 +02:00
Dario Nieuwenhuis
5085100df2 Add embassy-cortex-m crate.
- Move Interrupt and InterruptExecutor from `embassy` to `embassy-cortex-m`.
- Move Unborrow from `embassy` to `embassy-hal-common` (nothing in `embassy` requires it anymore)
- Move PeripheralMutex from `embassy-hal-common` to `embassy-cortex-m`.
2022-06-12 21:45:38 +02:00
Dario Nieuwenhuis
db344c2bda
common/PeripheralMutex: remove unsafe API. (#802)
Following the project's decision that "leak unsafe" APIs are not marked as "unsafe",
update PeripheralMutex to accept non-'static state without unsafe.

Fixes #801
2022-06-09 21:28:13 +02:00
Ulf Lilleengen
7d64f5cda7 Use correct index and bank 2022-06-07 15:59:22 +02:00
Dario Nieuwenhuis
3e4bead321 stm32: add USB driver. 2022-06-07 03:29:00 +02:00
Dario Nieuwenhuis
0aa73f58e2 Update stm32-metapac. 2022-06-07 00:28:26 +02:00
chemicstry
b0ffd9a1cc Fix AF pullup configuration for GPIOv1 2022-06-06 17:12:52 +03:00
bors[bot]
70e4418df9
Merge #781 #785
781:  embassy-net v2 r=Dirbaio a=Dirbaio

- No more `dyn`
- It's no longer a global singleton, you can create muliple net stacks at once.
  - You can't tear them down though, the Device it still has to be `'static` due to restrictions with smoltcp's "fake GAT" in the Device trait. :(
- Removed `_embassy_rand` hack, random seed is passed on creation.



785: stm32: g0: add PLL clock source r=Dirbaio a=willglynn

STM32G0 SYSCLK can be sourced from PLLRCLK. Given that the HSI runs at 16 MHz and the HSE range is 4-48 MHz, the PLL is the only way to reach 64 MHz. This commit adds `ClockSrc::PLL`.

The PLL sources from either HSI16 or HSE, divides it by `m`, and locks its VCO to multiple `n`. It then divides the VCO by `r`, `p`, and `q` to produce up to three associated clock signals:

  * PLLRCLK is one of the inputs on the SYSCLK mux. This is the main reason the user will configure the PLL, so `r` is mandatory and the output is enabled unconditionally.
  * PLLPCLK is available as a clock source for the ADC and I2S peripherals, so `p` is optional and the output is conditional.
  * PLLQCLK exists only on STM32G0B0xx, and exists only to feed the MCO and MCO2 peripherals, so `q` is optional and the output is conditional.

When the user specifies `ClockSrc::PLL(PllConfig)`, `rcc::init()` calls `PllConfig::init()` which initializes the PLL per [RM0454]. It disables the PLL, waits for it to stop, enables the source oscillator, configures the PLL, waits for it to lock, and then enables the appropriate outputs. `rcc::init()` then switches the clock source to PLLRCLK.

`rcc::init()` is now also resonsible for calculating and setting flash wait states. SYSCLCK < 24 MHz is fine in the reset state, but 24-48 MHz requires waiting 1 cycle and 48-64 MHz requires waiting 2 cycles. (This was likely a blocker for anyone using HSE >= 24 MHz, with or without the PLL.) Flash accesses are now automatically slowed down as needed before changing the clock source, and sped up as permitted after changing the clock source. The number of flash wait states also determines if flash prefetching will be profitable, so that is now handled automatically too.

[RM0454]: https://www.st.com/resource/en/reference_manual/rm0454-stm32g0x0-advanced-armbased-32bit-mcus-stmicroelectronics.pdf

Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Co-authored-by: Will Glynn <will@willglynn.com>
2022-05-31 00:25:21 +00:00
Will Glynn
1c2b27dcad embassy-stm32: g0: add PLL clock source
STM32G0 SYSCLK can be sourced from PLLRCLK. Given that the HSI runs at
16 MHz and the HSE range is 4-48 MHz, the PLL is the only way to reach
64 MHz. This commit adds `ClockSrc::PLL`.

The PLL sources from either HSI16 or HSE, divides it by `m`, and locks
its VCO to multiple `n`. It then divides the VCO by `r`, `p`, and `q`
to produce up to three associated clock signals:

  * PLLRCLK is one of the inputs on the SYSCLK mux. This is the main
    reason the user will configure the PLL, so `r` is mandatory and
	the output is enabled unconditionally.
  * PLLPCLK is available as a clock source for the ADC and I2S
    peripherals, so `p` is optional and the output is conditional.
  * PLLQCLK exists only on STM32G0B0xx, and exists only to feed the
    MCO and MCO2 peripherals, so `q` is optional and the output is
	conditional.

When the user specifies `ClockSrc::PLL(PllConfig)`, `rcc::init()`
calls `PllConfig::init()` which initializes the PLL per [RM0454]. It
disables the PLL, waits for it to stop, enables the source
oscillator, configures the PLL, waits for it to lock, and then
enables the appropriate outputs. `rcc::init()` then switches the
clock source to PLLRCLK.

`rcc::init()` is now also resonsible for calculating and setting flash
wait states. SYSCLCK < 24 MHz is fine in the reset state, but 24-48 MHz
requires waiting 1 cycle and 48-64 MHz requires waiting 2 cycles. (This
was likely a blocker for anyone using HSE >= 24 MHz, with or without
the PLL.) Flash accesses are now automatically slowed down as needed
before changing the clock source, and sped up as permitted after
changing the clock source. The number of flash wait states also
determines if flash prefetching will be profitable, so that is now
handled automatically too.

[RM0454]: https://www.st.com/resource/en/reference_manual/rm0454-stm32g0x0-advanced-armbased-32bit-mcus-stmicroelectronics.pdf
2022-05-27 23:56:42 -05:00
chemicstry
1d951a54be Reimplement BufRead for BufferedUart 2022-05-26 14:02:55 +03:00
Dario Nieuwenhuis
a5aea995a8 WIP embassy-net v2 2022-05-25 19:56:22 +02:00
bors[bot]
7743b8e1ae
Merge #776
776: Automatically set ADC clock prescaler on v2 ADC to respect max frequency r=Dirbaio a=matoushybl



Co-authored-by: Matous Hybl <hyblmatous@gmail.com>
2022-05-19 04:00:23 +00:00
Matous Hybl
53f65d8b09 Automatically set ADC clock prescaler on v2 ADC to respect max frequency 2022-05-18 18:34:36 +02:00
Ralf
c90968bb70 stm32/rcc: Modify only relevant CFGR bits and keep the settings previously done.
PLL settings remained intact because these bits are not writable when PLL is enabled,
but prescaler settings were overwritten by selecting PLL as sysclk (CFGR.SW[1:0]).
2022-05-12 09:09:39 +02:00
Ralf
1a216958ac stm32/rcc: Set flash prefetch buffer and half cycle access according to AHB clock prescaler 2022-05-12 09:09:39 +02:00
Ralf
f4677469f9 stm32/usart: Data length is including parity. To get e.g. 8E1 you need to choose 9 data bits 2022-05-12 09:09:30 +02:00
Matous Hybl
01fb447e9d Allow maximal clock for F7 HCLK 2022-05-08 23:07:28 +02:00
bors[bot]
e9ab960ebf
Merge #760
760: stm32/gpio: Add support for `set_speed` for gpio v1 r=Dirbaio a=GrantM11235



Co-authored-by: Grant Miller <GrantM11235@gmail.com>
2022-05-08 19:53:31 +00:00
Grant Miller
acc1761637 Remove unnecessary cfg 2022-05-08 14:50:15 -05:00
Grant Miller
b230ac9c1a stm32/gpio: Add support for set_speed for gpio v1 2022-05-08 14:43:37 -05:00
Dario Nieuwenhuis
96d0eb9476 stm32: Fix stm32f107 build. 2022-05-08 21:37:37 +02:00
bors[bot]
a4bf190f2f
Merge #752
752: Replace embassy::io with embedded_io. r=Dirbaio a=Dirbaio

TODO:

- [x] Release embedded-io on crates.io
- [x] Remove git dep

Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2022-05-06 23:54:07 +00:00
Dario Nieuwenhuis
931a137f8c Replace embassy::io with embedded_io. 2022-05-07 01:45:54 +02:00
Matous Hybl
118532278c Add H7 flash and bootloader support 2022-05-06 21:57:15 +02:00
Matous Hybl
6d56f772e1 Add F7 flash and bootloader support 2022-05-06 21:57:15 +02:00
Matous Hybl
f3700b4e42 Refactor flash handling to different modules for different families 2022-05-06 21:57:15 +02:00
Matous Hybl
4f5088d79d Add support for F3 flash 2022-05-06 21:57:15 +02:00
Dario Nieuwenhuis
fc32b3750c Remove embassy_hal_common::usb.
The replacement is `embassy-usb`. There's a WIP driver for stm32 USBD in #709,
there's no WIP driver for stm32 USB_OTG. This means we're left without
USB_OTG support for now.

Reason for removing is I'm going to soon remove `embassy::io`, and
USB uses it. I don't want to spend time maintaining "dead" code
that is going to be removed. Volunteers welcome, either to update
old USB to the new IO, or write a USB_OTG driver fo the new USB.
2022-05-04 01:41:37 +02:00
Dario Nieuwenhuis
49ae26f384
Merge pull request #748 from embassy-rs/nrf-i2c-timeout
Misc HAL improvements.
2022-05-03 01:25:05 +02:00
Dario Nieuwenhuis
71e46d7efd stm32/gpio: add EH1.0 trait impls. 2022-05-03 00:52:48 +02:00
bors[bot]
6e129cf34f
Merge #747
747: stm32/adc/v4: Fix log statement r=Dirbaio a=GrantM11235



Co-authored-by: Grant Miller <GrantM11235@gmail.com>
2022-05-02 20:18:01 +00:00
Grant Miller
4bccd77849 stm32/adc/v4: Fix log statement 2022-05-02 15:14:49 -05:00
Dario Nieuwenhuis
a5f5c3a844 net: add functions to get current Eth and IP config 2022-05-02 16:19:34 +02:00
bors[bot]
d600f39260
Merge #743
743: Add PLL config support for F2 r=Dirbaio a=Gekkio

- minor changes to make the F2 RCC API a bit more flexible
- low-level PLL config with assertions based on datasheet specs. It shouldn't be very difficult to later add a "reverse API" where you pass the clocks you want to a function and it generates a `PLLConfig` struct for you
- PLL API tested on my custom board with 12 MHz HSE as source for PLL to generate max clocks for SYSCLK/AHB/APB/APB1/PLL48
- the example *should* work but is untested since I don't have the Nucleo board 😞 

Co-authored-by: Joonas Javanainen <joonas.javanainen@gmail.com>
2022-04-30 21:08:43 +00:00
Joonas Javanainen
e88559c5ca
Use defmt-friendly error handling 2022-04-30 11:41:17 +03:00
Dario Nieuwenhuis
804b20c5af stm32/eth: make "ethmac" vs "eth" consistent in RCC regs. 2022-04-30 04:49:57 +02:00
David Lenfesty
5e6c4ae024 embassy-stm32/eth: consolidate v1a/v1c and add v1b
The only differences between v1a and v1c were clocks and GPIO, v1b will
likely work out of the box (or simply need minor tweaks)
2022-04-30 04:49:24 +02:00
David Lenfesty
2e7b42fc5b embassy-stm32/eth: convert LAN8742 driver to generic SMI driver
SMI Ethernet PHYs all share a common base set of registers that can do
90% of all tasks. The LAN8742 driver used some vendor-specific
registers to check link negotiation status, but the need for that was
debatable, so I migrated it to a generic driver instead, anybody who
wants extra functionality can copy it and impl their own on top of it.
2022-04-30 04:49:24 +02:00
David Lenfesty
905b40e212 embassy-stm32/eth/v1a: configure pins correctly for f107
v1a works correctly!
2022-04-30 04:49:24 +02:00
David Lenfesty
0d2ef1099b initial work porting eth to f107 2022-04-30 04:49:24 +02:00
David Lenfesty
f30e5d2d3f Initial import to v1a, does not compile 2022-04-30 04:49:24 +02:00
Joonas Javanainen
07ad52162b
Add PLL config support for F2 2022-04-29 18:21:40 +03:00
Joonas Javanainen
0cfe1dc9df
Move HSE config out of main clock mux
This makes the configuration more flexible and closer to the underlying
configuration register structure. For example, we could use HSI for the
system clock, but use HSE to output a clock with MCO.
2022-04-29 17:51:18 +03:00
Matous Hybl
7538f57d62 Remove unnecessary feature gating for giant transfers in DCMI 2022-04-27 16:53:20 +02:00
Ulf Lilleengen
da61611f8f Add bootloader to CI 2022-04-27 15:17:18 +02:00
Ulf Lilleengen
484e0acc63 Add stm32 flash + bootloader support
* Add flash drivers for L0, L1, L4, WB and WL. Not tested for WB, but
should be similar to WL.
* Add embassy-boot-stm32 for bootloading on STM32.
* Add flash examples and bootloader examples
* Update stm32-data
2022-04-27 15:17:18 +02:00
Dario Nieuwenhuis
009bb8e4e1 stm32: add stm32u5 GPDMA, SPIv4 support, add HIL tests. 2022-04-27 01:16:14 +02:00
Matous Hybl
945fa0871f Implement giant (chunked) DMA transfers for DCMI. 2022-04-25 14:30:43 +02:00
Dario Nieuwenhuis
3251a21fb7 Switch to crates.io embedded-hal, embedded-hal-async.
This temporarily removes support for the async UART trait, since it's
not yet in embedded-hal-async.
2022-04-22 19:58:24 +02:00
bors[bot]
6d0e6d563d
Merge #714
714: add more clock options for l4 and l5 r=Dirbaio a=ant32

- added an assert so it panics if pll48div is not 48Mhz
- added MSI as a clock source for PLL
- removed hsi48 option for MCUs mentioned in l4 rcc presentation
- copied some code from l4 to l5, but don't have a way of testing it.

Co-authored-by: Philip A Reimer <antreimer@gmail.com>
2022-04-12 21:42:36 +00:00
bors[bot]
77c2b151c2
Merge #715
715: stm32/dac: Check proper channel r=Dirbaio a=michalsrb

Small fix. Otherwise it panics when trying to use channel 1 if channel 2 does not exist.

Co-authored-by: Michal Srb <michalsrb@gmail.com>
2022-04-12 20:57:36 +00:00
Matous Hybl
371f3ef419 Add ADC support for H7 2022-04-12 22:25:00 +02:00
Michal Srb
c1914a477d stm32/dac: Check proper channel 2022-04-12 12:49:06 +02:00
Philip A Reimer
d90ecbbe40 add more clock options for l4 and l5 2022-04-11 19:11:02 -06:00
Philip A Reimer
d8860c0b80 add stm32l4 hsi48 and usb example 2022-04-09 14:55:03 -06:00
Dario Nieuwenhuis
8b757e1aec Add stm32wlexx support 2022-04-08 03:43:58 +02:00
Dario Nieuwenhuis
50ff63ab88 Add STM32L5 support. 2022-04-08 03:11:38 +02:00
Matous Hybl
eb6910fa86 Reexport unborrow macro in HALs 2022-04-07 12:57:02 +02:00
Philip A Reimer
1f59f8e7d0 add pllsai1 and allow for 120Mhz clock on stm32l4+ 2022-04-01 22:42:43 -06:00
chemicstry
d052631118 Fix STM32 timer interrupt bug 2022-03-30 00:27:33 +03:00
Joonas Javanainen
a608d0deaf
Add minimal STM32F2 RCC
No support for PLL or other clocks than SYSCLK/AHB/APB1/APB2
2022-03-27 18:40:49 +03:00
bors[bot]
37ada65a33
Merge #669
669: Add SDMMC v1 and SDIO support r=Dirbaio a=chemicstry

SDMMC v2 peripheral is an extension of SDMMC v1 (or SDIO) so I managed to reuse most of the code, with some cfg's.

Apart from small differeces in registers, the biggest change is that v2 uses internal DMA, while v1 has to use shared DMA peripheral. This makes code a bit uglier, because DMA channel for v1 has to be passed around. Not sure if it's possible to make it any cleaner.

This also adds `TransferOptions` structure to DMA, because SDMMC v1 requires setting peripheral flow control and burst transfers. Let me know if some alternative way would be prefered.

I tested this on STM32F429ZIT6 (with sd card) and STM32H745ZIT6 (with oscilloscope).

Depends on: https://github.com/embassy-rs/stm32-data/pull/130

Co-authored-by: chemicstry <chemicstry@gmail.com>
2022-03-20 20:19:58 +00:00
bors[bot]
f0a071790d
Merge #673
673: Inline GPIO functions r=Dirbaio a=nviennot

All GPIO functions are monomorphized (per pin). Inlining these make the ROM smaller when using opt-level="z"

Co-authored-by: Nicolas Viennot <nicolas@viennot.biz>
2022-03-19 20:34:07 +00:00
Nicolas Viennot
4aba87f983 Inline GPIO functions
All GPIO functions are monomorphized (per pin). Inlining these make the
ROM smaller when using opt-level="z"
2022-03-19 14:06:11 -04:00
chemicstry
bdeb537ffa Fix compile for stm32wb 2022-03-18 01:33:39 +02:00
chemicstry
b30a42aff8 Fix RCC safety and add reset to DAC 2022-03-18 01:16:07 +02:00
chemicstry
ca88ace98d Reset peripherals on enable 2022-03-18 00:46:46 +02:00
chemicstry
d26b751edc Add comments 2022-03-17 19:41:44 +02:00
chemicstry
051c6350ea Make UART futures Send 2022-03-17 18:23:47 +02:00
chemicstry
24a9e19062 More cleanup 2022-03-17 01:12:29 +02:00
chemicstry
9d71acc49e Cleanup 2022-03-16 23:55:07 +02:00
chemicstry
ea467e0acb Rename DMA trait 2022-03-16 20:30:57 +02:00
chemicstry
8a8e5c4b73 Fix SDMMC v2 and add H7 example 2022-03-16 20:20:39 +02:00
chemicstry
48fc48ea7d Fix BDMA 2022-03-16 19:41:34 +02:00
chemicstry
bf4a38ac06 Use RCC frequency instead of config 2022-03-16 19:09:37 +02:00
chemicstry
6d547b1143 SDIO working on stm32f4 2022-03-16 18:52:27 +02:00
chemicstry
34b5175d2c Add more options to DMA 2022-03-16 18:52:06 +02:00
chemicstry
2d224cf6a0 Update 2022-03-15 19:58:19 +02:00
Ulf Lilleengen
e09bde9345 Add support for splitting stm32 usart into TX and RX
* Keeps existing API for usart, but wraps it in Tx and Rx sub-types
* Adds split() method similar to nRF for getting indepdendent TX and RX
  parts
* Implements e-h traits for TX and RX types
* Add stm32h7 example
2022-03-15 10:35:37 +01:00
Dario Nieuwenhuis
1dc618f0e4 stm32/spi: fix blocking transfer hanging after async. 2022-03-15 04:13:33 +01:00
Grant Miller
49ef19c0b2 stm32/spi: Clear rx fifo in blocking methods 2022-03-14 21:55:37 -05:00
Dario Nieuwenhuis
059b164234 stm32/spi: do not clear rxfifo in SPIv3, the hw already does it. 2022-03-15 02:37:08 +01:00
Dario Nieuwenhuis
4579192832 stm32/spi: fix hang in SPIv3 by not waiting for rxfifo empty in finish_dma. 2022-03-15 02:36:34 +01:00
Dario Nieuwenhuis
306110f56e stm32/spi: implement async trasnfer_in_place 2022-03-15 00:40:48 +01:00
Grant Miller
f1d6c95205 rustfmt 2022-03-14 18:22:41 -05:00
Grant Miller
71632648c7 Fix zero-length-slice bugs 2022-03-14 18:14:55 -05:00
Grant Miller
15c533fe2a Fix async write bug 2022-03-14 18:04:31 -05:00
Grant Miller
6e00c58854 Make all functions generic over word size 2022-03-14 16:53:50 -05:00
Grant Miller
f0b62bc8e0 Use const REGS 2022-03-14 15:56:08 -05:00
Grant Miller
482ffea4dd Finish unification 2022-03-14 15:56:08 -05:00
Grant Miller
406b1b3dd2 Finish matching versions 2022-03-14 15:56:08 -05:00
Grant Miller
7cd6f00a90 Add set_txdmaen and set_rxdmaen functions 2022-03-14 15:56:08 -05:00
Grant Miller
444b37fcdf Add flush_rx_fifo function 2022-03-14 15:56:08 -05:00
Grant Miller
683c11f399 Call set_word_size before disabling SPE 2022-03-14 15:56:08 -05:00
Dario Nieuwenhuis
9bad9365dc Update rust nightly, embedded-hal 1.0, embedded-hal-async. 2022-03-11 00:38:07 +01:00
Dario Nieuwenhuis
77841a4676 stm32/dma: panic on DMA error. 2022-03-09 03:19:05 +01:00
Grant Miller
8c45c98e41 stm32: Refactor DMA interrupts
Previously, every dma interrupt handler called the same `on_irq`
function which had to check the state of every dma channel.

Now, each dma interrupt handler only calls an `on_irq` method for its
corresponding channel or channels.
2022-03-08 14:18:31 -06:00
Timo Kröger
372b71890d [can] Typo fix: l7 -> f7 2022-03-05 09:46:06 +01:00
Timo Kröger
d6d25e6470 [can] cfgs for naming inconsistencies
Approach is similar to USB OTG.
STM32L49x and STML4Ax have CAN1 and CAN2.
All others STM32L4xx do only have CAN1.
STM32F72x and STM32F73x are the only F7 devices with only CAN1.
2022-03-05 09:46:06 +01:00
Timo Kröger
6929350552 [can] Update macrotable comment
The chip description are corrected in:
https://github.com/embassy-rs/stm32-data/pull/123
2022-03-05 09:46:06 +01:00
Timo Kröger
4c30543938 [can] Do not use wildcard reexport for bxcan 2022-03-05 09:46:06 +01:00
bors[bot]
9ebf7eee6d
Merge #652 #653
652: Use new stm32-data registers and fix AHB clock calculation r=Dirbaio a=msamsonoff

This is the follow-on to my PR against stm32-data that added new register enums for the G0. I have updated the G0 RCC module to use those new enums.

I have also fixed an issue with the calculation of the AHB clock rate. 32 is not available as an AHB prescaler. The sequence jumps from 16 to 64. The original bit shifting math did not account for this gap. I have replaced it with a `match` instead.

653: Fixes for rustdoc building. r=Dirbaio a=Dirbaio



Co-authored-by: Matthew W. Samsonoff <matt.samsonoff@gmail.com>
Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2022-03-04 17:07:04 +00:00
Dario Nieuwenhuis
609975f821 rustfmt 2022-03-04 18:04:12 +01:00
Matthew W. Samsonoff
047ff9a2f2 Use new stm32-data registers and fix AHB clock calculation
The original code for calculating the AHB clock did not account for the gap in
prescaler values (32 is not an available value.) The bit shifting and math has
been replaced by a `match`.
2022-03-04 18:03:55 +01:00
Dario Nieuwenhuis
53d9a0b516 stm32: exclude spammy files from docs by prefixing with _.
These files end up containing chip-specific info, so they deduplicate
really badly when building docs for all 1200 chips.

The doc generator removes files starting with `_`.
2022-03-04 18:03:41 +01:00
Dario Nieuwenhuis
94b232cf88 docs: prevent inline doc spam for reexports. 2022-03-04 18:03:41 +01:00
Matous Hybl
0172ca5b81 stm32: Add support for using TIM12 and TIM15 as time driver 2022-02-28 19:20:22 +01:00
Matous Hybl
a88c5e716e stm32: Register access for timers now doesn't require self 2022-02-28 16:20:42 +01:00
Dario Nieuwenhuis
dd828a7a92 stm32: move macrotables to embassy-stm32 build.rs 2022-02-26 03:23:09 +01:00
Dario Nieuwenhuis
e6299549a0 stm32/i2c: use one static per instance instead of an array. 2022-02-26 01:23:17 +01:00
Dario Nieuwenhuis
8d46d31824 stm32/dbgmcu: do not use macrotable. 2022-02-26 01:20:42 +01:00
Timo Kröger
48f700b35c stm32 usart: Fix RX interrupt flag handling
* On v1 interrupts cannot be cleared individually.
  Instead they are cleared implicitly by reading or writing DR (which we do now).
* Multiple error flags can be set at the same time:
  Handle them all in one go intstead of re-entering the ISR for each one so that
  we do not lose any error flags on v1 hardware.
* Wake when the RX buffer becomes full: This allows fast running chips to pull data
  from the buffer before receiving the next byte.
2022-02-25 14:32:39 +01:00
Dario Nieuwenhuis
0ad7a3aa6f stm32: fix chips without dbgmcu (wl55 cm0 core) 2022-02-25 01:16:23 +01:00
Dario Nieuwenhuis
ea5cd19c30 stm32: fix build for h7ab 2022-02-24 06:28:29 +01:00
Dario Nieuwenhuis
2a246be06e stm32/time_driver: use trait impls from the main timer mod. 2022-02-24 06:28:29 +01:00
Dario Nieuwenhuis
e8ca5f9b04 stm32/rcc: fix build on l0 chips without CRS 2022-02-24 06:28:29 +01:00
Dario Nieuwenhuis
bf80504ac7 stm32: centralize gpio reg access in the gpio module. 2022-02-24 02:49:20 +01:00
Dario Nieuwenhuis
1b3c34b923 stm32/gpio: fix wrong conf for AF input. 2022-02-24 00:37:15 +01:00
Dario Nieuwenhuis
17e77ede3f stm32f1: fix wrong AF type in uart, can. 2022-02-24 00:37:15 +01:00
Dario Nieuwenhuis
052f370de9 stm32: move ADC, DAC pin impls to build.rs 2022-02-23 20:21:28 +01:00
Dario Nieuwenhuis
30ce71127a stm32: move MCO pin impls to build.rs 2022-02-23 19:54:46 +01:00
Dario Nieuwenhuis
1e69a8c484 stm32: move pin trait impls from macrotables to build.rs 2022-02-23 19:54:46 +01:00
Dario Nieuwenhuis
b4abb1f5c2 stm32: move dma trait impls from macrotables to build.rs 2022-02-23 19:16:37 +01:00
Dario Nieuwenhuis
2abb04d4d1 stm32/rcc: fix f3 build failure. 2022-02-23 03:42:46 +01:00
Dario Nieuwenhuis
39d06b59cd Update stm32-data 2022-02-14 02:12:06 +01:00
bors[bot]
eb922c4655
Merge #608
608: stm32f4: add adc + example r=Dirbaio a=ain101

Example tested on stm32f407vg Discovery Board.
minimal adc: no vref, dma, complex sequence

Co-authored-by: Frederik <frederik@frederik.at>
2022-02-13 11:44:59 +00:00
Frederik
7a3d34c1ed fix build for stm32f410tb 2022-02-12 23:56:50 +01:00
Frederik
6f0488cbe7 remove unnecessary mod 2022-02-12 23:55:58 +01:00
Dario Nieuwenhuis
340eb4eead stm32: add rust stable support 2022-02-12 02:45:52 +01:00
bors[bot]
f2eb438905
Merge #615
615: rp: remove OptionalPin r=Dirbaio a=Dirbaio

Mirror of https://github.com/embassy-rs/embassy/pull/605 for rp2040

Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2022-02-12 00:46:40 +00:00
Dario Nieuwenhuis
4a75475cfc stm32: remove unused sealed::OptionalPin 2022-02-12 01:34:09 +01:00
Dario Nieuwenhuis
6c925b2342 blocking_mutex: refactor to work on stable. No GATs, and can be constructed in const. 2022-02-12 01:16:31 +01:00
Frederik
e4f240823d adc cleanup retval 2022-02-11 17:48:32 +01:00
Frederik
7a3d28ad00 stm32f4: add adc + example
Example tested on stm32f407vg Discovery Board.
minimal adc: no vref, dma, complex sequence
2022-02-10 23:28:41 +01:00
Dario Nieuwenhuis
b99ab3d5d9 stm32: Add standard crate-wide macros for pin/dma traits, switch all drivers to use them. 2022-02-10 21:38:03 +01:00
Dario Nieuwenhuis
a8bd3ab952 Add missing + 'd on unborrows. 2022-02-10 16:06:42 +01:00
Dario Nieuwenhuis
550da471be stm32: Remove OptionalPin
The idea behind OptionalPin has a few problems:

- you need to impl the signal traits for NoPin which is a bit weird https://github.com/embassy-rs/embassy/blob/master/embassy-stm32/src/dcmi.rs#L413-L416
- you can pass any combination of set/unset pins, which needs checking at runtime  https://github.com/embassy-rs/embassy/blob/master/embassy-stm32/src/dcmi.rs#L130

The replacement is to do multiple `new` constructors for each combination of pins you want to take.
2022-02-10 02:38:10 +01:00
bors[bot]
1d265b73b2
Merge #601
601: [part 1/n] Change macrotables to build.rs codegen r=lulf a=Dirbaio

This PR replaces the "macrotables" (the macros like `stm32_data::peripherals!`) with a `const METADATA`.

Macrotables had some problems:

- Hard to debug
- Somewhat footgunny (typo the "pattern" and then nothing matches and the macro now expands to nothing, silently!)
- Limited power
  - Can't count, so we had to add a [special macrotable for that](f50f3f0a73/embassy-stm32/src/dma/bdma.rs (L26)).
  - Can't remove duplicates, so we had to fallback to [Rust code in build.rs](f50f3f0a73/embassy-stm32/build.rs (L105-L145))
  - Can't include the results as a listto another macro, so again [build.rs](https://github.com/embassy-rs/embassy/blob/master/embassy-stm32/build.rs#L100-L101).

They work fine for the 95% of cases, but for the remaining 5% we need Rust code in build.rs. So we might as well do everything with Rust code, so everything is consistent.

The new approach generates a `const METADATA: Metadata = Metadata { ... }` with [these structs](https://github.com/embassy-rs/embassy/blob/unmacrotablize/stm32-metapac-gen/src/assets/metadata.rs) in `stm32-metapac`. `build.rs` can then read that and generate whatever code.


Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2022-02-09 15:27:35 +00:00
bors[bot]
d91bd0b9a6
Merge #602
602: Add stm32 USB OTG peripherals r=Dirbaio a=chemicstry

Fixes #557. This is similar to #580, but for synopsys IP.

I could add examples to other chips, but I have no way of testing them. The F4 example is tested and working.

Co-authored-by: chemicstry <chemicstry@gmail.com>
2022-02-09 00:29:00 +00:00
chemicstry
10981ee809 Cleanup 2022-02-09 02:10:54 +02:00
chemicstry
1f81a69347 Merge USB FS and HS peripherals. Add ULPI. 2022-02-09 02:02:23 +02:00
Dario Nieuwenhuis
8160af6af9 stm32: replace peripheral_rcc! macrotable with build.rs 2022-02-09 00:58:17 +01:00
Dario Nieuwenhuis
d1a9680422 stm32: change interrupt declarations from macrotables to build.rs. 2022-02-09 00:45:52 +01:00
Matous Hybl
d37d714314 stm32: Add support for FMC 2022-02-08 17:30:20 +01:00
Matous Hybl
fee1de109d Fix RCC configuration for H7. 2022-02-08 14:36:53 +01:00
chemicstry
db0d798b48 Add stm32 USB OTG peripherals 2022-02-08 01:46:32 +02:00
Dario Nieuwenhuis
fbaa7e59d5 stm32/dma: fix interrupt codegen for new stm32-data 2022-02-05 03:03:32 +01:00
Dario Nieuwenhuis
f8b8872fa6
Merge pull request #593 from embassy-rs/remove-traits
traits: migrate Delay to embedded-hal 1.0+async, remove Rng and Flash.
2022-02-05 01:53:01 +01:00
Greg V
8bb41a3281 stm32f3: fix nonexistent cfg tests
The rcc code was taken from stm32-rs which uses 'x' features, but
embassy uses features with full chip names.

Add these 'x' wildcards as cfgs and use them in rcc.
They will be useful for USB too.
2022-02-02 22:53:03 +03:00
Dario Nieuwenhuis
0719b05d63 traits: migrate Delay to embedded-hal 1.0+async, remove Rng and Flash. 2022-01-27 00:08:02 +01:00
Ulf Lilleengen
4032fc0655 Support unstable-trait feature for stm32 2022-01-26 22:39:06 +01:00
Sam Lakerveld
3fc54236ea
stm32/i2c: allow empty transfers with async api 2022-01-25 16:28:49 +01:00
Dario Nieuwenhuis
a8580ec78a stm32/rcc: fix stm32f410 2022-01-24 00:50:35 +01:00
Dario Nieuwenhuis
533ceb707c stm32: add tim4, tim5 support for time-driver (stm32f410 doesn't have tim2, tim3) 2022-01-24 00:50:10 +01:00
Dario Nieuwenhuis
79f60adbfb stm32: add time-driver-any cargo feature that automatically picks one available timer. 2022-01-24 00:24:53 +01:00
Dario Nieuwenhuis
889d757ab8 stm32/spi: expose all functionality as inherent methods. 2022-01-19 17:59:55 +01:00
Dario Nieuwenhuis
3d27a0e7cb stm32/dma: make lowlevel api take ptrs instead of slices. 2022-01-19 17:59:55 +01:00
Dario Nieuwenhuis
97ab859f00 stm32/i2c: expose all functionality as inherent methods. 2022-01-19 17:59:55 +01:00
Dario Nieuwenhuis
c949519714 stm32/usart: expose all functionality as inherent methods. 2022-01-19 17:59:55 +01:00
Dario Nieuwenhuis
ade44e91c4 stm32/exti: add wait_for_high, wait_for_low. 2022-01-19 17:59:55 +01:00
Dario Nieuwenhuis
b526addf7b stm32/exti: expose all functionality as inherent methods. 2022-01-19 17:59:55 +01:00
Dario Nieuwenhuis
58fc64722c stm32/gpio: expose all functionality as inherent methods. 2022-01-19 17:59:55 +01:00
Dario Nieuwenhuis
52e156b429 stm32: use critical_section instead of cortex_m::interrupt 2022-01-19 17:59:55 +01:00
Matous Hybl
4988dfe981 Make advanced timer trait not require general purpose timer trait as the timers are too different. 2022-01-18 11:18:54 +01:00
Greg V
9fcc207629 stm32l1/rcc: fix clock frequency assertion
It was comparing a number in Hz (!) to "32" (MHz).
embassy-stm32's units don't work like those used by stm32-hal :/
2022-01-14 22:59:57 +03:00
Greg V
456b56d4fd stm32l1/rcc: set required flash bits for high frequencies
As is done for lots of other families
2022-01-14 22:59:57 +03:00
Matous Hybl
66e46d8012 Add the possibility to reconfigure Spi mode and bit order configuration on the fly. 2022-01-14 12:50:58 +01:00
Matous Hybl
e07df92651 Make RCC accessible using low-level API. 2022-01-13 16:12:45 +01:00
Matous Hybl
16d09f074a Add simple PWM, add PWM pin definitions also accessible from low-level API. 2022-01-13 16:05:54 +01:00
Matous Hybl
a1f7a94c69 Add low level timer API. 2022-01-13 16:05:54 +01:00
Ulf Lilleengen
2bc105803a Make exti an optional feature
* Add embassy-stm32 build with exti
* Add exti to examples
2022-01-12 14:28:10 +01:00
Dario Nieuwenhuis
3486d59d73 stm32: remove Dbgmcu from public API.
The use case is already covered by `config.enable_debug_during_sleep`.
2022-01-05 00:00:44 +01:00
Dario Nieuwenhuis
2eb0cc5df7 stm32/rcc: remove Rcc struct, RccExt trait.
All the RCC configuration is executed in init().
2022-01-05 00:00:44 +01:00
Dario Nieuwenhuis
c3fd9a0f44 stm32/rcc: f4/f7 cleanup and make a bit more consistent. 2022-01-04 21:17:17 +01:00
Dario Nieuwenhuis
b06e705a73 stm32/rcc: change family-specific code from dirs to single files.
Consistent with how other peripherals handle their versions.
2022-01-04 19:28:15 +01:00
Dario Nieuwenhuis
89b009b11d stm32h7/rcc: remove unneeded DMA enable settings.
These are automatically enabled by dma::init().
2022-01-04 13:31:30 +01:00
Dario Nieuwenhuis
5d2f40b337 stm32wl/rcc: remove unneded gpio enables in RCC.
These are already done by gpio::init().
2022-01-04 13:31:30 +01:00
Dario Nieuwenhuis
cdc66e110f stm32/rcc: remove builders on Config.
This makes API consistent with other Config structs in Embassy, where
the convention is to not use builders.
2022-01-04 13:31:30 +01:00
bors[bot]
cdfd128185
Merge #545
545: Add adapter for implementing async traits for blocking types r=lulf a=lulf

This allows writing drivers relying on async traits, while still
functioning with implementations that already implement the embedded-hal
traits.

Co-authored-by: Ulf Lilleengen <lulf@redhat.com>
2022-01-03 14:17:21 +00:00
bors[bot]
c0e94a7042
Merge #563
563: Initial ADC support for on STM32F1xx  r=Dirbaio a=sjoerdsimons

Add an ADC implementation for F1 based chips. Primarily tested using ADC1, proper functionality for ADC2 probably needs some extra work as it's mainly a slave and can't e.g. measure vrefint by itself.

Needs https://github.com/embassy-rs/stm32-data/pull/115

Co-authored-by: Sjoerd Simons <sjoerd@collabora.com>
Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2022-01-01 11:45:23 +00:00
bors[bot]
c20ef419a6
Merge #558
558: Port buffered uart to v1 stm32 hardware r=Dirbaio a=DCNick3

#526 seems to suggest that it will be rewritten for DMA support, but I am not sure how to implement it and the port was quite straightforward, so here it is. It might be immediately useful before DMA version will be implemented

Note that I have not tested this on v2 hardware

Co-authored-by: Nikita Strygin <nikita6@bk.ru>
2022-01-01 10:51:14 +00:00
Sjoerd Simons
92f2c6d09c adc: Implement support for f1 ADC block
Add basic support for the STM32F1xx ADC blocks.
2021-12-30 10:51:54 +01:00
Sjoerd Simons
a93b1141e9 stm32f1: Store adc clock rate in Clocks struct 2021-12-30 10:50:28 +01:00
Ben Gamari
8da6471a50 stm32/dac: Fix disable_channel
Previously disable_channel enabled rather than disabled the requested
channel due to an apparent copy-paste error. Refactor to eliminate this
sort of issue by construction.
2021-12-28 23:27:59 -05:00
Nikita Strygin
a94932be02 Mark clear_interrupt_flag as unsafe 2021-12-26 18:29:41 +03:00
Nikita Strygin
6b08c70273 Port buffered uart to v1 stm32 hardware
- No DMA
- Create clear_interrupt_flag function to
    handle differences between v1 and v2 hardware
2021-12-26 18:13:19 +03:00
Dario Nieuwenhuis
d1740b10f0 Lower some verbose logs to trace. 2021-12-23 13:43:14 +01:00
Ulf Lilleengen
3811c0a401 Add adapter for implementing async traits for blocking types
This allows writing drivers relying on async traits, while still
functioning with implementations that already implement the embedded-hal
traits.

Add examples to stm32l4 for using this feature.
2021-12-17 12:54:51 +01:00
Ulf Lilleengen
2bbd1ddb8a Remove unneeded rustfmt::skip 2021-12-16 11:37:53 +01:00
Ulf Lilleengen
985c11fad5 Update rust-toolchain 2021-12-16 11:34:20 +01:00
bors[bot]
d5a3064c2c
Merge #540
540: Initial support for STM32F3 r=Dirbaio a=VasanthakumarV

The [companion PR](https://github.com/embassy-rs/stm32-data/pull/109) in `stm32-data` should be merged before this PR.
The examples were tested on an STM32F303VC MCU.

Co-authored-by: VasanthakumarV <vasanth260m12@gmail.com>
Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2021-12-16 07:30:03 +00:00
Grant Miller
6597e67036 Add finish_dma function 2021-12-14 17:46:25 -06:00
Grant Miller
a13a7a6616 Replace wait_for_idle with spin_until_idle 2021-12-14 17:46:25 -06:00
Grant Miller
e75cb1a564 Regs type alias 2021-12-14 15:39:00 -06:00
Grant Miller
b06658c195 Refactor new 2021-12-14 15:39:00 -06:00
VasanthakumarV
78c5d65ca9 [lint] Add newline in pwr file 2021-12-13 18:16:58 +05:30
VasanthakumarV
3f33d307ff [feature] Add rcc register support for F3 2021-12-13 14:50:13 +05:30
VasanthakumarV
e2c074d133 [feature] Add pwr register support for F3 2021-12-13 13:49:41 +05:30
huntc
45ef944457 Stm flush required implementing also, along with std alloc split 2021-12-10 15:11:41 +11:00
Matous Hybl
1dd5a71c07 Add DCMI peripheral support. 2021-12-09 12:56:39 +01:00
Dario Nieuwenhuis
4ddd23d623 stm32/usart: unify v1 and v2 2021-12-08 05:12:48 +01:00
Dario Nieuwenhuis
022c4cb739 stm32/dma: simplify impls a bit. 2021-12-08 03:30:07 +01:00
Dario Nieuwenhuis
b316d2620c stm32/dma: improve trait docs, seal Word. 2021-12-08 03:18:15 +01:00
Dario Nieuwenhuis
6179da6b9c stm32/dma: eagerly start transfers when calling the functions.
`async fn`s do nothing until polled, but we want the DMA transfer to
immediately start in this case. Drivers rely on it. Some require special
orders, such as "start DMA, start SPI, then wait for DMA" which is awkward
to do without eager start.

Also use a manually-impl'd future, this allows getting rid of the "double"
Unborrow channel clone.
2021-12-08 03:04:39 +01:00
Dario Nieuwenhuis
4e349d0f5d stm32/dma: use the right waker slot number for DMA2 (must add 8) 2021-12-08 01:54:31 +01:00
Dario Nieuwenhuis
fd2fe62b5f stm32/dma: rename is_stopped to is_running.
Note that this does NOT invert the result of `en()` because it was
wrong before.
2021-12-08 01:51:39 +01:00
Matous Hybl
b2910558d3 Refactor DMA traits. 2021-12-07 21:43:47 +01:00
Joshua Salzedo
e2719aba10 Further extend the dma channel trait 2021-12-07 21:43:47 +01:00
Joshua Salzedo
93e047ede2 cargo fmt 2021-12-07 21:43:47 +01:00
Joshua Salzedo
3411039cb9 Implement extended Channel trait to bdma.rs 2021-12-07 21:43:47 +01:00
Joshua Salzedo
2d2c6d0e01 Implement extended Channel trait to dma.rs 2021-12-07 21:43:47 +01:00
Joshua Salzedo
3272987d92 Expand channel trait 2021-12-07 21:43:47 +01:00
Ulf Lilleengen
f9ac0c8047 Add back MISO flush 2021-12-07 09:40:45 +01:00
Grant Miller
79baa04118 Implement blocking traits with a macro 2021-12-07 00:03:52 -06:00
Grant Miller
bf1f80afa1 Unify blocking trait impls 2021-12-07 00:03:52 -06:00
Grant Miller
3a17e3a2a5 Move async trait impls to mod 2021-12-07 00:03:52 -06:00
Grant Miller
20d2151b1d check_error_flags function 2021-12-07 00:03:52 -06:00
Grant Miller
496579b48b Move Word trait to mod 2021-12-07 00:03:52 -06:00
Grant Miller
7c78247be3 v2: set frxth and ds in new 2021-12-06 22:36:53 -06:00
Grant Miller
d76bc45e30 Move Spi drop impl to mod 2021-12-06 17:19:55 -06:00
Grant Miller
bd9e730024 Move set_word_size to mod 2021-12-06 16:47:08 -06:00
Grant Miller
a35b7d90bc Add tx_ptr and rx_ptr methods 2021-12-06 16:33:06 -06:00
Grant Miller
a35f337bd6 Move Spi::new and Spi::compute_baud_rate to mod 2021-12-06 15:19:24 -06:00
Grant Miller
75374ce7e8 Fix ssoe in v1 2021-12-06 14:57:53 -06:00
Grant Miller
e1cccc8391 Move Spi to mod (without NoDma defaults) 2021-12-06 14:47:50 -06:00
Grant Miller
aeb69a7665 Track current word size in v2 and v3 also 2021-12-06 14:24:02 -06:00
Grant Miller
d51885c0eb Move WordSize methods to mod 2021-12-06 14:13:25 -06:00
Grant Miller
d426caefbf Move NoPin impls from v1 to mod 2021-12-06 14:02:21 -06:00
Ulf Lilleengen
81ec4c82fd Flush MISO before transfer operation 2021-12-03 09:53:28 +01:00
Matous Hybl
6e0eb33ea8 Downcast timer to GP16 for time drivers. 2021-12-02 18:07:05 +01:00
Matous Hybl
f0cb77443c Fix wrong pin configuration in STM32's SPI v3. 2021-12-01 22:18:14 +01:00
Dario Nieuwenhuis
b0fabfab5d Update stm32-data: rcc regs info comes from yamls now. 2021-11-29 02:28:02 +01:00
Ulf Lilleengen
25b49a8a2a Remove common clock types
Different STM32 RCC peripherals have different capabilities and register
values. Define types for each RCC types inside each module to ensure
full range of capabilities for each family can be used
2021-11-28 16:46:08 +01:00
Dario Nieuwenhuis
006e567716 stm32/pwm: allow using the advanced timer instances too. 2021-11-27 03:06:53 +01:00
Dario Nieuwenhuis
d7d1258411 stm32/pwm: small cleanups 2021-11-27 03:05:10 +01:00
Dario Nieuwenhuis
22fad1e7bc stm32/pwm: impl instance/pin for all chips 2021-11-27 03:04:50 +01:00
Ben Gamari
8211d58ee2 stm32/pwm: initial commit 2021-11-27 02:50:30 +01:00
Dario Nieuwenhuis
88d4b0c00d stm32: add stm32g4 support. 2021-11-27 02:34:23 +01:00
Ulf Lilleengen
cd9a1d547c Ensure SPI DMA write is completed
Fix a bug where DMA writes were not fully completed and only a single
byte out of two were written.
2021-11-24 14:59:18 +01:00
Wilfried Chauveau
eac604accd
Fix missing lifetime bounds 2021-11-21 10:10:28 +00:00
Dario Nieuwenhuis
24e5013c00 Allow unused to fix build failure in u5 2021-11-17 21:43:05 +01:00
Bob McWhirter
c2da498263 Update to defmt 3.0ish.
Lots of gitrevs deps.
2021-11-15 11:09:08 -05:00
bors[bot]
8193885cb5
Merge #482
482: Add MCO peripheral. r=Dirbaio a=matoushybl

This PR adds an abstraction over STM32 RCC feature called MCO (Microcontroller Clock Output). The clock output can bind to several clock sources and then can be scaled using a prescaler.

Given that from the embassy ecosystem the RCC is generaly invisible to the user, the MCO was implemented as a separate peripheral bound to the pin where the clock should appear.

Co-authored-by: Matous Hybl <hyblmatous@gmail.com>
2021-11-11 16:20:02 +00:00
Matous Hybl
c14642cffc Add MCO peripheral. 2021-11-11 11:34:09 +01:00
bors[bot]
96e2f0dfc5
Merge #468
468: Add v1c ethernet driver for the STM32F7 family. r=Dirbaio a=matoushybl



Co-authored-by: Matous Hybl <hyblmatous@gmail.com>
2021-11-10 22:07:38 +00:00
Matous Hybl
f0ba79059e Add v1c ethernet driver for the STM32F7 family. 2021-11-10 10:16:46 +01:00
Bob McWhirter
12a64b867b More support for U5 PWR (ish), RCC, and FLASH (ish). 2021-11-08 14:27:33 -05:00
Bob McWhirter
5f124ec49f Update U5 to init RCC. 2021-11-08 14:20:51 -05:00
Matous Hybl
9b5d9fbfca Fix v2 ethernet pin definitions. Fix ethernet example for H7 nucleos. 2021-11-04 16:25:30 +01:00
Bob McWhirter
d1272e00bb Prefix unused variable for now. 2021-11-02 15:45:56 -04:00
Bob McWhirter
44056c2e75 Less allowy. 2021-11-02 15:32:20 -04:00
Bob McWhirter
076c795ebb Even more allowed unused. 2021-11-02 15:28:14 -04:00
Bob McWhirter
6bbf450478 Allow unused macros temporarily until U5 supports DMA. 2021-11-02 15:20:42 -04:00
Bob McWhirter
705523d0ea Fix formatting. 2021-11-02 12:13:42 -04:00
Bob McWhirter
f12b70535b Adjust for STM32U5. 2021-11-02 12:05:24 -04:00
Bob McWhirter
bbff98ed0d Move the use inside the macro call, inside another set of braces in case it percolates up twice. 2021-10-26 14:34:03 -04:00
Bob McWhirter
a72816492a Only attempt to enable the dmamux peri clock if it has an enable bit. 2021-10-26 14:19:03 -04:00
Bob McWhirter
959aecf6ac Enable the DMAMUX clocks. 2021-10-26 14:01:39 -04:00
Matous Hybl
015cad84dd Initial support for STM32F767ZI. 2021-10-26 17:33:28 +02:00
bors[bot]
01e5376b25
Merge #456
456: Fix L4 clock setup for MSI and PLL to allow RNG operation r=Dirbaio a=lulf

Example is tested on STM32L475VG.

Co-authored-by: Ulf Lilleengen <lulf@redhat.com>
2021-10-26 11:59:14 +00:00
Ulf Lilleengen
e55726964d Fix clock setup for MSI and PLL to allow RNG opereation
Add RNG example using PLL as clock source.
2021-10-26 13:45:53 +02:00
Ulf Lilleengen
f8ebc967a9 Add implementation of async trait for STM32 I2C v2
* Add DMA read implementation for I2C v2
* Add example using DMA for I2C
2021-10-21 12:30:02 +02:00
Ulf Lilleengen
d2a79a46c5 Configure the correct pin instances 2021-10-21 11:57:00 +02:00
Tobias Pisani
43a7226d8b inline FRE register check for SPI on F1 2021-10-11 23:33:32 +02:00
Tobias Pisani
2cbb8a7ece Add AFType::Input for input configurations. 2021-10-11 22:57:21 +02:00
Tobias Pisani
259e84e68e Make miso/mosi optional when for unidirectional spi
Only suported on v1 currently
2021-10-11 22:57:21 +02:00
Tobias Pisani
c44bed300b Correctly set alternate function for stm32f1 gpios 2021-10-11 22:57:21 +02:00
Tobias Pisani
091e7e1f98 Generate USART pin definitions for stm32f1 2021-10-11 22:57:21 +02:00
Tobias Pisani
39880de958 partial alternate function configuration on STM32f1 2021-10-11 22:57:10 +02:00
Tobias Pisani
f9a576d13d feat: Add spi support for STM32F1 variants 2021-10-11 22:39:48 +02:00
Ben Gamari
006bbea51a stm32/adc: Add IN0 channel 2021-09-29 00:32:40 -04:00
Ben Gamari
5a38cc2140 stm32/dac: Ensure that clock is enabled 2021-09-29 00:32:40 -04:00
Ben Gamari
0b9961584b stm32/adc: Ensure that clock is enabled
Sadly due to the inconsistency in clocking configuration across devices
we cannot use RccPeripheral.
2021-09-29 00:32:40 -04:00
Ben Gamari
573e6ec373 stm32g0: Add support for low-power run 2021-09-28 21:19:10 -04:00
Ben Gamari
794798e225 stm32g0: Add support for HSI divider 2021-09-28 21:19:10 -04:00
Ben Gamari
aa4069fe10 stm32/adc: Fix ADC support for STM32G0 2021-09-28 21:19:10 -04:00
Ben Gamari
e2e0464d04 stm32/adc: Factor out conversion logic
Also guard errata workaround correctly.
2021-09-28 18:00:05 -04:00
Mariusz Ryndzionek
ce361abb1b Changing the casts (code review request) 2021-09-28 18:31:04 +02:00
Mariusz Ryndzionek
bce909ec1e Initial STM32F1 family support with two examples for STM32F103C8 (Blue Pill) 2021-09-28 18:31:04 +02:00
Joshua Salzedo
ab60cfd64b
Patch additional regressions 2021-09-27 15:48:56 -07:00
Joshua Salzedo
67e2f9159c
set moder::ALTERNATE last when configuring pins to AF modes.
- as per STM32F4xx_hal's impl
2021-09-27 15:27:43 -07:00
Joshua Salzedo
07e20a7443
Pub use version-specific CRC symbols, not just the CRC struct. 2021-09-27 11:17:31 -07:00
Joshua Salzedo
a26ffeb84b
Cargo fmt 2021-09-27 10:49:32 -07:00
Joshua Salzedo
e36d4f460a
Fix variable names in crc_v2/v3.
removed `reclaim` in crc_v1.
used write instead of modify.
renamed `init` to `reset` in crc_v1.
2021-09-27 10:46:09 -07:00
Joshua Salzedo
43ad28b9f9
Use unborrow for CRC constructor
sort feature gates
fix repetition in CRC config names
2021-09-27 10:38:55 -07:00
Joshua Salzedo
7392e33ad5
cargo fmt 2021-09-26 19:20:21 -07:00
Joshua Salzedo
e67af514e9
Fix v2/3 module paths 2021-09-26 19:15:54 -07:00
Joshua Salzedo
642b0825a6
V3 is just an extension of V2, merge modules. 2021-09-26 19:14:08 -07:00
Joshua Salzedo
f9ff5336d4
Merge all of the crc_v2 configurations into a single modify call 2021-09-26 18:46:19 -07:00
Joshua Salzedo
8fac444c4e
Flesh out v2 config writes 2021-09-26 18:39:55 -07:00
Joshua Salzedo
afef19d813
Start work towards CRC_V2 2021-09-26 18:26:20 -07:00
Joshua Salzedo
7899d73359
Expose read so the value can be obtained without a write. 2021-09-26 17:28:58 -07:00
Joshua Salzedo
c892289b2c
Actually export CRC 2021-09-26 17:26:33 -07:00
Joshua Salzedo
24dea91f5a
Fix interface changes 2021-09-26 17:24:48 -07:00
Joshua Salzedo
e18a27eea2
First pass at CRC_V1 2021-09-26 16:46:17 -07:00
Joshua Salzedo
e527892d89
Start work on CRC_v1 2021-09-26 16:29:22 -07:00
Dario Nieuwenhuis
f8d833e0c5
Merge pull request #403 from mryndzionek/af_type
Small adjustment to 'set_as_af' interface
2021-09-24 20:20:45 +02:00
Mariusz Ryndzionek
e4b37c40c9 Code review request - moving OutputType to mod sealed 2021-09-24 19:56:48 +02:00
Mariusz Ryndzionek
d371298a27 Small adjustment to 'set_as_af' interface
Small adjustment to 'set_as_af' interface - v2
2021-09-24 18:39:07 +02:00
Vincent Stakenburg
7d6d274d55 Add MSI and PLL clock source for L4 2021-09-24 18:27:39 +02:00
Ulf Lilleengen
b6fc19182b Add pwr for L1 and update RCC to new reg block 2021-09-23 14:51:16 +02:00
Ulf Lilleengen
9d45018077 Refactor V1 SPI 2021-09-21 14:50:23 +02:00
Ulf Lilleengen
c79485c286 Support for STM32L1
* Add RCC
* Fix more issues with dash in chip names
* Update stm32-data version
* Add blinky and spi example
2021-09-21 14:50:23 +02:00
Ulf Lilleengen
fb697a2657 Updates 2021-09-15 12:46:20 +02:00
Dario Nieuwenhuis
ead987245d embassy: Refactor module structure to remove kitchen-sink util. 2021-09-11 02:35:35 +02:00
Adam Greig
14fa6c2760
STM32H7: Ethernet: Disable RA in MAC filtering, fix order of MACA0 register writes. 2021-09-06 23:16:43 +01:00
Bob McWhirter
d4bf78a0c1 Don't set SAF=true, do set RA=true for Ethernet.
Source-Address-Filtering is not helping the board to receive packets.
For unknown reasons, the Receive-All is required, when in theory
it should not be required. Until we figure it out, follow the
stm32h7xx-hal example of setting RA=true.
2021-09-06 14:21:26 -04:00
Dario Nieuwenhuis
eff8ae9c4d
Merge pull request #381 from lulf/stm32wl55-subghz
Add HAL for SubGhz peripheral for STM32 WL series
2021-09-06 00:58:42 +02:00
Dario Nieuwenhuis
de016e8456 Remove trait_alias, allow(incomplete_features).
trait_alias seems unused. no idea why it's there.
2021-09-03 17:00:58 +02:00
Ulf Lilleengen
0f3d278ce3 Temporarily comment unused code 2021-09-02 11:31:38 +02:00
Ulf Lilleengen
4dccda085f Add missing files for G0 2021-09-02 11:19:54 +02:00
Ulf Lilleengen
f175574bcf Cargo fmt 2021-09-02 10:43:08 +02:00
Ulf Lilleengen
16aa1d1770 ADd missing file 2021-09-02 10:42:11 +02:00
Ulf Lilleengen
7ad6280e65 Add HAL for SubGhz peripheral for STM32 WL series
Based on the HAL from stm32wl, the peripheral driver has been
modified to fit into embassy, using the embassy APIs, providing
operation of the radio peripheral.

The initial version does not offer any async APIs, but the example
shows how the radio IRQ can be used to perform async TX of the radio.
2021-09-02 10:39:56 +02:00
Bob McWhirter
37ceae908b Rename Random impl to Rng.
Create Random struct providing next_x(range) for all T:Rng.
2021-09-01 09:39:33 -04:00
Bob McWhirter
7fa3b27cac Move random utils to another trait. 2021-08-30 09:55:29 -04:00
Bob McWhirter
d525f51940 Add a convenience next(range) to Rng. 2021-08-27 16:10:01 -04:00
Dario Nieuwenhuis
e56c6166dc
Merge pull request #373 from embassy-rs/docs
Time driver improvements, docs.
2021-08-26 23:37:37 +02:00
Bob McWhirter
dc394dd477 Fixes #374: Ensure Rng's error is defmt-able. 2021-08-26 14:04:12 -04:00
Dario Nieuwenhuis
7c0990ad1e time: allow storing state inside the driver struct. 2021-08-25 21:06:27 +02:00
Bob McWhirter
4aa52f1b9e Formatting. 2021-08-24 14:56:45 -04:00
Bob McWhirter
e36ae76e45 Fix blocking-write for SPI. 2021-08-24 14:44:47 -04:00
Ben Gamari
e2f71ffbbd Add support for STM32G0 2021-08-20 00:15:11 +02:00
Dario Nieuwenhuis
174c51f097 stm32/metapac: check GPIO RCC regs are always found. 2021-08-19 23:59:50 +02:00
Dario Nieuwenhuis
2c992f7010 stm32: move dbgmcu stuff to toplevel config setting, defaulting to true. 2021-08-19 23:50:19 +02:00
Dario Nieuwenhuis
9f51f9a170 stm32/wl: add stub APB3 to get it to build.
Completely untested.
2021-08-19 22:51:41 +02:00
Dario Nieuwenhuis
637fcdd316 stm32/rcc: update for new version naming 2021-08-19 22:17:45 +02:00
Dario Nieuwenhuis
ec51880e28 stm32/exti: unify all versions into single impl 2021-08-19 22:17:17 +02:00
Timo Kröger
f141b98741 bxcan: Cleanup
Older families like F1 and F4 have a consistent naming for the CAN
peripherals: CAN when there is only one instance, CAN1/CAN2/CAN2 if
there are multiple instances.
Newer families like L4 and F7 use the name CAN1 even if there is only
one instance. The number of filter banks is incorrect for those.

Affected chips:
* STM32F722
* STM32F723
* STM32F730
* STM32F732
* STM32F733
* STM32L4P5
* STM32L4Q5
* STM32L4R5
* STM32L4R7
* STM32L4R9
* STM32L4S5
* STM32L4S7
* STM32L4S9
* STM32L431
* STM32L432
* STM32L433
* STM32L442
* STM32L443
* STM32L451
* STM32L452
* STM32L462
* STM32L471
* STM32L475
* STM32L476
* STM32L485
* STM32L486
2021-08-18 21:58:50 +02:00
Timo Kröger
191a589820 bxcan: namechange "bxcan_v1" -> "can_bxcan" 2021-08-18 21:58:50 +02:00
Timo Kröger
dc6b7f3cba bxcan: Disable on drop 2021-08-18 21:58:50 +02:00
Timo Kröger
7c405250a7 CAN support with bxcan crate 2021-08-18 21:58:50 +02:00
Ulf Lilleengen
4df63f5379 Add per-core EXTI support
* Generate a core index put into the PAC for the peripherals to use as
  index into registers.
* Add EXTI v2 which uses CORE_INDEX to index exti registers
2021-08-17 16:22:47 +02:00
Ulf Lilleengen
61409e2fb6 Add example for STM32WL55 2021-08-17 16:22:47 +02:00
Bob McWhirter
a93ed2bed6 Add H7 exti button example using correct EXTI reg block offsets. 2021-08-16 15:15:07 -04:00
Ulf Lilleengen
cbff0398bb
Add IRQ-driven buffered USART implementation for STM32 v2 usart (#356)
* Add IRQ-driven buffered USART implementation for STM32 v2 usart

* Implementation based on nRF UARTE, but simplified to not use DMA to
  avoid complex interaction between DMA and USART.
* Implementation of AsyncBufRead and AsyncWrite traits
* Some unit tests to ring buffer
* Update polyfill version
* Update sub module to get usart IRQ fix
2021-08-16 17:16:49 +02:00
Thales Fragoso
c7ae2d2a3a stm32: Add fences to DMA code 2021-08-10 20:45:41 -03:00
Ben Gamari
40e7176e13 embassy-stm32: Eliminate use of unwrap 2021-08-05 22:40:08 +02:00
Ben Gamari
41aaff95f8 stm32h7: Use unwrap! 2021-08-05 22:39:59 +02:00
Ben Gamari
e44acd0d56 stm32f4: Use unwrap! where possible 2021-08-05 22:39:59 +02:00
Dario Nieuwenhuis
05e50e1f4a time_driver: use regular fn ptr -> raw ptr casts 2021-08-05 19:19:47 +02:00
Dario Nieuwenhuis
b1d631d639 stm32/time: add Cargo features to choose tim2/tim3 2021-08-05 19:14:09 +02:00
Dario Nieuwenhuis
0ea6a2d890 time: replace dyn clock/alarm with a global Driver trait 2021-08-05 19:14:09 +02:00
Dario Nieuwenhuis
cfa1f61154
Merge pull request #344 from bobmcwhirter/remove_builders
Remove builders from Config(s) and examples.
2021-08-04 21:32:39 +02:00
Dario Nieuwenhuis
07d4b196f7 Update nightly, remove removed features. 2021-08-04 19:48:14 +02:00
Dario Nieuwenhuis
9bd34429f3 stm32: add missing + 'a bounds on trait GATs 2021-08-04 19:39:54 +02:00
Bob McWhirter
f4971fbb79 Further work sharing config for example and removing duplicated code. 2021-08-04 13:39:02 -04:00
Bob McWhirter
03f15d3a60 Remove builders from Config(s) and examples. 2021-08-04 11:32:39 -04:00
Dario Nieuwenhuis
de77dc11ca
Merge pull request #301 from thalesfragoso/i2cv2-dma
i2c-v2: Implement write_dma and write_dma_vectored
2021-08-04 12:28:18 +02:00
Dario Nieuwenhuis
5d31dd328f
Merge pull request #341 from lulf/usart-dma-read
Add uart::Read DMA-based implementation
2021-08-04 11:02:15 +02:00
Ulf Lilleengen
0d02342b2d Rename bread -> read_blocking 2021-08-04 08:34:30 +02:00
Bob McWhirter
88c11a653c Formatting fixes. 2021-08-03 14:12:11 -04:00
Bob McWhirter
d7409d63e8 Enhance Rcc configuration to be more fluentish.
Clean up H7 examples to remove all vegan HALs and PACs.
2021-08-03 13:57:18 -04:00
Ulf Lilleengen
6ff0614cb6 Add uart::Read DMA-based implementation
* Rename existing read() to bread() (blocking)
2021-08-03 15:31:24 +02:00
Dario Nieuwenhuis
3f28bb6c77 common: Initialize PeripheralMutex state with closure to ensure it's done in-place. 2021-08-02 20:13:41 +02:00
Dario Nieuwenhuis
e238079d7d Make const the states when able. 2021-08-02 19:59:02 +02:00
Dario Nieuwenhuis
63ac7ac799 Mark news as unsafe due to not being leak-safe. 2021-08-02 19:55:04 +02:00
Dario Nieuwenhuis
af87031d62 hal-common: remove Pin in PeripheralMutex 2021-08-02 19:55:04 +02:00
Bob McWhirter
3a00a1dba7 Undo the pwr-guarding cfg. 2021-08-02 11:34:41 -04:00
Bob McWhirter
f6c5f039c8 Emit a default memory.x alongside device.x from metapac. 2021-08-02 11:23:55 -04:00
Thales Fragoso
64a3ebd183 i2c-v2: Use new interrupts macro 2021-08-01 19:10:42 -03:00
Thales Fragoso
c1bb83d29d i2c-v2: Deref interrupt enabling in write_dma_internal 2021-08-01 19:10:42 -03:00
Thales Fragoso
6ddc83029a i2c-v2: Simplify write_dma 2021-08-01 19:10:42 -03:00
Thales Fragoso
362f7efe99 i2c-v2: Implement write_dma and write_dma_vectored 2021-08-01 19:10:42 -03:00
Dario Nieuwenhuis
3835278567
Merge pull request #321 from thalesfragoso/f4-pll
F4 PLL
2021-07-31 11:08:46 +02:00
Thales Fragoso
21e3acaa00 stm32: Use build.rs to generate a more coarse feature 2021-07-31 02:52:26 -03:00
Thales Fragoso
0421c57bd6 F4: Add PWR configuration to PLL 2021-07-29 18:43:15 -03:00
Thales Fragoso
5cfb9adad8 f4-pll: Add max values per chip 2021-07-29 18:43:15 -03:00
Thales Fragoso
e7714983b3 f4-rcc: Add option to enable debug_wfe and add hello example 2021-07-29 18:43:15 -03:00
Thales Fragoso
5abaf8e9d6 Start working on the F4 PLL 2021-07-29 18:43:13 -03:00
Timo Kröger
9342497132 stm32wl55: Use Dbgmcu::enable_all 2021-07-29 17:38:40 +02:00
Timo Kröger
cad43587e6 stm32l0: Use embassy::main for examples 2021-07-29 17:37:32 +02:00
Timo Kröger
2a4890165d stm32f0: Enable debug access in low power modes 2021-07-29 15:35:23 +02:00
Dario Nieuwenhuis
7bfb763e09 Rename embassy-extras to embassy-hal-common 2021-07-29 13:44:51 +02:00
Dario Nieuwenhuis
c8a48d726a
Merge pull request #277 from Liamolucko/fix-peripheral-ub
extras: Fix UB in `Peripheral`
2021-07-29 13:08:30 +02:00
Liam Murphy
d5ba35424d Replace PeripheralStateUnchecked with register_interrupt_unchecked 2021-07-29 15:11:26 +10:00
Bob McWhirter
8759213fcc Use new interrupt! table format to /enable/ the IRQs also. 2021-07-27 13:23:33 -04:00
Bob McWhirter
b910551c9a Generate more rows in the interrupts! table.
Adjust DMA/BDMA to use the new style.
2021-07-27 12:52:01 -04:00
Liam Murphy
079526559f Remove critical sections from PeripheralMutex interrupt handler by checking the interrupt's priority on startup.
Since `PeripheralMutex` is the only way to safely maintain state across interrupts, and it no longer allows setting the interrupt's priority, the priority changing isn't a concern.

This also prevents other causes of UB due to the interrupt being exposed during `with`, and allowing enabling the interrupt and setting its context to a bogus pointer.
2021-07-27 17:28:52 +10:00
Timo Kröger
06fb2a7a80 Enable SYSCFG clock in exti::init() 2021-07-24 11:13:49 +02:00
Dario Nieuwenhuis
3c7375c6cd stm32/bdma: do not clear IF on IRQ handler 2021-07-24 10:01:11 +02:00
Timo Kröger
43c4f24207 STM32 BDMA: Use interrupt flags instead of atomics 2021-07-24 09:26:07 +02:00
Timo Kröger
5a4a5ce334 STM32 DMA: Use interrupt flags instead of atomics 2021-07-24 09:26:07 +02:00
Bob McWhirter
83f63890e5 Actually take a &mut of that read slice. 2021-07-23 13:22:39 -04:00
Bob McWhirter
473a83a937 Adjust how we deal with read/write being different length.
Including some docs about it.
Removing the Rx-enablement for write-only operations.
2021-07-23 13:22:39 -04:00
Bob McWhirter
f1a3e0e05d As before, EVERY DANG TIME.
It'll be sweet with intellij-rust-plugin works better.
2021-07-23 13:22:39 -04:00
Bob McWhirter
b07325b476 Enable DMA for SPIv1 on F4's etc. 2021-07-23 13:22:39 -04:00
Bob McWhirter
8ab82191b7 Every dang time. 2021-07-23 13:22:39 -04:00
Bob McWhirter
a1dac21bdf Make SPIv3 work with DMA.
Add both DMA and non-DMA example to H7.
2021-07-23 13:22:39 -04:00
Bob McWhirter
6dbe049468 Add back in the other versions of SPI. 2021-07-23 13:22:39 -04:00
Bob McWhirter
0d2051243e SPIv2 + DMA. 2021-07-23 13:22:39 -04:00
Bob McWhirter
1a03f00b56 Wire up peripheral DMA channels for SPI. 2021-07-23 13:22:39 -04:00
Bob McWhirter
3df2aadc39 Avoid borrowck issue. 2021-07-23 13:22:39 -04:00
Bob McWhirter
dedc2bac42 IntelliJ'd. 2021-07-23 13:22:39 -04:00
Bob McWhirter
4c5a234a3a Add a non-minc write() to DMA which takes a count.
Use it from "read-only" SPI.
2021-07-23 13:22:39 -04:00
Bob McWhirter
7bbad4c4e5 More unused allowances. 2021-07-23 13:22:39 -04:00
Bob McWhirter
4bcc3b06c6 Include all versions when handing to CI. 2021-07-23 13:22:39 -04:00
Bob McWhirter
a75110296d Annotate to avoid unused warnings for the moment. 2021-07-23 13:22:39 -04:00
Bob McWhirter
3f379e06b0 Begin reworking SPI to add DMA for stm32. 2021-07-23 13:22:39 -04:00
Bob McWhirter
fe66f0f8f8 Checkpoint. 2021-07-23 13:22:39 -04:00
Bob McWhirter
650f867b1c Add a single-column variant to gpio_rcc! macro table
which includes just the set of registers that need to be
considered.

Then match against those registers with a single `modify(...)`
2021-07-23 11:32:20 -04:00
Bob McWhirter
13873df30b Auto-enable all GPIOs during init(). 2021-07-23 11:32:19 -04:00
Bob McWhirter
d68f2617e6 Add a Dbgmcu struct capable of enabling all relevant DBGMCU.cr fields.
Includes the addition of a `dbgmcu!(...)` macro table which currently takes
the form of

	(cr, $fn_name:ident)

where `$fn_name` is something like `set_dbgsleep_d1` etc.

The method is unsafe, since it's performing unsafe PAC operations.

Two examples modified to demonstrate its usage.
2021-07-22 14:18:48 -04:00
Bob McWhirter
2d3137afc7 The async move portion of @thalesfragoso's i2c PR. 2021-07-20 11:38:16 -04:00
Thales
40ea8298ee
Merge pull request #300 from thalesfragoso/clear-dma
stm32: Clear possible set flags after disabling DMA
2021-07-17 17:28:02 -03:00
Thales
f4b8709bac
Merge pull request #281 from thalesfragoso/i2c-256
i2c-v2: Support transfers with more than 255 bytes
2021-07-17 17:21:50 -03:00
Thales Fragoso
aae0431d31 stm32: Clear possible set flags after disabling DMA 2021-07-17 16:59:35 -03:00
Dario Nieuwenhuis
36be877ba3 stm32/dma: only set TRBUFF in DMAv1 (H7) 2021-07-17 08:01:20 +02:00
Dario Nieuwenhuis
3655048e0f stm32/dma: add MuxChannel trait to distinguish DMAMUX1 and DMAMUX2 channels. 2021-07-17 07:54:16 +02:00
Dario Nieuwenhuis
54b5012c56 stm32/dma: update codegen+macrotables for new stm32-data 2021-07-17 07:35:59 +02:00
Bob McWhirter
0119ea809d Get DMA on H7 working, add usart_dma example for H7. 2021-07-16 14:41:20 -04:00
Dario Nieuwenhuis
ae948415a7 stm32/dma: disable after finishing 2021-07-16 14:41:20 -04:00
Dario Nieuwenhuis
d0f2dc3abd Fix rustfmt 2021-07-16 14:41:20 -04:00
Dario Nieuwenhuis
63a0e188ea stm32/dma: fix h7 impls 2021-07-16 14:41:20 -04:00
Dario Nieuwenhuis
3d1391ef2d stm32/dma: impl all variants 2021-07-16 14:41:20 -04:00
Dario Nieuwenhuis
1b42b30201 stm32/pwr: add initial H7 SMPS support 2021-07-16 01:17:45 +02:00
Thales Fragoso
2f08c7ced5 stm32: Allow for RccPeripheral without reset field
This fix build on F0, since it doesn't have DMARST. This change makes
RccPeripheral::reset a no-op on peripherals where a reset field couldn't
be found
2021-07-15 13:25:51 -03:00
Thales Fragoso
e06628cdfb Update stm32-data 2021-07-14 23:39:50 -03:00
Thales Fragoso
aa8c7f990f i2c-v2: Implement write_vectored 2021-07-14 23:39:50 -03:00
Thales Fragoso
f2e78e9c34 i2c-v2: Correct number of chunks calculation 2021-07-14 23:39:50 -03:00
Thales Fragoso
8c7f8a61e3 i2c-v2: Support transfers with more than 255 bytes 2021-07-14 23:39:50 -03:00
Dario Nieuwenhuis
4361cb15f1 stm32/usart: merge v2 and v3 (they're identical) 2021-07-15 00:52:37 +02:00
Dario Nieuwenhuis
f916fe5476 all hals: reexport PAC if unstable-pac feature is set. 2021-07-14 22:19:04 +02:00
Bob McWhirter
43cb8de434 Remove gratuitous NoDmaMarker. 2021-07-14 14:37:42 -04:00
Bob McWhirter
38b1359c40 Remove pub and cfg's, since they will be implied by the existance of TxDma<T> in theory. 2021-07-14 14:35:03 -04:00
Bob McWhirter
a88f0028ef First shot at async dma usart for stm32. 2021-07-14 14:14:14 -04:00
Bob McWhirter
6e0e83cfd9 More conversions to associated consts. 2021-07-13 10:56:35 -04:00
Bob McWhirter
604a25ec5d Reduce number of traits and impls. 2021-07-13 10:46:31 -04:00
Bob McWhirter
8fbea38a5b Simplify some of the bdma macros.
Make more things associated consts.
2021-07-13 10:09:35 -04:00
Bob McWhirter
92247369e7 Remove some unused traits.
Move some fns to associated consts.
2021-07-13 10:09:35 -04:00
Bob McWhirter
2e10ab2e5c Let's count channels per DMA peripheral, shall we now? 2021-07-13 10:09:35 -04:00
Bob McWhirter
b0b61d99e6 Macros do indeed require a ! to invoke. 2021-07-13 10:09:35 -04:00
Bob McWhirter
6534b63e01 Simplify some macros around dmamux peripheral channels. 2021-07-13 10:09:35 -04:00
Bob McWhirter
0befa10367 Trivial to force CI to do it's thing. 2021-07-13 10:09:35 -04:00
Bob McWhirter
06e899b14c Adjust to DMA1EN in the rcc for l0. 2021-07-13 10:09:35 -04:00
Bob McWhirter
a9b2ed52ee Remove deadcode from dmamux.
Smoosh bdma down to a single version.
2021-07-13 10:09:35 -04:00
Bob McWhirter
45964c658c Generalize RCC enabling for BDMA peris. 2021-07-13 10:09:35 -04:00
Bob McWhirter
ff1cb9ac74 Remove warnings. 2021-07-13 10:09:35 -04:00
Bob McWhirter
97ad434d38 Twizzle our DMA vs BDMA channels. 2021-07-13 10:09:35 -04:00
Bob McWhirter
a24a7e9fec Allow some unused lints given that H7 is still in flight with its multitude of DMA. 2021-07-13 10:09:35 -04:00
Bob McWhirter
13975a0818 Try to improve H7 clockstuff. 2021-07-13 10:09:35 -04:00
Bob McWhirter
696a3b8552 Try to figure out h7cm's problem. 2021-07-13 10:09:35 -04:00
Bob McWhirter
6552af8f0b Fix warning for unused import. 2021-07-13 10:09:35 -04:00
Bob McWhirter
6e69992217 Add a no-op bdma for bdma v2 for CI. 2021-07-13 10:09:35 -04:00
Bob McWhirter
811ed18922 Add a missing 'use' for dma_v2. 2021-07-13 10:09:35 -04:00
Bob McWhirter
30a1d9bf93 Move to copying regs instead of &'static referencing.
Remove unneeded stuff from the DMAMUX end of the stick.
2021-07-13 10:09:35 -04:00
Bob McWhirter
f01ddd5f5c Mix dmamux into bdma_v1. 2021-07-13 10:09:35 -04:00
Bob McWhirter
6ec7253095 Checkpoint my DMA for thales. 2021-07-13 10:08:43 -04:00
Bob McWhirter
acdf7f4f13 Another checkpoint. 2021-07-13 10:08:43 -04:00
Bob McWhirter
31325a2547 Another checkpoint. 2021-07-13 10:08:43 -04:00
Bob McWhirter
043f0ea508 Checkpoint DMAMUX channel setup. 2021-07-13 10:08:43 -04:00
Thales Fragoso
91521a86a0 F0: usart + DMA working 2021-07-13 10:08:43 -04:00
Thales Fragoso
a56ddfdc04 STM: Add usart v2 2021-07-13 10:08:43 -04:00
Thales Fragoso
f32caaeaaf STM: Start working on bdma-v1 2021-07-13 10:08:43 -04:00
Liam Murphy
ff9ff5e43a Update the import 2021-07-05 18:31:54 +10:00
Liam Murphy
fc1ef4947d Fix stm32 ethernet 2021-07-05 18:18:05 +10:00
Dario Nieuwenhuis
ecc151d4e2 stm32/adc: simplify delay handling 2021-07-05 03:18:23 +02:00
Rukai
25d4b2ea26 fix stm32 warnings 2021-07-05 01:54:29 +02:00
Thales Fragoso
c2f595b26a F0: Fix missing apb2 clock 2021-07-03 02:12:22 -03:00
Bob McWhirter
f5ce807e25 Let's adjust i2c the correct way, removing the correct APBesque frequency, not the i2c periph speed. 2021-07-02 13:54:07 -04:00
Bob McWhirter
9f5d35d891 Remove the frequency argument for i2c, move to using RccPeripheral. 2021-07-01 13:53:57 -04:00
Bob McWhirter
8f94123ca4 argh, intellij. 2021-07-01 11:37:01 -04:00
Bob McWhirter
0920c0cb1d Make UART pins Rx/Tx/etc in addition to USART. 2021-07-01 11:30:54 -04:00
Bob McWhirter
54ada5bae1 Stub in the DMA bits that aren't yet there. 2021-07-01 11:30:54 -04:00
Bob McWhirter
bf3bc92525 Re-enable because intellij. 2021-07-01 11:30:54 -04:00
Bob McWhirter
497d3aa153 Add USARTv3 support. 2021-07-01 11:30:54 -04:00
Thales Fragoso
e07dda8707 stm32: Adjust some fences around DMA
Also bump stm32-data
2021-06-30 18:58:21 -03:00
Bob McWhirter
f3b9c97763 Change atomics and add a fence. 2021-06-30 10:17:25 -04:00
Bob McWhirter
cf5b7dc943 Because IntelliJ makes life hard. 2021-06-30 10:03:18 -04:00
Bob McWhirter
6a0b0f3162 Enable RCC within the USART itself. 2021-06-30 09:57:27 -04:00
Bob McWhirter
07a6686879 Protect DMA-related things with cfg. 2021-06-29 13:00:52 -04:00
Bob McWhirter
6b78d56ceb Formatting. 2021-06-29 12:48:58 -04:00
Bob McWhirter
c53ab325c1 Wire up DMA with USART v1. 2021-06-29 11:01:57 -04:00
Bob McWhirter
b88fc2847a Checkpoint with lifetime issues. 2021-06-29 11:01:57 -04:00
Thales Fragoso
c5022b1196 stm32: Make sure Output gpio driver is pushpull 2021-06-27 13:25:35 -03:00
Thales Fragoso
0eaadfc125 stm32: Update gpio examples 2021-06-25 18:16:43 -03:00
Thales Fragoso
a3f0aa02a4 Separate OpenDrain pin to a new type 2021-06-25 17:22:51 -03:00
Thales Fragoso
efb3b3a0a8 stm32: Allow for open drain configuration for output pin 2021-06-24 20:42:43 -03:00
Thales Fragoso
013792b944 Separate exti into v1 and v2 2021-06-24 20:28:06 -03:00
Thales Fragoso
1c33a3b94c #[cfg] exti 2021-06-24 19:41:04 -03:00
Thales Fragoso
409884be2a Add F0 RCC 2021-06-24 19:21:56 -03:00
Dario Nieuwenhuis
5a4e3ceb88 Update stm32-data (adds DBGMCU to all chips) 2021-06-21 01:38:59 +02:00
Thales Fragoso
598201bff3 eth-v2: Make embassy-net optional 2021-06-16 16:48:35 +02:00
Thales Fragoso
6cecc6d4b5 eth-v2: Get hclk frequency from clock singleton 2021-06-16 16:48:35 +02:00
Thales Fragoso
f7e1f262af eth-v2: Enable source address filtering 2021-06-16 16:48:35 +02:00
Thales Fragoso
ffc19a54d6 eth-v2: Fix bug in Rx descriptors and add docs art 2021-06-16 16:48:35 +02:00
Thales Fragoso
6daa55a897 eth-v2: Fix setting the registers for the descriptors
Also, the interrupts are set to 1 to clear, the manual could have helped
with that one...
2021-06-16 16:48:35 +02:00
Thales Fragoso
0b42e12604 eth-v2: Fix off by one bug 2021-06-16 16:48:35 +02:00
Thales Fragoso
54ad2a41f1 eth-v2: Work around missing AF for REF_CLK 2021-06-16 16:48:35 +02:00
Thales Fragoso
0c837f07c0 eth-v2: Enable clocks in new 2021-06-16 16:48:35 +02:00
Thales Fragoso
e039c7c42c eth-v2: Remove Instance trait 2021-06-16 16:48:35 +02:00
Thales Fragoso
05a239faf6 eth-v2: Implement embassy-net's Device Trait and fix Drop 2021-06-16 16:48:35 +02:00
Thales Fragoso
4cffa200bd eth: Add lan8742a PHY 2021-06-16 16:48:35 +02:00
Thales Fragoso
46e1bae9e3 eth-v2: Start Ethernet peripheral implementation 2021-06-16 16:48:35 +02:00
Ulf Lilleengen
56c5218292 Prescaler 1 means divide by 3 on WL55 2021-06-16 16:21:16 +02:00
Ulf Lilleengen
383beb37b3 Rename from wl55 to wl5x and enable debug wfe 2021-06-16 16:07:21 +02:00
Ulf Lilleengen
b6a8703698 Add support for generating PAC for dual cores
* Chips that have multiple cores will be exposed as chipname_corename,
  i.e. stm32wl55jc_cm4
* Chips that have single cores will use the chip family as feature name
  and pick the first and only core from the list
* Add support for stm32wl55 chip family
2021-06-16 15:12:07 +02:00
Ulf Lilleengen
8ae4f47d3d Fix compile 2021-06-15 16:44:00 +02:00
Ulf Lilleengen
49fad2de8a Use correct frequencies for timers 2021-06-15 16:07:23 +02:00
Ulf Lilleengen
4b406dd107 Remove default rcc impl 2021-06-14 20:24:51 +02:00
Bob McWhirter
d58fb11b2e ADCv3 and example. 2021-06-14 13:20:42 -04:00
Ulf Lilleengen
531093f281 Derive SPI v1 and v3 clocks automatically 2021-06-14 11:58:16 +02:00
Ulf Lilleengen
5e1b0a5398 Add wb55 clocks 2021-06-14 11:41:02 +02:00
Ulf Lilleengen
ee9f67fa01 Add common types 2021-06-14 11:33:11 +02:00
Ulf Lilleengen
a2da2a6db2 Remove unused l0 code 2021-06-14 11:33:11 +02:00
Ulf Lilleengen
95532726b2 Add minimal RCC impls for L4 and F4 2021-06-14 11:33:11 +02:00
Ulf Lilleengen
a13e07625f Add ... c1? 2021-06-14 11:33:11 +02:00
Ulf Lilleengen
0b52731897 Add clocks for h7 2021-06-14 11:33:11 +02:00
Ulf Lilleengen
2c63393c9e Add Clock type per RCC family 2021-06-14 11:33:11 +02:00
Ulf Lilleengen
952f525af5 Provide a way for a peripheral to query its clock frequency
Currently this looks up the frequency in the global singleton that must
be initialized by the per-chip RCC implementation. At present, this is
only done for the L0 family of chips.
2021-06-14 11:33:11 +02:00
Ulf Lilleengen
0a9022d59f Enable timer clock in RCC on timer start
* Moves the tim2-specific code into macro which always uses TIM2
* For peripherals without clock specified, attempt to locate enable and
  reset registers in the RCC block matching the peripheral name. This
  could be useful for peripherals where deducing the clock name might
  not be feasible, but it remains to be tested with more chip families
  to see if it is sufficiently accurate.
2021-06-10 09:37:30 +02:00
Ulf Lilleengen
1bb7123156 Add examples for STM32L0 2021-06-09 23:09:48 +02:00
Ulf Lilleengen
f3d1ac6623 Enable clock for RNG 2021-06-09 13:54:53 +02:00
Ulf Lilleengen
939ea3bbd0 Reduce generics noise 2021-06-08 17:20:29 +02:00
Ulf Lilleengen
ed29d82071 Use critical_section 2021-06-08 17:20:29 +02:00
Ulf Lilleengen
212bda0940 Enable clock for SPI v1 and v3 2021-06-08 17:20:29 +02:00
Ulf Lilleengen
a57482fddd Cargo fmt 2021-06-08 17:20:29 +02:00
Ulf Lilleengen
ee3b82b743 Auto generate SPI v2 clock enable
Adds RccPeripheral trait for peripherals implementing clock enable and reset for a given peripheral.

Add macro table generting implementations of RccPeripheral for peripherals with clock set, currently restricted to SPI.
2021-06-08 17:20:29 +02:00
Ulf Lilleengen
a63388874a Update after name fix 2021-06-07 14:06:54 +02:00
Ulf Lilleengen
f24c38f2a4 Fix 2021-06-07 13:51:06 +02:00
Ulf Lilleengen
1cd2c55b7c Fix stm32l0 build 2021-06-07 12:19:09 +02:00
Ulf Lilleengen
f5e2fb9a5a Update to new api 2021-06-07 12:03:31 +02:00
Dario Nieuwenhuis
0ffa78aca1 Use macrotables from build.rs 2021-06-07 05:12:10 +02:00
Dario Nieuwenhuis
3be49d3e79 fmt: Add dunmy use to avoid "unused variable" errors when no log is enabled. 2021-06-07 03:21:37 +02:00
Dario Nieuwenhuis
ef1ebefec0 fmt: use absolute paths 2021-06-07 03:15:05 +02:00
Dario Nieuwenhuis
e7dc5c0939 fmt: make all macros macro_rules so scoping is consistent. 2021-06-07 00:16:39 +02:00
Rukai
010b2b9497 Fix stm32 warnings 2021-06-06 00:46:20 +10:00
Bob McWhirter
b4dca64e20 Move most of DMA out of gen.py. 2021-06-03 14:53:48 -04:00
Bob McWhirter
240616aa72 General clean-up and removal of dead code. 2021-06-03 14:25:17 -04:00
Bob McWhirter
d75bf143eb Remove the exti_interrupts table. 2021-06-03 14:18:58 -04:00
Bob McWhirter
2c722ec0ee Migrate sdmmc to macro tables. 2021-06-03 13:50:48 -04:00
Bob McWhirter
fe47f781be Migrate exti_irq stuff to macro tables. 2021-06-03 13:35:27 -04:00
Bob McWhirter
75dc0fd542 Migrate TIM[2-5] to macro tables. 2021-06-03 13:23:21 -04:00
Bob McWhirter
c00a85f9a9 Refactor SPI signal pin macro. 2021-06-03 13:12:38 -04:00
Bob McWhirter
3dd497c1e6 Refactor some I2c signal pin macro. 2021-06-03 13:12:38 -04:00
Bob McWhirter
00892c7362 Migrate USART to macro tables. 2021-06-03 13:12:38 -04:00
Bob McWhirter
6958091b50 Move DAC, I2C, SPI and RNG to macro-tables. 2021-06-03 13:12:38 -04:00
Dario Nieuwenhuis
c7c6b0b464
Merge pull request #211 from bobmcwhirter/dac_v2
DAC v2 basics.
2021-06-02 16:16:27 +02:00
Ulf Lilleengen
c3a521066d Add utility to enable debug 2021-06-02 15:23:10 +02:00
Ulf Lilleengen
4863d5e01e Add a way to enable more features of the STM32L0 RCC
Add ability to enable the hsi48 clock. Code modified from the STM32L0XX
hal
2021-06-02 14:28:33 +02:00
Bob McWhirter
0c54c1afd1 DAC v2 basics. 2021-06-01 12:08:30 -04:00
Ulf Lilleengen
1a9a619033 Implement togglable output pin for Output 2021-05-31 09:33:33 +02:00
Dario Nieuwenhuis
b2d8d23f4c more fix 2021-05-31 03:25:10 +02:00
Dario Nieuwenhuis
d24b67512f More fixes 2021-05-31 03:21:44 +02:00
Dario Nieuwenhuis
d8e4421fc6 Add stm32-metapac crate, with codegen in rust 2021-05-31 02:40:58 +02:00
Ulf Lilleengen
edec5833b3 Refactor SPI and fix write bug
* SPI write v2 was hanging in write due to an infinite loop
* SPI word write was not followed by a read back

The u8 and u16 write/read logic have been refactored into write_word and
read_word.
2021-05-27 23:05:42 +02:00
Dario Nieuwenhuis
3f6f1d99bb
Merge pull request #207 from lulf/clock-init
Enable clock by default for stm32l0
2021-05-27 13:36:14 +02:00
Ulf Lilleengen
3669eba561 Use builder 2021-05-27 10:01:40 +02:00
Ulf Lilleengen
a41a812345 Move clocks to rcc mod 2021-05-27 09:50:11 +02:00
Ulf Lilleengen
6eaf224fec No more systemclock 2021-05-26 21:46:57 +02:00
Ulf Lilleengen
bfa999a2e0 Assume tim2 in macro and remove clock setup in chip specific rcc init
Add temporary start_tim2() fn to Clock to assist macro in starting
embassy clock
2021-05-26 21:42:07 +02:00
Ulf Lilleengen
f960f5b105 Rework 2021-05-26 13:55:25 +02:00
Ulf Lilleengen
9743c59ad4 Simplify 2021-05-26 13:29:11 +02:00
Ulf Lilleengen
ea67940743 Refactor 2021-05-26 13:08:14 +02:00
Ulf Lilleengen
c501b162fc Enable clock by default for stm32l0
Modify init function to return a Clock instance defined by a per-chip
SystemClock type and use this in macro setup

A proof of concept implementation for STM32 L0 chips.

This allows using embassy::main macros for STM32 devices that have the
clock setup logic.
2021-05-26 12:33:07 +02:00
Bob McWhirter
a9ec941dca i2c v1 2021-05-25 14:47:07 -04:00
Bob McWhirter
aed8283cd5 Finalize i2c v2. 2021-05-25 10:02:40 -04:00
Ulf Lilleengen
ef254647f7 Add stm32l0 2021-05-25 13:32:10 +02:00
Ulf Lilleengen
1c10e746b6 Re-adds embassy macros for stm32
* Hook RCC config into chip config and use chip-specific RCC init
  function
* RTC/clock setup is ignored for now
2021-05-25 13:30:42 +02:00
Thales Fragoso
9c5d4d9f8a STM32 Clock: Use atomic-polyfill 2021-05-23 17:22:07 -03:00
Thales Fragoso
66f232574a Update stm32-data and rename RTC to Clock 2021-05-23 17:09:11 -03:00
Thales Fragoso
90b25e70d7 timer-rtc: Already ask for the timer frequency 2021-05-23 16:15:24 -03:00
Thales Fragoso
e501932cb5 Update generated files 2021-05-23 15:59:49 -03:00
Thales Fragoso
13698d58e4 Add timer/rtc impl macro 2021-05-23 15:59:09 -03:00
Thales Fragoso
e49e3723a8 wip timers for embassy rtc 2021-05-22 23:58:40 -03:00
Thales Fragoso
212d905816 Update generated files 2021-05-22 23:55:44 -03:00
Thales Fragoso
7c06518c52 Update generated files 2021-05-22 22:27:49 -03:00
Thales Fragoso
5e49a9932f Update generated files 2021-05-22 22:07:05 -03:00
Thales Fragoso
a0fe9e4645 Add unstable feature to give access to the pac 2021-05-22 15:34:49 -03:00
Thales Fragoso
2605dabca3 H7 RCC: Fix off by one error 2021-05-21 20:20:17 -03:00
Thales Fragoso
f5860c3c4c Fix import on SDMMC 2021-05-21 20:20:17 -03:00
Thales Fragoso
1689ab2f8b H7 RCC: Setup DBGMCU to enable debugging during wfi/wfe 2021-05-21 20:20:17 -03:00
Thales Fragoso
f9724fa576 Update generated code 2021-05-21 20:20:12 -03:00
Thales Fragoso
7f65f491e5 Finish initial H7 RCC support 2021-05-21 20:16:25 -03:00
Thales Fragoso
82ca5b495e Update generated code 2021-05-21 20:14:52 -03:00
Thales Fragoso
2ea12d96ee More work on H7 RCC 2021-05-21 20:13:39 -03:00
Thales Fragoso
054f0d51dc H7: Add initial PLL configuration 2021-05-21 20:13:37 -03:00
Thales Fragoso
7e388fcf58 Add pac RCC for H7 (generated) 2021-05-21 20:11:27 -03:00
Dario Nieuwenhuis
447e4e6023 Regen 2021-05-21 19:35:15 +02:00
Dario Nieuwenhuis
35f1f65670 Generate mod regs just once, so rustfmt is way faster. 2021-05-21 19:34:41 +02:00
Dario Nieuwenhuis
f96db3d9d2 Remove ad-hoc imports from generated code. 2021-05-21 19:29:37 +02:00
Dario Nieuwenhuis
0d08e65235 Regen 2021-05-21 19:05:21 +02:00
Ulf Lilleengen
03bfbe51f5 Create DMA fn to select peripheral based on channel number 2021-05-21 18:38:33 +02:00
Ulf Lilleengen
32fbb32a84 Move exti setup into pac module 2021-05-21 18:38:33 +02:00
Ulf Lilleengen
a95c78b8bd Merge exti macros into one and use simpler recursion 2021-05-21 18:38:33 +02:00
Ulf Lilleengen
9fa5a2920f Move regs trait implementation into generated pac
This allows handling devices that don't have DMA2
2021-05-21 18:38:33 +02:00
Ulf Lilleengen
0cd3236fa3 Generate exti interrupt handlers
Match interrupts starting with ^EXTI and generate init code and irq
handler for them
2021-05-21 18:38:33 +02:00
Dario Nieuwenhuis
2e6c550355
Merge pull request #197 from rukai/fix_stm32_warnings
Fix warnings for embassy-stm32 and embassy-stm32-examples and add .cargo/config.toml + memory.x
2021-05-21 17:25:59 +02:00
Dario Nieuwenhuis
0bc440233c
Merge pull request #184 from bobmcwhirter/spi_v3
Spi v3
2021-05-21 17:21:36 +02:00
Bob McWhirter
b3eda9914b Use the correct register names. 2021-05-20 14:24:40 -04:00
Bob McWhirter
222faccbab Formatting. 2021-05-20 14:19:43 -04:00
Bob McWhirter
8b36269d65 Use modify instead of write for regs within a driver. 2021-05-20 14:14:31 -04:00
Bob McWhirter
d890ef98c1 Make SPIv3 work and improve v1 and v2. 2021-05-20 14:13:45 -04:00
Lucas Kent
82f9242df2 Fix warnings for embassy-stm32 and embassy-stm32-examples 2021-05-20 22:25:12 +10:00
Dario Nieuwenhuis
105c8504b6 Mark Unborrow as unsafe to implement 2021-05-19 23:29:33 +02:00
Bob McWhirter
0d1a0934c4 Cargo fmt. 2021-05-17 13:58:49 -04:00
Bob McWhirter
1872824d56 Add SPI v3, fix up v2's af_num and remove extraneous Error enums. 2021-05-17 13:56:13 -04:00
Bob McWhirter
a4fd1282e9 Generate _spi_v3 items. 2021-05-17 11:34:36 -04:00
Dario Nieuwenhuis
f7858631d8 stm32: fix build, add ci 2021-05-17 03:16:58 +02:00
Dario Nieuwenhuis
cd0d3c4b0d Merge branch 'stm32-neo' 2021-05-17 02:16:17 +02:00
Dario Nieuwenhuis
2303364322 Standardize module structure, fix some build failures 2021-05-17 02:04:51 +02:00
Dario Nieuwenhuis
bdc3ada4b2 WIP: dma 2021-05-17 01:08:30 +02:00
Dario Nieuwenhuis
befc052cba stm32/usart_v1: add read 2021-05-17 01:04:51 +02:00
Dario Nieuwenhuis
852ca5a1c5 stm32/usart_v1: implement tx 2021-05-17 01:04:51 +02:00
Dario Nieuwenhuis
bfc7f52e6d Remove stm32.
stm32 developemnt continues in the `stm32-neo` branch for now.
2021-05-17 00:57:32 +02:00
Thales Fragoso
0f5ba6d4a9 SDMMC: Implement Default for Config and add docs 2021-05-15 21:21:06 -03:00
Thales Fragoso
86063ac2a2 Update generated code 2021-05-14 23:53:12 -03:00
Thales Fragoso
1e5f25aa41 Move parameters to a config struct 2021-05-14 23:47:58 -03:00
Thales Fragoso
a5d473be0e Fix RNG interrupt name 2021-05-14 23:47:56 -03:00
Thales Fragoso
2cb66d6032 Update generated code 2021-05-14 23:44:51 -03:00
Thales Fragoso
ad720f83df Expose data transfer timeout and implement configuration for BusWidth one 2021-05-14 23:43:11 -03:00
Thales Fragoso
359aaa5aeb Implement embedded-sdmmc traits 2021-05-14 23:43:09 -03:00
Thales Fragoso
a130499c9a Get rid of some warnings 2021-05-14 23:42:12 -03:00
Thales Fragoso
c183c352c7 SDMMC: Implement read and write 2021-05-14 23:42:12 -03:00
Thales Fragoso
490152d028 Better interrupt handling 2021-05-14 23:42:09 -03:00
Thales Fragoso
72fb3a7520 Init working :) 2021-05-14 23:40:28 -03:00
Thales Fragoso
0b607ca80a Initial H7 sdmmc support 2021-05-14 23:40:28 -03:00
Dario Nieuwenhuis
180ca48d34 Remove AF_NUM const from pin traits, only use af_num fn 2021-05-15 03:18:15 +02:00
Dario Nieuwenhuis
e63c4bde0b stm32: remove psel_bits 2021-05-15 03:07:59 +02:00
Dario Nieuwenhuis
8bb1bc3507 Move pin configuration to gpio mod 2021-05-15 03:07:59 +02:00
Bob McWhirter
2569d38ab4 Adjust pin-names to FooPin.
Move common bits up to spi/mod.rs.
Isolate the RNG interrupt in a sub-module to avoid conflict with the const.
2021-05-14 10:11:43 -04:00
Bob McWhirter
9e93a0999f Add SPIv1, use cfg_attr to pick correct impl.
Add IRQ to impl_rng!() to accomodate RNG vs HASH_RNG split.
2021-05-13 14:28:53 -04:00
Bob McWhirter
07db3ed7c1 Further improvement to SPIv2. 2021-05-12 14:18:42 -04:00