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7 Commits

Author SHA1 Message Date
xoviat
d1dfaa1905 stm32/ipcc: fix hil test 2023-05-21 20:18:26 -05:00
xoviat
bf45b1d83d fix memory.x 2023-05-11 17:23:18 -05:00
xoviat
8a620fd59c stm32/ble: fix tests and add instructions to run example 2023-05-11 16:45:42 -05:00
goueslati
007f452927 removed hardcoded addresses in memory.x 2023-05-04 11:02:17 +01:00
Dario Nieuwenhuis
13328c58d3
examples/stm32wb: do not reserve words at start of RAM. 
They're used to communicate from the app to ST's OTA bootloader. See AN5247. 

This bootloader is optional, must be flashed by the user, and requires changing the FLASH start address as well, so the current memory regions still require modifications to use it. Therefore there's no point in reserving these words.

Thanks @adamgreig for investigating the purpose.
 2023-02-20 01:01:01 +01:00
Dario Nieuwenhuis
272982ee54 examples/stm32wb: fix linker script. 
cortex-m-rt 0.7.2 now enforces the stack is 8-byte aligned. Stack is placed
at `ORIGIN(RAM) + LENGTH(RAM)` by default, which wasn't 8-byte-aligned. See https://github.com/rust-embedded/cortex-m/discussions/469

ST trims 8 bytes from start of RAM, and uses the whole 192kb, so let's just
copy that:

bceb1dae09/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/linker/stm32wb55xx_flash_cm4.ld (L48)
 2023-02-19 23:02:31 +01:00
Dario Nieuwenhuis
0c07d03754 Add missing stm32wl/stm32wb chips except stm32wle 2022-04-08 03:15:27 +02:00