Dario Nieuwenhuis
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0d08e65235
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Regen
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2021-05-21 19:05:21 +02:00 |
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Dario Nieuwenhuis
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bdc3ada4b2
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WIP: dma
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2021-05-17 01:08:30 +02:00 |
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Thales Fragoso
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86063ac2a2
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Update generated code
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2021-05-14 23:53:12 -03:00 |
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Thales Fragoso
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a5d473be0e
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Fix RNG interrupt name
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2021-05-14 23:47:56 -03:00 |
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Thales Fragoso
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2cb66d6032
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Update generated code
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2021-05-14 23:44:51 -03:00 |
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Thales Fragoso
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490152d028
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Better interrupt handling
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2021-05-14 23:42:09 -03:00 |
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Bob McWhirter
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2569d38ab4
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Adjust pin-names to FooPin.
Move common bits up to spi/mod.rs.
Isolate the RNG interrupt in a sub-module to avoid conflict with the const.
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2021-05-14 10:11:43 -04:00 |
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Bob McWhirter
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9e93a0999f
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Add SPIv1, use cfg_attr to pick correct impl.
Add IRQ to impl_rng!() to accomodate RNG vs HASH_RNG split.
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2021-05-13 14:28:53 -04:00 |
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Bob McWhirter
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36c16dbef8
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Continuing to update clocks (unused now) and SPI
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2021-05-12 10:46:18 -04:00 |
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Bob McWhirter
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7d52e1b350
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Further work on SPI v2 blocking.
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2021-05-11 11:25:01 -04:00 |
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Bob McWhirter
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0470abb353
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Checkpoint.
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2021-05-10 15:33:37 -04:00 |
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Dario Nieuwenhuis
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c4294d97ff
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Fix DMA
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2021-05-10 21:31:59 +02:00 |
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Dario Nieuwenhuis
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ac616a6dcf
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Add dma scaffolding
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2021-05-10 01:20:04 +02:00 |
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Dario Nieuwenhuis
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23ca2f9174
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Autogenerate the tailored PAC for each chip
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2021-05-06 03:43:46 +02:00 |
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