Commit Graph

3088 Commits

Author SHA1 Message Date
Philip A Reimer
1f59f8e7d0 add pllsai1 and allow for 120Mhz clock on stm32l4+ 2022-04-01 22:42:43 -06:00
bors[bot]
0eea6fd6b5
Merge #690
690: Use embassy/defmt-timestamp-uptime in all examples. r=Dirbaio a=Dirbaio

bors r+

Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2022-04-02 02:35:49 +00:00
Dario Nieuwenhuis
82803bffda Use embassy/defmt-timestamp-uptime in all examples. 2022-04-02 04:35:06 +02:00
bors[bot]
a9e63167e1
Merge #689
689: Avoid writing bootloader flash if not needed r=lulf a=lulf

bors r+

Co-authored-by: Ulf Lilleengen <lulf@redhat.com>
2022-03-31 13:24:25 +00:00
Ulf Lilleengen
b0a53610ba Avoid writing bootloader flash if not needed 2022-03-31 15:23:06 +02:00
bors[bot]
f028b0064b
Merge #685
685: Fix STM32 timer interrupt bug r=Dirbaio a=chemicstry

Previously timer overflow interrupts were not firing correctly, because Update Interrupt Enable (UIE) was not set.

The timers still worked somewhat correclty, because overflow was handled together with other interrupts.

Co-authored-by: chemicstry <chemicstry@gmail.com>
2022-03-29 22:13:30 +00:00
chemicstry
d052631118 Fix STM32 timer interrupt bug 2022-03-30 00:27:33 +03:00
bors[bot]
1a31cda3c3
Merge #682
682: Convert chip name to upper case to fix rebuilds r=Dirbaio a=DCNick3

PR #665 made stm32-metapac rebuild when the chip definition was changed.
Though it used the lowercase version of the chip name as a filename which probably worked fine on windows with its case-independent filesystem, but was causing constant rebuilds on linux

Co-authored-by: Nikita Strygin <nikita6@bk.ru>
2022-03-28 15:50:13 +00:00
Nikita Strygin
58948051e5 Convert chip name to upper case to fix rebuilds
PR #665 made stm32-metapac rebuild when the chip definition was changed.
Though it used the lowercase version of the chip name as a filename
which probably worked fine on windows with its case-independent
filesystem, but was causing constant rebuilds on linux
2022-03-28 18:44:17 +03:00
bors[bot]
c6fb7807c0
Merge #677
677: nrf: nrf52832 doesn't have SPI3 r=Dirbaio a=Dirbaio



Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2022-03-27 17:44:54 +00:00
bors[bot]
a211003021
Merge #678
678: Add minimal F2 family support r=Dirbaio a=Gekkio

Here's the bare minimum to support F2 family (207/217/205/215). A lot is missing in RCC (e.g. PLL support), but this is enough to have a working blinky example. The example is set up for a NUCLEO-F207ZG board which I don't have, but I've tested it on my custom board with a F215 and different pinout 😅 

After looking at other RCC implementation, I noticed there's two main API styles: a "low-level" API (e.g. L0) where the `Config` struct has dividers and other low-level "knobs", and a "high-level" API (e.g. F0) where it has desired clock frequencies and the RCC implementation figures out how to achieve them. Which one is preferred? Personally I like the low-level API slightly more, because it gives you the most control and it would be easy to also provide some functions to calculate the required parameters based on desired clock frequencies.

F2 has a nasty errata: a delay or DSB instruction must be added after every RCC peripheral clock enable. I've added this workaround to build.rs, but am not sure if this is the best approach. Any comments?

I'm planning to add PLL support too once I know which kind of API is preferred. Would you prefer a separate pull request for that, or should I continue working on this one?

Co-authored-by: Joonas Javanainen <joonas.javanainen@gmail.com>
2022-03-27 17:18:30 +00:00
Joonas Javanainen
55a9bf98c5
Add STM32F217ZG to CI
F217 has the most features in the F2 family
2022-03-27 19:56:44 +03:00
Joonas Javanainen
5d97c8c8b2
Add F2 examples to CI 2022-03-27 19:55:43 +03:00
Joonas Javanainen
83211c2b61
Add workaround for F2 errata 2022-03-27 19:00:36 +03:00
Joonas Javanainen
a16fef21e1
Add blinky example for STM32F2
Default configuration is for NUCLEO-F207ZG board
2022-03-27 18:45:37 +03:00
Joonas Javanainen
a608d0deaf
Add minimal STM32F2 RCC
No support for PLL or other clocks than SYSCLK/AHB/APB1/APB2
2022-03-27 18:40:49 +03:00
Dario Nieuwenhuis
490d4588ea nrf: nrf52832 doesn't have SPI3 2022-03-22 19:33:35 +01:00
bors[bot]
5c68f0bae7
Merge #676
676: Fix potential unaligned write r=lulf a=lulf

Ensure 4 byte alignment of writes to boot magic.

Reduce log level

Co-authored-by: Ulf Lilleengen <lulf@redhat.com>
2022-03-22 13:44:33 +00:00
Ulf Lilleengen
73012ed40e Fix potential unaligned write
Reduce log level
2022-03-22 14:43:17 +01:00
Joonas Javanainen
08e6a996bc
Regenerate embassy-stm32 features 2022-03-21 00:19:36 +02:00
Joonas Javanainen
5fd1421af2
Mark F2 as a supported family 2022-03-21 00:19:20 +02:00
Joonas Javanainen
5df4ae7baf
Fix suffix of generated chip metadata files
stm32-data switched from YAML to JSON files in this commit:

4c1eda7c32
2022-03-21 00:17:24 +02:00
bors[bot]
48f7d37e75
Merge #675
675: Update stm32data r=Dirbaio a=Dirbaio



Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2022-03-20 20:33:47 +00:00
Dario Nieuwenhuis
9941e0d012 Update stm32-data 2022-03-20 21:33:16 +01:00
bors[bot]
37ada65a33
Merge #669
669: Add SDMMC v1 and SDIO support r=Dirbaio a=chemicstry

SDMMC v2 peripheral is an extension of SDMMC v1 (or SDIO) so I managed to reuse most of the code, with some cfg's.

Apart from small differeces in registers, the biggest change is that v2 uses internal DMA, while v1 has to use shared DMA peripheral. This makes code a bit uglier, because DMA channel for v1 has to be passed around. Not sure if it's possible to make it any cleaner.

This also adds `TransferOptions` structure to DMA, because SDMMC v1 requires setting peripheral flow control and burst transfers. Let me know if some alternative way would be prefered.

I tested this on STM32F429ZIT6 (with sd card) and STM32H745ZIT6 (with oscilloscope).

Depends on: https://github.com/embassy-rs/stm32-data/pull/130

Co-authored-by: chemicstry <chemicstry@gmail.com>
2022-03-20 20:19:58 +00:00
bors[bot]
f0a071790d
Merge #673
673: Inline GPIO functions r=Dirbaio a=nviennot

All GPIO functions are monomorphized (per pin). Inlining these make the ROM smaller when using opt-level="z"

Co-authored-by: Nicolas Viennot <nicolas@viennot.biz>
2022-03-19 20:34:07 +00:00
Nicolas Viennot
4aba87f983 Inline GPIO functions
All GPIO functions are monomorphized (per pin). Inlining these make the
ROM smaller when using opt-level="z"
2022-03-19 14:06:11 -04:00
bors[bot]
f683b5d454
Merge #672
672: Reset peripherals on enable r=chemicstry a=chemicstry

Add reset on initialization to peripherals that did not have it before. This fixes problems when same peripheral is reinitialized at runtime multiple times.

Some exceptions:
- ADC: all ADCs share a single reset
- DCMI: does reset before enable - couldn't find anything about the order in the reference manual. Just keep it if it works?

I also fixed safety issues where global RCC registers where accessed without critical section.

Co-authored-by: chemicstry <chemicstry@gmail.com>
2022-03-17 23:47:45 +00:00
chemicstry
bdeb537ffa Fix compile for stm32wb 2022-03-18 01:33:39 +02:00
chemicstry
b30a42aff8 Fix RCC safety and add reset to DAC 2022-03-18 01:16:07 +02:00
chemicstry
ca88ace98d Reset peripherals on enable 2022-03-18 00:46:46 +02:00
bors[bot]
842a1ae30b
Merge #671
671: nrf/gpio: Make Input is_high/is_low public. r=Dirbaio a=Dirbaio



Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2022-03-17 22:28:32 +00:00
Dario Nieuwenhuis
6d994351a6 nrf/gpio: Make Input is_high/is_low public. 2022-03-17 23:27:55 +01:00
bors[bot]
5f39f13616
Merge #670
670: Make UART futures Send r=Dirbaio a=chemicstry

This is a quick fix to make `Uart` futures implement `Send`.

Previously they were `!Send`, because pointer to the data register was held across an await point. Simple rearrange fixes the issue.

Co-authored-by: chemicstry <chemicstry@gmail.com>
2022-03-17 18:09:57 +00:00
chemicstry
d26b751edc Add comments 2022-03-17 19:41:44 +02:00
chemicstry
051c6350ea Make UART futures Send 2022-03-17 18:23:47 +02:00
chemicstry
a9854924fa Revert settings.json 2022-03-17 02:22:04 +02:00
chemicstry
c24d482d51 Fix DMA channels 2022-03-17 01:54:56 +02:00
chemicstry
24a9e19062 More cleanup 2022-03-17 01:12:29 +02:00
chemicstry
f87c497315 Format 2022-03-17 00:03:24 +02:00
chemicstry
9d71acc49e Cleanup 2022-03-16 23:55:07 +02:00
chemicstry
224071f08e Add F7 example 2022-03-16 23:44:02 +02:00
chemicstry
f08f4df180 Cleanup 2022-03-16 20:33:46 +02:00
chemicstry
ea467e0acb Rename DMA trait 2022-03-16 20:30:57 +02:00
chemicstry
8a8e5c4b73 Fix SDMMC v2 and add H7 example 2022-03-16 20:20:39 +02:00
chemicstry
48fc48ea7d Fix BDMA 2022-03-16 19:41:34 +02:00
chemicstry
bf4a38ac06 Use RCC frequency instead of config 2022-03-16 19:09:37 +02:00
chemicstry
6d547b1143 SDIO working on stm32f4 2022-03-16 18:52:27 +02:00
chemicstry
34b5175d2c Add more options to DMA 2022-03-16 18:52:06 +02:00
bors[bot]
75e5b39799
Merge #668
668: Update chiptool. r=Dirbaio a=Dirbaio



Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2022-03-15 22:19:59 +00:00