Commit Graph

3428 Commits

Author SHA1 Message Date
bors[bot]
9f854110f2
Merge #1082 #1083
1082: stm32: Add basic support for DMA priority settings r=lulf a=matoushybl

This adds very basic support for specifying priority for DMA interrupts. Unfortunately, the patch now doesn't allow for specifying different priorities for DMA1/DMA2, or BDMA1/BDMA2, which I didn't know how to support.

1083: stm32: Fix H7 unaligned erase r=lulf a=matoushybl

This PR simplifies erasing sectors on the H7, which was buggy.

Co-authored-by: Matous Hybl <hyblmatous@gmail.com>
2022-12-01 13:49:59 +00:00
bors[bot]
d8ea297d6a
Merge #1088
1088: stm32: Enable fifo for buffered uart r=lulf a=matoushybl

This PR enables fifo for buffered uart where it is available. This should hopfully get rid of some overrun errors. I tried it in my application where it worked, but more intensive testing is probably required.

Co-authored-by: Matous Hybl <hyblmatous@gmail.com>
2022-12-01 13:34:52 +00:00
Matous Hybl
e1d7d8d841 stm32: Enable fifo for buffered uart 2022-11-30 22:17:51 +01:00
bors[bot]
eb010fbe33
Merge #1086
1086: rp: Add an RngCore impl based on ROSC.RANDOMBIT r=Dirbaio a=yodaldevoid

This has the potential to not be random, but it should not be an issue if default clock settings are used.

Co-authored-by: Gabriel Smith <ga29smith@gmail.com>
2022-11-30 19:10:44 +00:00
Gabriel Smith
71df28e269 rp: Add an RngCore impl based on ROSC.RANDOMBIT
This has the potential to not be random, but it should not be an issue
if default clock settings are used.
2022-11-30 14:06:05 -05:00
bors[bot]
645fb66a51
Merge #1087
1087: embassy-stm32: Allow SPI with DMA to implement blocking embbeded-hal traits r=Dirbaio a=guillaume-michel

Before this PR, on STM32, SPI with DMA do not implement embedded-hal blocking traits even if it is allowed by the hardware.

This PR fixes this issue.

I could not do the same thing for `embassy_embedded_hal::shared_bus::asynch::SpiDevice` because  I could not figure out how to deal with "non-blocking" mutex in a non async fn. Maybe someone has the answer...

Hope it is still useful as is.

Co-authored-by: Guillaume MICHEL <guillaume@squaremind.io>
2022-11-30 13:45:26 +00:00
Guillaume MICHEL
e0ea5dfdb2 embassy-stm32: Allow SPI with DMA to implement blocking embbeded-hal traits 2022-11-30 09:26:16 +01:00
bors[bot]
8436c6180f
Merge #1085
1085: Bump defmt-rtt to 0.4 r=Dirbaio a=Dirbaio

bors r+

Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2022-11-29 20:19:25 +00:00
Dario Nieuwenhuis
1dcb0ea1f5 Bump defmt-rtt to 0.4 2022-11-29 21:15:24 +01:00
bors[bot]
902586a019
Merge #1084
1084: Bump embedded-nal-async to 0.3.0 r=Dirbaio a=Dirbaio

bors r+

Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2022-11-29 11:07:07 +00:00
Dario Nieuwenhuis
3135ad016d Bump embedded-nal-async to 0.3.0 2022-11-29 12:05:46 +01:00
Christian Perez Llamas
199504be56 Optimization to be able to work with only 2 buffers 2022-11-29 01:09:47 +01:00
Matous Hybl
4cc0463123 stm32: Add basic support for DMA priority settings 2022-11-28 21:22:39 +01:00
Matous Hybl
2a35a09444 stm32: Fix H7 unaligned erase 2022-11-28 21:15:24 +01:00
bors[bot]
cea29d7de3
Merge #1079
1079: Async function in trait cleanup r=Dirbaio a=yodaldevoid

Some issues I ran across after the AFIT stuff was merged.

Co-authored-by: Gabriel Smith <ga29smith@gmail.com>
Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2022-11-27 23:13:41 +00:00
Dario Nieuwenhuis
787e5d4907 Add -time, -sync to CI with all features. 2022-11-28 00:12:13 +01:00
Gabriel Smith
aedcc472c9 time: Fix nighly feature compilation after upgrade to embedded-hal-async
0.2.0-alpha.0
2022-11-27 17:59:01 -05:00
Gabriel Smith
4d84b5469e Drive-by documentation link fixes 2022-11-27 16:32:18 -05:00
Gabriel Smith
3ca14ba4e9 usb-driver: Remove unncessary lifetime 2022-11-27 16:28:24 -05:00
Gabriel Smith
d438d1b685 sync: Fix nightly feature compilation after upgrade to embedded-io 0.4.0 2022-11-27 16:24:20 -05:00
Christian Perez Llamas
6b8ab32536 Use &mut self for start methods 2022-11-26 15:22:31 +01:00
Dario Nieuwenhuis
805b885de6
Merge pull request #1044 from embassy-rs/buffereduart-atomic
rp/uart: use lockfree ringbuffer.
2022-11-25 23:04:28 +01:00
Dario Nieuwenhuis
7b838d0336 rp/uart: use lockfree ringbuffer.
This gets rid of another PeripheralMutex usage.
2022-11-25 22:30:47 +01:00
Dario Nieuwenhuis
fa37452359
Merge pull request #974 from embassy-rs/afit
Switch to async-fn-in-trait
2022-11-25 22:09:57 +01:00
Dario Nieuwenhuis
1e2fb0459d Switch to async-fn-in-trait 2022-11-25 21:02:06 +01:00
bors[bot]
83c2f8f416
Merge #1077
1077: fix: bump embassy-boot version r=lulf a=lulf

bors r+

Co-authored-by: Ulf Lilleengen <lulf@redhat.com>
2022-11-25 14:53:35 +00:00
Ulf Lilleengen
09077f133d fix: bump embassy-boot version 2022-11-25 15:51:31 +01:00
bors[bot]
c7be481190
Merge #1075
1075: fix: add required metadata for embassy-boot r=lulf a=lulf



Co-authored-by: Ulf Lilleengen <lulf@redhat.com>
2022-11-25 13:12:24 +00:00
Ulf Lilleengen
89821846d7 fix: add required metadata for embassy-boot 2022-11-25 11:43:12 +01:00
Dario Nieuwenhuis
758f5d7ea2 Release embassy-executor v0.1.1 2022-11-23 14:53:18 +01:00
Dario Nieuwenhuis
f0ba22fc17
Merge pull request #1076 from embassy-rs/executor-docs-rs
executor: enable features for docs.rs
2022-11-23 14:52:17 +01:00
Dario Nieuwenhuis
db7e153fc0 executor: enable features for docs.rs
Otherwise the non-raw executor and the macros don't show up.
2022-11-23 14:49:40 +01:00
bors[bot]
a4f9e7cbcc
Merge #1071
1071: refactor: autodetect macro variant r=Dirbaio a=lulf

Apply heuristics using target_arch, target_os and target_family to determine which variant of the entry point to use.

Co-authored-by: Ulf Lilleengen <lulf@redhat.com>
2022-11-23 13:21:59 +00:00
Dario Nieuwenhuis
de95ab264d
Merge pull request #1073 from embassy-rs/revert-riscv-race
fix: revert race condition introduced for riscv
2022-11-23 14:00:26 +01:00
Ulf Lilleengen
04a7d97673
refactor: autodetect macro variant
Export all main macro per target architecture from embassy-macros,
and select the appropriate macro in embassy-executor.
2022-11-23 13:54:59 +01:00
@imrank03
5aad2129ef added the runner for stm32f091rc 2022-11-23 17:51:43 +05:30
Ulf Lilleengen
50c5cc5db6
fix: revert race condition introduced for riscv 2022-11-23 13:17:05 +01:00
bors[bot]
b76631bebe
Merge #1069
1069: GPIOTE InputChannel with mutable reference. r=Dirbaio a=Ardelean-Calin

Adding these changes enables us to define a channel using a mutable reference to `GPIOTE_CH(n)`, similar to how we can do with other drivers. So instead of using:
```rust
let p = embassy_nrf::init(config);
let freq_in = InputChannel::new(
    p.GPIOTE_CH0,
    Input::new(&mut p.P0_19, embassy_nrf::gpio::Pull::Up),
    embassy_nrf::gpiote::InputChannelPolarity::HiToLo,
);
```
we can use:
```rust
let p = embassy_nrf::init(config);
let freq_in = InputChannel::new(
    &mut p.GPIOTE_CH0,
    Input::new(&mut p.P0_19, embassy_nrf::gpio::Pull::Up),
    embassy_nrf::gpiote::InputChannelPolarity::HiToLo,
);
```
therefore not giving ownership to GPIOTE_CH0.

Co-authored-by: Ardelean Călin Petru <ardelean.calin@outlook.com>
Co-authored-by: Ardelean Calin <ardelean.calin@proton.me>
2022-11-23 12:17:02 +00:00
Ardelean Calin
eae67d0be8 Review comments. Corrected unused fields. 2022-11-23 14:16:18 +02:00
@imrank03
28991d7794 added blinky example for stm32f0 2022-11-23 17:30:58 +05:30
bors[bot]
2fa2c1a6fe
Merge #1054
1054: riscv fixes r=lulf a=swolix

With these changes I can run embassy on our RISC-V processor, please consider merging this, feedback is very welcome.

I don't fully understand the code in the executor, but I have implemented a critical section by globally disabling interrupts, which means the wfi inside the critical section will hang the whole thing.

Co-authored-by: Sijmen Woutersen <sijmen.woutersen@gmail.com>
2022-11-23 09:24:11 +00:00
bors[bot]
83b199a874
Merge #1056
1056: embassy-nrf: Add TWIS module r=Dirbaio a=kalkyl

Verified to be working on nrf9160

Co-authored-by: kalkyl <henrik.alser@me.com>
Co-authored-by: Henrik Alsér <henrik.alser@me.com>
2022-11-22 21:50:42 +00:00
Henrik Alsér
cf900a8a3f Rename write to respond_to_read 2022-11-22 22:10:04 +01:00
Ardelean Calin
4f2f375777 Corrected order of use statements. 2022-11-22 17:45:05 +02:00
Ardelean Calin
e7c876d744 Changed pin to private as it is for OutputChannel 2022-11-22 17:36:22 +02:00
Ardelean Calin
64c2e1b9b6 Switched to PeripheralRef for channel. 2022-11-22 17:35:38 +02:00
bors[bot]
61be0e75c8
Merge #1068
1068: Add Default to some types r=Dirbaio a=mkj

These are a couple of places I've found `Default` to be handy

Co-authored-by: Matt Johnston <matt@ucc.asn.au>
2022-11-22 15:04:24 +00:00
Ardelean Călin Petru
a074cd0625
Update gpiote.rs
Adding these changes enables us to define a channel using a mutable reference to `GPIOTE_CH(n)`, similar to how we can do with other drivers.
So instead of using:
```rust
let freq_in = InputChannel::new(
    p.GPIOTE_CH0,
    Input::new(&mut p.P0_19, embassy_nrf::gpio::Pull::Up),
    embassy_nrf::gpiote::InputChannelPolarity::HiToLo,
);
```
we can use:
```rust
let freq_in = InputChannel::new(
    &mut p.GPIOTE_CH0,
    Input::new(&mut p.P0_19, embassy_nrf::gpio::Pull::Up),
    embassy_nrf::gpiote::InputChannelPolarity::HiToLo,
);
```
2022-11-22 16:56:04 +02:00
bors[bot]
ca4f615b25
Merge #1067
1067: doc: update cargo manifests with keywords r=lulf a=lulf



Co-authored-by: Ulf Lilleengen <lulf@redhat.com>
2022-11-22 13:59:28 +00:00
Matt Johnston
536b6a2de5 sync/signal: Implement Default for Signal 2022-11-22 21:55:42 +08:00