Thales Fragoso
e07dda8707
stm32: Adjust some fences around DMA
...
Also bump stm32-data
2021-06-30 18:58:21 -03:00
Bob McWhirter
f3b9c97763
Change atomics and add a fence.
2021-06-30 10:17:25 -04:00
Bob McWhirter
cf5b7dc943
Because IntelliJ makes life hard.
2021-06-30 10:03:18 -04:00
Bob McWhirter
6a0b0f3162
Enable RCC within the USART itself.
2021-06-30 09:57:27 -04:00
Bob McWhirter
e1736114d4
Remove paste.
2021-06-30 09:44:28 -04:00
Bob McWhirter
07a6686879
Protect DMA-related things with cfg.
2021-06-29 13:00:52 -04:00
Bob McWhirter
6b78d56ceb
Formatting.
2021-06-29 12:48:58 -04:00
Bob McWhirter
c53ab325c1
Wire up DMA with USART v1.
2021-06-29 11:01:57 -04:00
Bob McWhirter
b88fc2847a
Checkpoint with lifetime issues.
2021-06-29 11:01:57 -04:00
Thales Fragoso
c5022b1196
stm32: Make sure Output gpio driver is pushpull
2021-06-27 13:25:35 -03:00
Thales Fragoso
0eaadfc125
stm32: Update gpio examples
2021-06-25 18:16:43 -03:00
Thales Fragoso
a3f0aa02a4
Separate OpenDrain pin to a new type
2021-06-25 17:22:51 -03:00
Thales Fragoso
efb3b3a0a8
stm32: Allow for open drain configuration for output pin
2021-06-24 20:42:43 -03:00
Thales Fragoso
013792b944
Separate exti into v1 and v2
2021-06-24 20:28:06 -03:00
Thales Fragoso
1c33a3b94c
#[cfg] exti
2021-06-24 19:41:04 -03:00
Thales Fragoso
210104e6dc
Remove unused gpio_af from codegen
2021-06-24 19:23:51 -03:00
Thales Fragoso
409884be2a
Add F0 RCC
2021-06-24 19:21:56 -03:00
Thales Fragoso
797534d1a6
Update features to include F0
2021-06-22 14:41:42 -03:00
Dario Nieuwenhuis
5a4e3ceb88
Update stm32-data (adds DBGMCU to all chips)
2021-06-21 01:38:59 +02:00
Thales Fragoso
098ce6e740
stm32h7: Add ethernet example
2021-06-16 16:48:35 +02:00
Thales Fragoso
77546825a1
stm32: Make vcell dependency optional
2021-06-16 16:48:35 +02:00
Thales Fragoso
598201bff3
eth-v2: Make embassy-net optional
2021-06-16 16:48:35 +02:00
Thales Fragoso
6cecc6d4b5
eth-v2: Get hclk frequency from clock singleton
2021-06-16 16:48:35 +02:00
Thales Fragoso
f7e1f262af
eth-v2: Enable source address filtering
2021-06-16 16:48:35 +02:00
Thales Fragoso
ffc19a54d6
eth-v2: Fix bug in Rx descriptors and add docs art
2021-06-16 16:48:35 +02:00
Thales Fragoso
6daa55a897
eth-v2: Fix setting the registers for the descriptors
...
Also, the interrupts are set to 1 to clear, the manual could have helped
with that one...
2021-06-16 16:48:35 +02:00
Thales Fragoso
0b42e12604
eth-v2: Fix off by one bug
2021-06-16 16:48:35 +02:00
Thales Fragoso
54ad2a41f1
eth-v2: Work around missing AF for REF_CLK
2021-06-16 16:48:35 +02:00
Thales Fragoso
0c837f07c0
eth-v2: Enable clocks in new
2021-06-16 16:48:35 +02:00
Thales Fragoso
e039c7c42c
eth-v2: Remove Instance trait
2021-06-16 16:48:35 +02:00
Thales Fragoso
05a239faf6
eth-v2: Implement embassy-net's Device Trait and fix Drop
2021-06-16 16:48:35 +02:00
Thales Fragoso
4cffa200bd
eth: Add lan8742a PHY
2021-06-16 16:48:35 +02:00
Thales Fragoso
46e1bae9e3
eth-v2: Start Ethernet peripheral implementation
2021-06-16 16:48:35 +02:00
Ulf Lilleengen
56c5218292
Prescaler 1 means divide by 3 on WL55
2021-06-16 16:21:16 +02:00
Ulf Lilleengen
383beb37b3
Rename from wl55 to wl5x and enable debug wfe
2021-06-16 16:07:21 +02:00
Ulf Lilleengen
b6a8703698
Add support for generating PAC for dual cores
...
* Chips that have multiple cores will be exposed as chipname_corename,
i.e. stm32wl55jc_cm4
* Chips that have single cores will use the chip family as feature name
and pick the first and only core from the list
* Add support for stm32wl55 chip family
2021-06-16 15:12:07 +02:00
Ulf Lilleengen
8ae4f47d3d
Fix compile
2021-06-15 16:44:00 +02:00
Ulf Lilleengen
49fad2de8a
Use correct frequencies for timers
2021-06-15 16:07:23 +02:00
Ulf Lilleengen
4b406dd107
Remove default rcc impl
2021-06-14 20:24:51 +02:00
Bob McWhirter
d58fb11b2e
ADCv3 and example.
2021-06-14 13:20:42 -04:00
Ulf Lilleengen
531093f281
Derive SPI v1 and v3 clocks automatically
2021-06-14 11:58:16 +02:00
Ulf Lilleengen
5e1b0a5398
Add wb55 clocks
2021-06-14 11:41:02 +02:00
Ulf Lilleengen
ee9f67fa01
Add common types
2021-06-14 11:33:11 +02:00
Ulf Lilleengen
a2da2a6db2
Remove unused l0 code
2021-06-14 11:33:11 +02:00
Ulf Lilleengen
95532726b2
Add minimal RCC impls for L4 and F4
2021-06-14 11:33:11 +02:00
Ulf Lilleengen
a13e07625f
Add ... c1?
2021-06-14 11:33:11 +02:00
Ulf Lilleengen
0b52731897
Add clocks for h7
2021-06-14 11:33:11 +02:00
Ulf Lilleengen
2c63393c9e
Add Clock type per RCC family
2021-06-14 11:33:11 +02:00
Ulf Lilleengen
952f525af5
Provide a way for a peripheral to query its clock frequency
...
Currently this looks up the frequency in the global singleton that must
be initialized by the per-chip RCC implementation. At present, this is
only done for the L0 family of chips.
2021-06-14 11:33:11 +02:00
Dominik Boehi
9edb6e41ce
Make gen.py work without CSafeLoader
2021-06-12 18:28:21 +02:00
