Commit Graph

4701 Commits

Author SHA1 Message Date
bors[bot]
b05cd77a62
Merge #1170
1170: nrf: add support for UICR configuration. r=Dirbaio a=Dirbaio

- APPROTECT enable/disable. Notably this fixes issues with nrf52-rev3 and nrf53 from locking itself at reset.
- Use NFC pins as GPIO.
- Use RESET pin as GPIO.

NFC and RESET pins singletons are made available only when usable as GPIO, for compile-time checking.

TODO: test
- [x] nrf52 rev1
- [x] nrf52 rev3
- [x] nrf53
- [x] nrf91

Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2023-02-20 00:47:15 +00:00
Dario Nieuwenhuis
7fa478358a nrf: warn if uicr configuration could not be written.
If the user requests some configuration, but UICR is already programmed
to something else, detect this and warn the user.

We don't do it for the debug port settings, because if they are wrong
then the user will simply not be able to read debug logs.
2023-02-20 01:31:02 +01:00
Dario Nieuwenhuis
3f88bf6f9b nrf: add support for UICR configuration.
- APPROTECT enable/disable. Notably this fixes issues with nrf52-rev3 and nrf53 from locking itself at reset.
- Use NFC pins as GPIO.
- Use RESET pin as GPIO.

NFC and RESET pins singletons are made available only when usable as GPIO,
for compile-time checking.
2023-02-20 01:28:45 +01:00
bors[bot]
a2bd37be40
Merge #1221
1221: examples/stm32wb: do not reserve words at start of RAM. r=Dirbaio a=Dirbaio

They're used to communicate from the app to ST's OTA bootloader. See AN5247. 

This bootloader is optional, must be flashed by the user, and requires changing the FLASH start address as well, so the current memory regions still require modifications to use it. Therefore there's no point in reserving these words.

Thanks `@adamgreig` for investigating the purpose.

bors r+

Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2023-02-20 00:01:22 +00:00
Dario Nieuwenhuis
13328c58d3
examples/stm32wb: do not reserve words at start of RAM.
They're used to communicate from the app to ST's OTA bootloader. See AN5247. 

This bootloader is optional, must be flashed by the user, and requires changing the FLASH start address as well, so the current memory regions still require modifications to use it. Therefore there's no point in reserving these words.

Thanks @adamgreig for investigating the purpose.
2023-02-20 01:01:01 +01:00
bors[bot]
1567e724f9
Merge #1218 #1219
1218: Lora: sx126x: Change timing window to match values found experimentally. r=Dirbaio a=CBJamo

As mentioned in #1188.

1219: stm32/sdmmc: Fix SDIOv1 writes r=Dirbaio a=chemicstry

This fixes writes on sdmmc v1 (SDIO). I'm pretty sure I tested writes in #669, but maybe I was just lucky or I just forgot.

There were two problems:
- Writes require DMA FIFO mode, otherwise SDIO FIFO is under/overrun depending on sdio/pclk2 clock ratio.
- Hardware flow control is broken for sdmmc v1 (I checked F1 and F4 erratas). This causes clock glitches above 12 MHz and results in write CRC errors.

Co-authored-by: Caleb Jamison <caleb@cbjamo.com>
Co-authored-by: chemicstry <chemicstry@gmail.com>
2023-02-19 23:01:44 +00:00
bors[bot]
4ad255b34b
Merge #1217
1217: Fix a typo in "PioPeripheral" r=Dirbaio a=SekoiaTree

Renames "PioPeripherial" to "PioPeripheral" (without the second i).

Co-authored-by: sekoia <sequoia.1009@gmail.com>
2023-02-19 22:46:57 +00:00
bors[bot]
4fd59f26fb
Merge #1220
1220: examples/stm32wb: fix linker script. r=Dirbaio a=Dirbaio

cortex-m-rt 0.7.2 now enforces the stack is 8-byte aligned. Stack is placed at `ORIGIN(RAM) + LENGTH(RAM)` by default, which wasn't 8-byte-aligned. See https://github.com/rust-embedded/cortex-m/discussions/469

ST trims 8 bytes from start of RAM, and uses the whole 192kb, so let's just copy that:

bceb1dae09/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/linker/stm32wb55xx_flash_cm4.ld (L48)

bors r+

Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2023-02-19 22:03:13 +00:00
Dario Nieuwenhuis
272982ee54 examples/stm32wb: fix linker script.
cortex-m-rt 0.7.2 now enforces the stack is 8-byte aligned. Stack is placed
at `ORIGIN(RAM) + LENGTH(RAM)` by default, which wasn't 8-byte-aligned. See https://github.com/rust-embedded/cortex-m/discussions/469

ST trims 8 bytes from start of RAM, and uses the whole 192kb, so let's just
copy that:

bceb1dae09/Drivers/CMSIS/Device/ST/STM32WBxx/Source/Templates/gcc/linker/stm32wb55xx_flash_cm4.ld (L48)
2023-02-19 23:02:31 +01:00
chemicstry
a53f525f51 stm32/sdmmc: Fix SDIOv1 writes 2023-02-18 01:37:06 +02:00
Caleb Jamison
7783e0ebb1 Change timing window to match values found experimentally. 2023-02-17 07:43:19 -05:00
sekoia
e641db1f75 Fix a typo in "PioPeripheral" 2023-02-15 14:10:07 +01:00
Dario Nieuwenhuis
e3492862e9
Merge pull request #38 from overheat/master
update embassy dependences
2023-02-15 12:34:45 +01:00
Aaron Tsui
0bcd1b1e10 update embassy dependences 2023-02-15 11:08:27 +08:00
bors[bot]
e3f8020c3b
Merge #1215
1215: Add clone to embassy_rp::gpio::Level r=Dirbaio a=Slushee-a

Allows you to wite a cleaner state change detector. Example:
```rs
let mut button_state: Level = Level::Low;
let mut prev_button_state: Level = button_state;

loop {
    button_state = button.get_level();

    if prev_button_state != button_state {
        led.set_level(button_state);  // Takes ownership of button_state. 
    }

    prev_button_state = button_state; // Can't be done since the ownership has been moved.
                                      // Adding Clone makes this code possible
}
```

Co-authored-by: Slushee <55996847+Slushee-a@users.noreply.github.com>
2023-02-13 17:31:47 +00:00
Slushee
dfc58ad3a2
Add copy to Level enum in embassy-rp gpio module 2023-02-13 17:29:35 +00:00
Slushee
1626a4a74b
Add clone to embassy_rp::gpio::Level 2023-02-13 17:12:50 +00:00
Mathias
5e74926907 feature-gate variants without vals defined 2023-02-13 15:46:49 +01:00
Mathias
218b44652c Rebase on master 2023-02-13 14:55:15 +01:00
Dario Nieuwenhuis
41a563aae3 net: document all features 2023-02-13 03:11:16 +01:00
Dario Nieuwenhuis
363054de98 stm32: doc all chips. 2023-02-13 03:02:12 +01:00
bors[bot]
06abde8676
Merge #1213
1213: stm32: fix fmc-related build failures on some F4's r=Dirbaio a=Dirbaio

f413vh has a peripheral named `FSMC` but using the `FMC` regs. This might be a mistake? `@rmja`

Fix build for now, we can investigate later if the regs are OK.

bors r+

Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2023-02-13 01:40:58 +00:00
Dario Nieuwenhuis
4e15043fc2 add stm32f413vh to CI 2023-02-13 02:40:29 +01:00
Dario Nieuwenhuis
951f208915 Add more crates to docs. 2023-02-13 02:39:03 +01:00
Dario Nieuwenhuis
1e36c91bf8 stm32: fix fmc-related build failures on some F4's 2023-02-13 02:22:06 +01:00
Dario Nieuwenhuis
80b7c3cf69 Fix doc build. 2023-02-13 01:30:53 +01:00
bors[bot]
d159a6c62d
Merge #1211
1211: Fix rcc prescaler for wl55 HCLK1 r=lulf a=chrenderle

fix "prescaler none" which incorrectly set "prescaler divided by 3"
Issue: #1168 

Co-authored-by: Christian Enderle <mail@chrenderle.de>
2023-02-12 11:00:22 +00:00
Christian Enderle
d21643c060 fix "prescaler none" which incorrectly set "prescaler divided by 3" 2023-02-12 11:36:57 +01:00
Dario Nieuwenhuis
e1eac15c42
Merge pull request #1185 from embassy-rs/dns-impl
Add DNS socket to embassy-net
2023-02-10 23:53:25 +01:00
Dario Nieuwenhuis
76642b3a3c fix h7 examples 2023-02-10 23:35:44 +01:00
bors[bot]
20c1dd112c
Merge #1210
1210: nrf/qspi: do not panic when canceling futures. r=Dirbaio a=Dirbaio

QSPI can't cancel DMA transfers. Before we'd panic on cancel, now we blocking-wait instead.

Blocking is not great, but it's better than panicking, especially when using code that's hardware-agnostic through the embedded-storage traits.

Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
2023-02-10 22:13:56 +00:00
Dario Nieuwenhuis
4c4e923e05 nrf/qspi: do not panic when canceling futures. 2023-02-10 23:03:16 +01:00
Dario Nieuwenhuis
a509af4bc0 exmaples/dns: don't use the socket. 2023-02-10 23:00:16 +01:00
Ulf Lilleengen
a2b8921ff3
fix: cfg guard for ipv6 2023-02-10 19:38:17 +01:00
Ulf Lilleengen
128a453163
remove unneeded features 2023-02-10 19:04:54 +01:00
Ulf Lilleengen
a7d3ef9122
scope dns operations within a cfged block 2023-02-10 19:00:00 +01:00
Ulf Lilleengen
32c3725631
add waker for DNS slots 2023-02-10 18:44:51 +01:00
Ulf Lilleengen
48dff04d64
Bump max queries 2023-02-10 18:34:21 +01:00
Ulf Lilleengen
472473d8c1
Create slice using ::Owned 2023-02-10 18:32:35 +01:00
Ulf Lilleengen
6e68353a93
attempt removing option 2023-02-10 18:30:17 +01:00
Ulf Lilleengen
7ae47cb1d8
Expose api on Stack and add doc
Make it work with smoltcp 0.9
2023-02-10 18:20:50 +01:00
Ulf Lilleengen
cd440a49d6
Rewrite to use a single socket 2023-02-10 17:46:08 +01:00
Ulf Lilleengen
614740a1b2
cargo fmt 2023-02-10 17:45:25 +01:00
Ulf Lilleengen
c203cefe01
Handle cancellation 2023-02-10 17:45:19 +01:00
Ulf Lilleengen
9cfea693ed
Add DNS socket to embassy-net 2023-02-10 17:45:03 +01:00
bors[bot]
023b0d5b22
Merge #1209
1209: Time: Add from_hz function for Duration. r=Dirbaio a=CBJamo

I found myself doing things like this

```rust
    let rate_us = 1_000_000 / rate_hz;
    let mut ticker = Ticker::every(Duration::from_micros(rate_us));
```

Several times, and figured it was worth adding a little convenience function to handle that. This also makes the calculation const, which is a nice little upside. The compiler might have been doing that already, but this makes sure. 

Speaking of const, would it be better to give hz as a float? Obviously we'd want to avoid that at runtime since many targets don't have a fpu, but if it's at compile time that doesn't matter and a float may be more ergonomic.

Co-authored-by: Caleb Jamison <caleb@cbjamo.com>
2023-02-10 02:19:31 +00:00
Caleb Jamison
bd7b3bd455 Clamp ticks to 1 and round to nearest. 2023-02-09 20:57:27 -05:00
Caleb Jamison
a4371e9544 Add from_hz function for Duration. 2023-02-09 19:22:06 -05:00
bors[bot]
e1a0df7d46
Merge #1205
1205: stm32/rng Fix rng generation lock-up r=Dirbaio a=lucasgranberg

This PR fixes a problem where the device gets locked in case of rng errors.

The PR also includes a hack for stm32wl based devices where the more complicated RNG peripheral can get stuck on seed errors.

Co-authored-by: Lucas Granberg <lukkeg@gmail.com>
2023-02-09 11:39:52 +00:00
Lucas Granberg
2b6654541d rustfmt 2023-02-09 13:01:44 +02:00