1099: rp: implement input for OutputOpenDrain r=Dirbaio a=Dirbaio
Needed for onewire and similar protocols.
Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
1089: feat: embassy-boot for rp2040 r=Dirbaio a=lulf
Add embassy-boot support for RP2040, with examples for the Raspberry Pi Pico.
Co-authored-by: Ulf Lilleengen <lulf@redhat.com>
The "must not be called reentrantly" invariant is too "global" to
maintain comfortably, and the cost of the RefCell is negligible,
so this was a case of premature optimization.
1074: Added blinky example for stm32f0 r=lulf a=imrank03
Hi, I have added **blinky** example for `stm32f0` and tested with Nucleo board `STM32F091RC`.
- Can I add more example for stm32f0?
Co-authored-by: @imrank03 <immu0396@gmail.com>
1082: stm32: Add basic support for DMA priority settings r=lulf a=matoushybl
This adds very basic support for specifying priority for DMA interrupts. Unfortunately, the patch now doesn't allow for specifying different priorities for DMA1/DMA2, or BDMA1/BDMA2, which I didn't know how to support.
1083: stm32: Fix H7 unaligned erase r=lulf a=matoushybl
This PR simplifies erasing sectors on the H7, which was buggy.
Co-authored-by: Matous Hybl <hyblmatous@gmail.com>
1088: stm32: Enable fifo for buffered uart r=lulf a=matoushybl
This PR enables fifo for buffered uart where it is available. This should hopfully get rid of some overrun errors. I tried it in my application where it worked, but more intensive testing is probably required.
Co-authored-by: Matous Hybl <hyblmatous@gmail.com>
1086: rp: Add an RngCore impl based on ROSC.RANDOMBIT r=Dirbaio a=yodaldevoid
This has the potential to not be random, but it should not be an issue if default clock settings are used.
Co-authored-by: Gabriel Smith <ga29smith@gmail.com>
1087: embassy-stm32: Allow SPI with DMA to implement blocking embbeded-hal traits r=Dirbaio a=guillaume-michel
Before this PR, on STM32, SPI with DMA do not implement embedded-hal blocking traits even if it is allowed by the hardware.
This PR fixes this issue.
I could not do the same thing for `embassy_embedded_hal::shared_bus::asynch::SpiDevice` because I could not figure out how to deal with "non-blocking" mutex in a non async fn. Maybe someone has the answer...
Hope it is still useful as is.
Co-authored-by: Guillaume MICHEL <guillaume@squaremind.io>
1079: Async function in trait cleanup r=Dirbaio a=yodaldevoid
Some issues I ran across after the AFIT stuff was merged.
Co-authored-by: Gabriel Smith <ga29smith@gmail.com>
Co-authored-by: Dario Nieuwenhuis <dirbaio@dirbaio.net>
1071: refactor: autodetect macro variant r=Dirbaio a=lulf
Apply heuristics using target_arch, target_os and target_family to determine which variant of the entry point to use.
Co-authored-by: Ulf Lilleengen <lulf@redhat.com>
1069: GPIOTE InputChannel with mutable reference. r=Dirbaio a=Ardelean-Calin
Adding these changes enables us to define a channel using a mutable reference to `GPIOTE_CH(n)`, similar to how we can do with other drivers. So instead of using:
```rust
let p = embassy_nrf::init(config);
let freq_in = InputChannel::new(
p.GPIOTE_CH0,
Input::new(&mut p.P0_19, embassy_nrf::gpio::Pull::Up),
embassy_nrf::gpiote::InputChannelPolarity::HiToLo,
);
```
we can use:
```rust
let p = embassy_nrf::init(config);
let freq_in = InputChannel::new(
&mut p.GPIOTE_CH0,
Input::new(&mut p.P0_19, embassy_nrf::gpio::Pull::Up),
embassy_nrf::gpiote::InputChannelPolarity::HiToLo,
);
```
therefore not giving ownership to GPIOTE_CH0.
Co-authored-by: Ardelean Călin Petru <ardelean.calin@outlook.com>
Co-authored-by: Ardelean Calin <ardelean.calin@proton.me>
1054: riscv fixes r=lulf a=swolix
With these changes I can run embassy on our RISC-V processor, please consider merging this, feedback is very welcome.
I don't fully understand the code in the executor, but I have implemented a critical section by globally disabling interrupts, which means the wfi inside the critical section will hang the whole thing.
Co-authored-by: Sijmen Woutersen <sijmen.woutersen@gmail.com>
