Thales Fragoso
77546825a1
stm32: Make vcell dependency optional
2021-06-16 16:48:35 +02:00
Thales Fragoso
598201bff3
eth-v2: Make embassy-net optional
2021-06-16 16:48:35 +02:00
Thales Fragoso
3396a51938
net: Add features for pool size and remove unwrap on smoltcp device
2021-06-16 16:48:35 +02:00
Thales Fragoso
6cecc6d4b5
eth-v2: Get hclk frequency from clock singleton
2021-06-16 16:48:35 +02:00
Thales Fragoso
f7e1f262af
eth-v2: Enable source address filtering
2021-06-16 16:48:35 +02:00
Thales Fragoso
ffc19a54d6
eth-v2: Fix bug in Rx descriptors and add docs art
2021-06-16 16:48:35 +02:00
Thales Fragoso
6daa55a897
eth-v2: Fix setting the registers for the descriptors
...
Also, the interrupts are set to 1 to clear, the manual could have helped
with that one...
2021-06-16 16:48:35 +02:00
Thales Fragoso
0b42e12604
eth-v2: Fix off by one bug
2021-06-16 16:48:35 +02:00
Thales Fragoso
54ad2a41f1
eth-v2: Work around missing AF for REF_CLK
2021-06-16 16:48:35 +02:00
Thales Fragoso
0c837f07c0
eth-v2: Enable clocks in new
2021-06-16 16:48:35 +02:00
Thales Fragoso
e039c7c42c
eth-v2: Remove Instance trait
2021-06-16 16:48:35 +02:00
Thales Fragoso
05a239faf6
eth-v2: Implement embassy-net's Device Trait and fix Drop
2021-06-16 16:48:35 +02:00
Thales Fragoso
4cffa200bd
eth: Add lan8742a PHY
2021-06-16 16:48:35 +02:00
Thales Fragoso
46e1bae9e3
eth-v2: Start Ethernet peripheral implementation
2021-06-16 16:48:35 +02:00
Dario Nieuwenhuis
6386c34079
Merge pull request #250 from lulf/dual-core
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Add support for generating PAC for dual cores
2021-06-16 16:46:01 +02:00
Ulf Lilleengen
a4ea08f89f
Update submodule
2021-06-16 16:31:12 +02:00
Ulf Lilleengen
56c5218292
Prescaler 1 means divide by 3 on WL55
2021-06-16 16:21:16 +02:00
Ulf Lilleengen
383beb37b3
Rename from wl55 to wl5x and enable debug wfe
2021-06-16 16:07:21 +02:00
Ulf Lilleengen
b6a8703698
Add support for generating PAC for dual cores
...
* Chips that have multiple cores will be exposed as chipname_corename,
i.e. stm32wl55jc_cm4
* Chips that have single cores will use the chip family as feature name
and pick the first and only core from the list
* Add support for stm32wl55 chip family
2021-06-16 15:12:07 +02:00
Dario Nieuwenhuis
927be50109
Merge pull request #249 from embassy-rs/nrf-pacs
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nrf: use released nrf52805-pac, nrf52820-pac
2021-06-15 23:12:55 +02:00
Dario Nieuwenhuis
76ae9e0e7c
nrf: use released nrf52805-pac, nrf52820-pac
2021-06-15 22:25:37 +02:00
Dario Nieuwenhuis
c9bf039cae
Merge pull request #248 from lulf/add-timer-frequencies
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Add separate fields for timer frequencies
2021-06-15 17:29:48 +02:00
Ulf Lilleengen
8ae4f47d3d
Fix compile
2021-06-15 16:44:00 +02:00
Ulf Lilleengen
49fad2de8a
Use correct frequencies for timers
2021-06-15 16:07:23 +02:00
Dario Nieuwenhuis
ceb5d92da3
Merge pull request #246 from lulf/remove-default-rcc
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Remove default rcc impl
2021-06-14 20:30:02 +02:00
Ulf Lilleengen
4b406dd107
Remove default rcc impl
2021-06-14 20:24:51 +02:00
Dario Nieuwenhuis
fd24677f84
Merge pull request #245 from bobmcwhirter/adc_v3
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ADCv3 and example.
2021-06-14 19:26:42 +02:00
Bob McWhirter
d58fb11b2e
ADCv3 and example.
2021-06-14 13:20:42 -04:00
Dario Nieuwenhuis
0dafd8f763
Merge pull request #241 from lulf/get-clock-frequencies
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Provide a way for a peripheral to query its clock frequency
2021-06-14 16:22:14 +02:00
Ulf Lilleengen
531093f281
Derive SPI v1 and v3 clocks automatically
2021-06-14 11:58:16 +02:00
Ulf Lilleengen
5e1b0a5398
Add wb55 clocks
2021-06-14 11:41:02 +02:00
Ulf Lilleengen
ee9f67fa01
Add common types
2021-06-14 11:33:11 +02:00
Ulf Lilleengen
a2da2a6db2
Remove unused l0 code
2021-06-14 11:33:11 +02:00
Ulf Lilleengen
95532726b2
Add minimal RCC impls for L4 and F4
2021-06-14 11:33:11 +02:00
Ulf Lilleengen
a13e07625f
Add ... c1?
2021-06-14 11:33:11 +02:00
Ulf Lilleengen
0b52731897
Add clocks for h7
2021-06-14 11:33:11 +02:00
Ulf Lilleengen
2c63393c9e
Add Clock type per RCC family
2021-06-14 11:33:11 +02:00
Ulf Lilleengen
952f525af5
Provide a way for a peripheral to query its clock frequency
...
Currently this looks up the frequency in the global singleton that must
be initialized by the per-chip RCC implementation. At present, this is
only done for the L0 family of chips.
2021-06-14 11:33:11 +02:00
Dario Nieuwenhuis
85f172dd93
Merge pull request #244 from Tiwalun/fix-gen-macos
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Make gen.py work without CSafeLoader
2021-06-12 20:20:09 +02:00
Dominik Boehi
9edb6e41ce
Make gen.py work without CSafeLoader
2021-06-12 18:28:21 +02:00
Dario Nieuwenhuis
97e2f10665
Merge pull request #242 from Tiwalun/stm32wb55-metapac
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Initial support and example for STM32WB55
2021-06-12 16:33:40 +02:00
Dominik Boehi
b82e2627aa
Add STM32WB55 examples to CI, fix example crate name
2021-06-12 07:06:42 +02:00
Dominik Boehi
0eab96f573
Initial support and example for STM32WB55
2021-06-12 07:06:36 +02:00
Dario Nieuwenhuis
3353f59a43
Merge pull request #243 from embassy-rs/update-smoltcp
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UPdate smoltcp
2021-06-12 00:56:24 +02:00
Dario Nieuwenhuis
890e93f367
UPdate smoltcp
2021-06-12 00:50:36 +02:00
Ulf Lilleengen
def8870cbb
Merge pull request #240 from lulf/enable-timer-clock
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Enable timer clock in RCC on timer start
2021-06-11 16:30:54 +02:00
Ulf Lilleengen
6c7fd3e3c4
Refactor
2021-06-11 16:21:51 +02:00
Ulf Lilleengen
8dd3ddd228
Special handling for timers instead
2021-06-10 09:52:57 +02:00
Ulf Lilleengen
0a9022d59f
Enable timer clock in RCC on timer start
...
* Moves the tim2-specific code into macro which always uses TIM2
* For peripherals without clock specified, attempt to locate enable and
reset registers in the RCC block matching the peripheral name. This
could be useful for peripherals where deducing the clock name might
not be feasible, but it remains to be tested with more chip families
to see if it is sufficiently accurate.
2021-06-10 09:37:30 +02:00
Ulf Lilleengen
37fbc5fcc4
Merge pull request #239 from lulf/add-h7ab-missing
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Update reference to missing H7AB
2021-06-10 09:04:22 +02:00
