Commit Graph

5749 Commits

Author SHA1 Message Date
bors[bot]
ce1078994d
Merge #1479
1479: Move stm32 to bind_interrupts r=xoviat a=xoviat



Co-authored-by: xoviat <xoviat@users.noreply.github.com>
2023-05-24 23:47:35 +00:00
xoviat
b6ba1ea53a stm32: move lora to bind_interrupts 2023-05-24 18:09:04 -05:00
xoviat
316be179af stm32: move to bind_interrupts
disable lora functionality for now
2023-05-24 17:29:56 -05:00
Rasmus Melchior Jacobsen
e785e1bc22 Add ConcatFlash utility 2023-05-24 14:40:34 +02:00
Dario Nieuwenhuis
3cc0ec654a
Merge pull request #83 from papyDoctor/master
Update examples in README.md
2023-05-24 11:41:03 +00:00
Olivier Monnom
a19f8c32ff
Update examples in README.md 2023-05-24 09:22:05 +02:00
Rasmus Melchior Jacobsen
87acf5f50f Add missing set_default_layout() in "other" family 2023-05-23 23:01:55 +02:00
Rasmus Melchior Jacobsen
14e3e72b0f Add missing implementations for f4 alternate regions 2023-05-23 22:51:26 +02:00
Rasmus Melchior Jacobsen
faf506b300 Remove Drop for AltFlashLayout 2023-05-23 22:50:41 +02:00
Rasmus Melchior Jacobsen
879c621394 Ensure FlashRegion can only be created within this crate 2023-05-23 22:49:27 +02:00
bors[bot]
627d7f66ef
Merge #1477
1477: embassy-embedded-hal: Add i2c transaction to I2cDevice r=Dirbaio a=CBJamo

Not sure why this was a todo before, but this seems to be working fine in my limited testing.

Co-authored-by: Caleb Jamison <caleb@hellbender.com>
2023-05-23 09:20:44 +00:00
Caleb Jamison
3ad52f837d Remove debug 2023-05-22 21:31:00 -04:00
Caleb Jamison
49eaf000b8 Add i2c transaction 2023-05-22 21:26:03 -04:00
bors[bot]
1fdde8f03f
Merge #1457
1457: TL Mbox read and write for stm32wb r=xoviat a=OueslatiGhaith

Hello,

This pull request is related to #1397 and #1401, inspired by #24, built upon the work done in #1405 and #1424, and was tested on an stm32wb55rg.

This pull request aims to add read and write functionality to the TL mailbox for stm32wb microcontrollers

Co-authored-by: goueslati <ghaith.oueslati@habemus.com>
Co-authored-by: xoviat <xoviat@users.noreply.github.com>
2023-05-23 01:15:22 +00:00
xoviat
64092169e3 stm32/ipcc: disable test 2023-05-22 20:14:37 -05:00
Rasmus Melchior Jacobsen
187551f914 Move module documentation 2023-05-22 16:55:18 +02:00
Rasmus Melchior Jacobsen
cd1bf31fed Add YieldingAsync adapter 2023-05-22 16:48:31 +02:00
Rasmus Melchior Jacobsen
d54eb1107e Yield between BlockingAsync NorFlash write and erase operations 2023-05-22 15:57:20 +02:00
Rasmus Melchior Jacobsen
e9121cba2c stm32: Fix watchdog timeout computation 2023-05-22 14:22:27 +02:00
goueslati
059ab358a5 stm32/ipcc: uncomment shci init cmd 2023-05-22 11:13:22 +01:00
bors[bot]
ab7d129e15
Merge #1473
1473: Protect default implementations for FirmwareUpdater and BootLoader r=lulf a=rmja

It seems as if the arm compiler can does not care about whether the bootloader symbols are undefined if the default() function is never used. The x64 compiler does care however, so this change ensures that we can instantiate the types from tests.

Co-authored-by: Rasmus Melchior Jacobsen <rmja@laesoe.org>
2023-05-22 09:52:56 +00:00
goueslati
12720737e1 stm32/ipcc: fix incorrect example 2023-05-22 10:52:05 +01:00
Rasmus Melchior Jacobsen
18c62aa5b4 Protect default implementations for FirmwareUpdater and BootLoader
It seems as if the arm compiler can does not care about whether the bootloader symbols are undefined if the default() function is never used. The x64 compiler does care however, so this change ensures that we can instantiate the types from tests.
2023-05-22 11:32:39 +02:00
xoviat
d1dfaa1905 stm32/ipcc: fix hil test 2023-05-21 20:18:26 -05:00
xoviat
1f65a4eb6f stm32/ipcc: enable test 2023-05-21 18:40:29 -05:00
xoviat
eb09d7d671 stm32/ipcc: update doc 2023-05-21 18:39:13 -05:00
xoviat
7f702fd6f1 stm32/ipcc: fix warnings 2023-05-20 11:29:53 -05:00
xoviat
383bef1711 stm32/ipcc: naming 2023-05-20 10:24:26 -05:00
xoviat
5e86188c25 stm32/ipcc: cleanup naming 2023-05-20 10:24:13 -05:00
xoviat
661b1f3373 stm32/ipcc: remove constrain 2023-05-20 10:23:57 -05:00
bors[bot]
d55b9bc6e2
Merge #1440
1440: rp: Pin fix, improve fifo handling r=Dirbaio a=CBJamo

Went to actually use this code and found two issues:
* The config for the pins got dropped in the shuffle. 
* I found that when using more than one ws2812, only the first would get data. I'm pretty sure the data was shifted out before the task got back to push the next word. So now the fifo gets filled, then we wait.

Co-authored-by: Caleb Jamison <caleb@cbjamo.com>
Co-authored-by: Caleb Jamison <caleb@hellbender.com>
2023-05-19 20:53:26 +00:00
Caleb Jamison
1ebb742fbf Switch to DMA, use new clocks, don't take ownership of pio common 2023-05-19 16:48:47 -04:00
Caleb Jamison
1be6e53316 Pin fix, improve fifo handling 2023-05-19 15:06:36 -04:00
Dario Nieuwenhuis
d737e3dcbb
Merge pull request #1469 from embassy-rs/update-nightly
Update Rust nightly.
2023-05-19 19:01:31 +02:00
Dario Nieuwenhuis
a1cbdd8d29 nrf/uarte: fix deref warning, fix errata not being applied on nrf53. 2023-05-19 18:25:34 +02:00
Dario Nieuwenhuis
8b9306ed5c stm32/sdmmc: fix "drop with a value that implements Copy does nothing" warning. 2023-05-19 18:00:33 +02:00
Dario Nieuwenhuis
df56f901de time: fix unused mut. 2023-05-19 17:38:57 +02:00
Dario Nieuwenhuis
9f7392474b Update Rust nightly. 2023-05-19 17:12:39 +02:00
bors[bot]
9dff6b9d81
Merge #1419
1419: stm32/pwm: improve dead-time api r=Dirbaio a=xoviat



Co-authored-by: xoviat <xoviat@users.noreply.github.com>
2023-05-19 14:41:44 +00:00
goueslati
d736c9205c updated test case 2023-05-19 15:40:09 +01:00
bors[bot]
464018e12d
Merge #1463
1463: Allow for an optional user-defined entry macro when targeting RISC-V r=Dirbaio a=jessebraham

In [esp-hal](https://github.com/esp-rs/esp-hal) we use our own custom runtime crate, [esp-riscv-rt](https://github.com/esp-rs/esp-riscv-rt). This PR adds the ability to optionally specify an entry macro when using `embassy_executor::main`. The following forms are both accepted:

```rust
#[embassy_executor::main] // uses `riscv_rt::entry` by default
async fn main() {}

#[embassy_executor::main(entry = "esp_riscv_rt::entry")]
async fn main() {}
```

I attempted to get this working without needing to quote the entry macro argument, however I was not able to get this working. Based off some reading I did this may not be possible, however I am rather inexperienced with proc macros. Happy to change this if anybody has any insight.

Co-authored-by: Jesse Braham <jesse@beta7.io>
2023-05-19 14:14:08 +00:00
Dario Nieuwenhuis
55e4a89819
Merge pull request #1467 from embassy-rs/stm32-usb-no-time
stm32/usb: do not require embassy-time.
2023-05-19 16:10:41 +02:00
Dario Nieuwenhuis
a521a9b5ce stm32: test more feature combinations in ci. 2023-05-19 15:38:45 +02:00
Dario Nieuwenhuis
f43d57846e stm32/usb: do not require embassy-time.
Fixes #1466
2023-05-19 15:20:37 +02:00
bors[bot]
4b303949bf
Merge #1465
1465: rp: continue clock rework r=Dirbaio a=pennae

vastly reduce the code size of initial clock config (over 700 bytes saved!), at the cost of about 48 bytes of ram used to store the frequencies of all clocks in the system. also stop exporting unstable pac items for clock config, fix a few settings that were out of spec, and add missing features (most notably gpin source information).

Co-authored-by: pennae <github@quasiparticle.net>
2023-05-17 22:20:44 +00:00
pennae
fc746a88b5 rp/clocks: comment out all gpin handling for now
gpin clock sources aren't going to be very useful during cold boot and
thus require runtime clock reconfig. once we get there we can use this
for reference. or maybe we can't, only time will tell.
2023-05-17 23:25:49 +02:00
pennae
1e029a9e66 rp/clocks: remove superfluous clock actions
the rtc doesn't have to be disabled since it's always clocked from ref,
and the watchdog doesn't need to be configured twice.
2023-05-17 21:36:19 +02:00
pennae
053d5629ba rp/clocks: require GpinPin for gpin config
we'll take static ownership of an entire pin (not just a limited
reference), otherwise we cannot at all guarantee that the pin will not
be reused for something else while still in use. in theory we could
limit the liftime of this use, but that would require attaching
lifetimes to ClockConfig (and subsequently the main config), passing
those through init(), and returning an object that undoes the gpin
configuration on drop. that's a lot unnecessary support code while we
don't have runtime clock reconfig.
2023-05-17 21:36:19 +02:00
pennae
1b3d9a0aef rp/clocks: compactify pll setup
we don't need to preserve existing bits of the pll pwr register, so
let's only write and save a few instructions.
2023-05-17 21:36:19 +02:00
pennae
f79d8cb2d3 rp/clocks: store clock frequencies in ram
don't recalculate clock frequencies every time they are asked for. while
this is not very often in practice it does consume a bunch of flash
space that cannot be optimized away, and was pulled in unconditionally
previously. while we technically only need the configured rosc, xosc and
gpin frequencies it is easier to store all frequencies (and much cheaper
at runtime too).
2023-05-17 21:36:19 +02:00