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@ -35,7 +35,7 @@ For Cortex-M targets, consider making sure that ALL of the following features ar
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* `executor-thread`
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* `executor-thread`
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* `nightly`
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* `nightly`
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For ESP32, consider using the executors and `#[main]` macro provided by your appropriate link:https://crates.io/crates/esp-hal-common[HAL crate].
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For Xtensa ESP32, consider using the executors and `#[main]` macro provided by your appropriate link:https://crates.io/crates/esp-hal-common[HAL crate].
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== Why is my binary so big?
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== Why is my binary so big?
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@ -184,12 +184,10 @@ impl<'d, DFU: NorFlash, STATE: NorFlash> BlockingFirmwareUpdater<'d, DFU, STATE>
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///
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///
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/// Failing to meet alignment and size requirements may result in a panic.
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/// Failing to meet alignment and size requirements may result in a panic.
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pub fn write_firmware(&mut self, offset: usize, data: &[u8]) -> Result<(), FirmwareUpdaterError> {
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pub fn write_firmware(&mut self, offset: usize, data: &[u8]) -> Result<(), FirmwareUpdaterError> {
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//assert!(data.len() >= DFU::ERASE_SIZE);
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assert!(data.len() >= DFU::ERASE_SIZE);
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self.state.verify_booted()?;
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self.state.verify_booted()?;
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if offset == 0 {
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self.dfu.erase(offset as u32, (offset + data.len()) as u32)?;
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self.dfu.erase(0, self.dfu.capacity() as u32)?;
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}
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self.dfu.write(offset as u32, data)?;
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self.dfu.write(offset as u32, data)?;
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@ -161,10 +161,6 @@ pub struct Config {
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/// Set this to true to invert RX pin signal values (V<sub>DD</sub> =0/mark, Gnd = 1/idle).
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/// Set this to true to invert RX pin signal values (V<sub>DD</sub> =0/mark, Gnd = 1/idle).
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#[cfg(any(usart_v3, usart_v4))]
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#[cfg(any(usart_v3, usart_v4))]
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pub invert_rx: bool,
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pub invert_rx: bool,
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/// enable single wire half duplex communication. Only the tx pin is used. Needs an external
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/// pull up
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pub half_duplex: bool,
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}
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}
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impl Default for Config {
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impl Default for Config {
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@ -184,7 +180,6 @@ impl Default for Config {
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invert_tx: false,
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invert_tx: false,
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#[cfg(any(usart_v3, usart_v4))]
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#[cfg(any(usart_v3, usart_v4))]
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invert_rx: false,
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invert_rx: false,
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half_duplex: false,
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}
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}
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}
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}
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}
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}
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@ -816,27 +811,19 @@ impl<'d, T: BasicInstance, TxDma, RxDma> Uart<'d, T, TxDma, RxDma> {
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let r = T::regs();
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let r = T::regs();
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// Some chips do not have swap_rx_tx bit
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// Some chips do not have swap_rx_tx bit
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if config.half_duplex {
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cfg_if::cfg_if! {
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if config.swap_rx_tx {
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if #[cfg(any(usart_v3, usart_v4))] {
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rx.set_as_af(rx.af_num(), AFType::OutputOpenDrain);
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if config.swap_rx_tx {
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} else {
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let (rx, tx) = (tx, rx);
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tx.set_as_af(tx.af_num(), AFType::OutputOpenDrain);
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rx.set_as_af(rx.af_num(), AFType::Input);
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}
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tx.set_as_af(tx.af_num(), AFType::OutputPushPull);
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} else {
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cfg_if::cfg_if! {
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if #[cfg(any(usart_v3, usart_v4))] {
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if config.swap_rx_tx {
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let (rx, tx) = (tx, rx);
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rx.set_as_af(rx.af_num(), AFType::Input);
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tx.set_as_af(tx.af_num(), AFType::OutputPushPull);
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} else {
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rx.set_as_af(rx.af_num(), AFType::Input);
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tx.set_as_af(tx.af_num(), AFType::OutputPushPull);
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}
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} else {
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} else {
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rx.set_as_af(rx.af_num(), AFType::Input);
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rx.set_as_af(rx.af_num(), AFType::Input);
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tx.set_as_af(tx.af_num(), AFType::OutputPushPull);
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tx.set_as_af(tx.af_num(), AFType::OutputPushPull);
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}
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}
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} else {
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rx.set_as_af(rx.af_num(), AFType::Input);
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tx.set_as_af(tx.af_num(), AFType::OutputPushPull);
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}
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}
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}
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}
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@ -1052,7 +1039,6 @@ fn configure(
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#[cfg(not(usart_v1))]
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#[cfg(not(usart_v1))]
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r.cr3().modify(|w| {
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r.cr3().modify(|w| {
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w.set_onebit(config.assume_noise_free);
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w.set_onebit(config.assume_noise_free);
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w.set_hdsel(config.half_duplex);
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});
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});
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r.cr1().write(|w| {
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r.cr1().write(|w| {
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@ -73,8 +73,6 @@ impl<'d, STATE: NorFlash, RST: Reset> Handler for Control<'d, STATE, RST> {
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self.detach_start = Some(Instant::now());
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self.detach_start = Some(Instant::now());
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self.timeout = Some(Duration::from_millis(req.value as u64));
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self.timeout = Some(Duration::from_millis(req.value as u64));
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self.state = State::AppDetach;
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self.state = State::AppDetach;
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// hack to make it work together with usb serial logging
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self.reset();
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Some(OutResponse::Accepted)
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Some(OutResponse::Accepted)
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}
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}
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_ => None,
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_ => None,
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