executor: add faster ARM-specific impl.

Does a wake+poll in 79 cycles in nrf52840.

embassy-executor/CHANGELOG.md

@@ -5,6 +5,11 @@ All notable changes to this project will be documented in this file.
 The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/),
 and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0.html).
 
+## 0.3.3 - 2023-11-15
+
+- Add `main` macro reexport for Xtensa arch.
+- Remove use of `atomic-polyfill`. The executor now has multiple implementations of its internal data structures for cases where the target supports atomics or doesn't.
+
 ## 0.3.2 - 2023-11-06
 
 - Use `atomic-polyfill` for `riscv32`

embassy-executor/Cargo.toml

@@ -1,6 +1,6 @@
 [package]
 name = "embassy-executor"
-version = "0.3.2"
+version = "0.3.3"
 edition = "2021"
 license = "MIT OR Apache-2.0"
 description = "async/await executor designed for embedded usage"
@@ -34,7 +34,7 @@ _arch = [] # some arch was picked
 arch-std = ["_arch", "critical-section/std"]
 arch-cortex-m = ["_arch", "dep:cortex-m"]
 arch-xtensa = ["_arch"]
-arch-riscv32 = ["_arch"]
+arch-riscv32 = ["_arch", "dep:portable-atomic"]
 arch-wasm = ["_arch", "dep:wasm-bindgen", "dep:js-sys"]
 
 # Enable the thread-mode executor (using WFE/SEV in Cortex-M, WFI in other embedded archs)
@@ -59,9 +59,12 @@ rtos-trace = { version = "0.1.2", optional = true }
 
 embassy-macros = { version = "0.2.1", path = "../embassy-macros" }
 embassy-time = { version = "0.1.5", path = "../embassy-time", optional = true}
-atomic-polyfill = "1.0.1"
 critical-section = "1.1"
 
+# needed for riscv
+# remove when https://github.com/rust-lang/rust/pull/114499 is merged
+portable-atomic = { version = "1.5", optional = true }
+
 # arch-cortex-m dependencies
 cortex-m = { version = "0.7.6", optional = true }
 

embassy-executor/src/arch/cortex_m.rs

@@ -115,12 +115,12 @@ mod thread {
 pub use interrupt::*;
 #[cfg(feature = "executor-interrupt")]
 mod interrupt {
-    use core::cell::UnsafeCell;
+    use core::cell::{Cell, UnsafeCell};
     use core::mem::MaybeUninit;
 
-    use atomic_polyfill::{AtomicBool, Ordering};
     use cortex_m::interrupt::InterruptNumber;
     use cortex_m::peripheral::NVIC;
+    use critical_section::Mutex;
 
     use crate::raw;
 
@@ -146,7 +146,7 @@ mod interrupt {
     /// It is somewhat more complex to use, it's recommended to use the thread-mode
     /// [`Executor`] instead, if it works for your use case.
     pub struct InterruptExecutor {
-        started: AtomicBool,
+        started: Mutex<Cell<bool>>,
         executor: UnsafeCell<MaybeUninit<raw::Executor>>,
     }
 
@@ -158,7 +158,7 @@ mod interrupt {
         #[inline]
         pub const fn new() -> Self {
             Self {
-                started: AtomicBool::new(false),
+                started: Mutex::new(Cell::new(false)),
                 executor: UnsafeCell::new(MaybeUninit::uninit()),
             }
         }
@@ -167,7 +167,8 @@ mod interrupt {
         ///
         /// # Safety
         ///
-        /// You MUST call this from the interrupt handler, and from nowhere else.
+        /// - You MUST call this from the interrupt handler, and from nowhere else.
+        /// - You must not call this before calling `start()`.
         pub unsafe fn on_interrupt(&'static self) {
             let executor = unsafe { (&*self.executor.get()).assume_init_ref() };
             executor.poll();
@@ -196,11 +197,7 @@ mod interrupt {
         /// do it after.
         ///
         pub fn start(&'static self, irq: impl InterruptNumber) -> crate::SendSpawner {
-            if self
+            if critical_section::with(|cs| self.started.borrow(cs).replace(true)) {
-                .started
-                .compare_exchange(false, true, Ordering::Acquire, Ordering::Relaxed)
-                .is_err()
-            {
                 panic!("InterruptExecutor::start() called multiple times on the same executor.");
             }
 
@@ -222,10 +219,10 @@ mod interrupt {
         /// This returns a [`SendSpawner`] you can use to spawn tasks on this
         /// executor.
         ///
-        /// This MUST only be called on an executor that has already been spawned.
+        /// This MUST only be called on an executor that has already been started.
         /// The function will panic otherwise.
         pub fn spawner(&'static self) -> crate::SendSpawner {
-            if !self.started.load(Ordering::Acquire) {
+            if !critical_section::with(|cs| self.started.borrow(cs).get()) {
                 panic!("InterruptExecutor::spawner() called on uninitialized executor.");
             }
             let executor = unsafe { (&*self.executor.get()).assume_init_ref() };

embassy-executor/src/arch/riscv32.rs

@@ -7,9 +7,9 @@ pub use thread::*;
 mod thread {
     use core::marker::PhantomData;
 
-    use atomic_polyfill::{AtomicBool, Ordering};
     #[cfg(feature = "nightly")]
     pub use embassy_macros::main_riscv as main;
+    use portable_atomic::{AtomicBool, Ordering};
 
     use crate::{raw, Spawner};
 

embassy-executor/src/arch/xtensa.rs

@@ -8,6 +8,9 @@ mod thread {
     use core::marker::PhantomData;
     use core::sync::atomic::{AtomicBool, Ordering};
 
+    #[cfg(feature = "nightly")]
+    pub use embassy_macros::main_riscv as main;
+
     use crate::{raw, Spawner};
 
     /// global atomic used to keep track of whether there is work to do since sev() is not available on Xtensa

embassy-executor/src/raw/mod.rs

@@ -7,7 +7,15 @@
 //! Using this module requires respecting subtle safety contracts. If you can, prefer using the safe
 //! [executor wrappers](crate::Executor) and the [`embassy_executor::task`](embassy_macros::task) macro, which are fully safe.
 
+#[cfg_attr(target_has_atomic = "ptr", path = "run_queue_atomics.rs")]
+#[cfg_attr(not(target_has_atomic = "ptr"), path = "run_queue_critical_section.rs")]
 mod run_queue;
+
+#[cfg_attr(all(cortex_m, target_has_atomic = "8"), path = "state_atomics_arm.rs")]
+#[cfg_attr(all(not(cortex_m), target_has_atomic = "8"), path = "state_atomics.rs")]
+#[cfg_attr(not(target_has_atomic = "8"), path = "state_critical_section.rs")]
+mod state;
+
 #[cfg(feature = "integrated-timers")]
 mod timer_queue;
 pub(crate) mod util;
@@ -21,7 +29,6 @@ use core::pin::Pin;
 use core::ptr::NonNull;
 use core::task::{Context, Poll};
 
-use atomic_polyfill::{AtomicU32, Ordering};
 #[cfg(feature = "integrated-timers")]
 use embassy_time::driver::{self, AlarmHandle};
 #[cfg(feature = "integrated-timers")]
@@ -30,21 +37,14 @@ use embassy_time::Instant;
 use rtos_trace::trace;
 
 use self::run_queue::{RunQueue, RunQueueItem};
+use self::state::State;
 use self::util::{SyncUnsafeCell, UninitCell};
 pub use self::waker::task_from_waker;
 use super::SpawnToken;
 
-/// Task is spawned (has a future)
-pub(crate) const STATE_SPAWNED: u32 = 1 << 0;
-/// Task is in the executor run queue
-pub(crate) const STATE_RUN_QUEUED: u32 = 1 << 1;
-/// Task is in the executor timer queue
-#[cfg(feature = "integrated-timers")]
-pub(crate) const STATE_TIMER_QUEUED: u32 = 1 << 2;
-
 /// Raw task header for use in task pointers.
 pub(crate) struct TaskHeader {
-    pub(crate) state: AtomicU32,
+    pub(crate) state: State,
     pub(crate) run_queue_item: RunQueueItem,
     pub(crate) executor: SyncUnsafeCell<Option<&'static SyncExecutor>>,
     poll_fn: SyncUnsafeCell<Option<unsafe fn(TaskRef)>>,
@@ -116,7 +116,7 @@ impl<F: Future + 'static> TaskStorage<F> {
     pub const fn new() -> Self {
         Self {
             raw: TaskHeader {
-                state: AtomicU32::new(0),
+                state: State::new(),
                 run_queue_item: RunQueueItem::new(),
                 executor: SyncUnsafeCell::new(None),
                 // Note: this is lazily initialized so that a static `TaskStorage` will go in `.bss`
@@ -161,7 +161,7 @@ impl<F: Future + 'static> TaskStorage<F> {
         match future.poll(&mut cx) {
             Poll::Ready(_) => {
                 this.future.drop_in_place();
-                this.raw.state.fetch_and(!STATE_SPAWNED, Ordering::AcqRel);
+                this.raw.state.despawn();
 
                 #[cfg(feature = "integrated-timers")]
                 this.raw.expires_at.set(Instant::MAX);
@@ -193,11 +193,7 @@ impl<F: Future + 'static> AvailableTask<F> {
     ///
     /// This function returns `None` if a task has already been spawned and has not finished running.
     pub fn claim(task: &'static TaskStorage<F>) -> Option<Self> {
-        task.raw
+        task.raw.state.spawn().then(|| Self { task })
-            .state
-            .compare_exchange(0, STATE_SPAWNED | STATE_RUN_QUEUED, Ordering::AcqRel, Ordering::Acquire)
-            .ok()
-            .map(|_| Self { task })
     }
 
     fn initialize_impl<S>(self, future: impl FnOnce() -> F) -> SpawnToken<S> {
@@ -394,8 +390,7 @@ impl SyncExecutor {
                 #[cfg(feature = "integrated-timers")]
                 task.expires_at.set(Instant::MAX);
 
-                let state = task.state.fetch_and(!STATE_RUN_QUEUED, Ordering::AcqRel);
+                if !task.state.run_dequeue() {
-                if state & STATE_SPAWNED == 0 {
                     // If task is not running, ignore it. This can happen in the following scenario:
                     //   - Task gets dequeued, poll starts
                     //   - While task is being polled, it gets woken. It gets placed in the queue.
@@ -546,18 +541,7 @@ impl Executor {
 /// You can obtain a `TaskRef` from a `Waker` using [`task_from_waker`].
 pub fn wake_task(task: TaskRef) {
     let header = task.header();
-
+    if header.state.run_enqueue() {
-    let res = header.state.fetch_update(Ordering::SeqCst, Ordering::SeqCst, |state| {
-        // If already scheduled, or if not started,
-        if (state & STATE_RUN_QUEUED != 0) || (state & STATE_SPAWNED == 0) {
-            None
-        } else {
-            // Mark it as scheduled
-            Some(state | STATE_RUN_QUEUED)
-        }
-    });
-
-    if res.is_ok() {
         // We have just marked the task as scheduled, so enqueue it.
         unsafe {
             let executor = header.executor.get().unwrap_unchecked();
@@ -571,18 +555,7 @@ pub fn wake_task(task: TaskRef) {
 /// You can obtain a `TaskRef` from a `Waker` using [`task_from_waker`].
 pub fn wake_task_no_pend(task: TaskRef) {
     let header = task.header();
-
+    if header.state.run_enqueue() {
-    let res = header.state.fetch_update(Ordering::SeqCst, Ordering::SeqCst, |state| {
-        // If already scheduled, or if not started,
-        if (state & STATE_RUN_QUEUED != 0) || (state & STATE_SPAWNED == 0) {
-            None
-        } else {
-            // Mark it as scheduled
-            Some(state | STATE_RUN_QUEUED)
-        }
-    });
-
-    if res.is_ok() {
         // We have just marked the task as scheduled, so enqueue it.
         unsafe {
             let executor = header.executor.get().unwrap_unchecked();

embassy-executor/src/raw/run_queue_atomics.rs

@@ -1,7 +1,6 @@
 use core::ptr;
 use core::ptr::NonNull;
-
+use core::sync::atomic::{AtomicPtr, Ordering};
-use atomic_polyfill::{AtomicPtr, Ordering};
 
 use super::{TaskHeader, TaskRef};
 use crate::raw::util::SyncUnsafeCell;

embassy-executor/src/raw/run_queue_critical_section.rs

@@ -0,0 +1,75 @@
+use core::cell::Cell;
+
+use critical_section::{CriticalSection, Mutex};
+
+use super::TaskRef;
+
+pub(crate) struct RunQueueItem {
+    next: Mutex<Cell<Option<TaskRef>>>,
+}
+
+impl RunQueueItem {
+    pub const fn new() -> Self {
+        Self {
+            next: Mutex::new(Cell::new(None)),
+        }
+    }
+}
+
+/// Atomic task queue using a very, very simple lock-free linked-list queue:
+///
+/// To enqueue a task, task.next is set to the old head, and head is atomically set to task.
+///
+/// Dequeuing is done in batches: the queue is emptied by atomically replacing head with
+/// null. Then the batch is iterated following the next pointers until null is reached.
+///
+/// Note that batches will be iterated in the reverse order as they were enqueued. This is OK
+/// for our purposes: it can't create fairness problems since the next batch won't run until the
+/// current batch is completely processed, so even if a task enqueues itself instantly (for example
+/// by waking its own waker) can't prevent other tasks from running.
+pub(crate) struct RunQueue {
+    head: Mutex<Cell<Option<TaskRef>>>,
+}
+
+impl RunQueue {
+    pub const fn new() -> Self {
+        Self {
+            head: Mutex::new(Cell::new(None)),
+        }
+    }
+
+    /// Enqueues an item. Returns true if the queue was empty.
+    ///
+    /// # Safety
+    ///
+    /// `item` must NOT be already enqueued in any queue.
+    #[inline(always)]
+    pub(crate) unsafe fn enqueue(&self, task: TaskRef) -> bool {
+        critical_section::with(|cs| {
+            let prev = self.head.borrow(cs).replace(Some(task));
+            task.header().run_queue_item.next.borrow(cs).set(prev);
+
+            prev.is_none()
+        })
+    }
+
+    /// Empty the queue, then call `on_task` for each task that was in the queue.
+    /// NOTE: It is OK for `on_task` to enqueue more tasks. In this case they're left in the queue
+    /// and will be processed by the *next* call to `dequeue_all`, *not* the current one.
+    pub(crate) fn dequeue_all(&self, on_task: impl Fn(TaskRef)) {
+        // Atomically empty the queue.
+        let mut next = critical_section::with(|cs| self.head.borrow(cs).take());
+
+        // Iterate the linked list of tasks that were previously in the queue.
+        while let Some(task) = next {
+            // If the task re-enqueues itself, the `next` pointer will get overwritten.
+            // Therefore, first read the next pointer, and only then process the task.
+
+            // safety: we know if the task is enqueued, no one else will touch the `next` pointer.
+            let cs = unsafe { CriticalSection::new() };
+            next = task.header().run_queue_item.next.borrow(cs).get();
+
+            on_task(task);
+        }
+    }
+}

embassy-executor/src/raw/state_atomics.rs

@@ -0,0 +1,73 @@
+use core::sync::atomic::{AtomicU32, Ordering};
+
+/// Task is spawned (has a future)
+pub(crate) const STATE_SPAWNED: u32 = 1 << 0;
+/// Task is in the executor run queue
+pub(crate) const STATE_RUN_QUEUED: u32 = 1 << 1;
+/// Task is in the executor timer queue
+#[cfg(feature = "integrated-timers")]
+pub(crate) const STATE_TIMER_QUEUED: u32 = 1 << 2;
+
+pub(crate) struct State {
+    state: AtomicU32,
+}
+
+impl State {
+    pub const fn new() -> State {
+        Self {
+            state: AtomicU32::new(0),
+        }
+    }
+
+    /// If task is idle, mark it as spawned + run_queued and return true.
+    #[inline(always)]
+    pub fn spawn(&self) -> bool {
+        self.state
+            .compare_exchange(0, STATE_SPAWNED | STATE_RUN_QUEUED, Ordering::AcqRel, Ordering::Acquire)
+            .is_ok()
+    }
+
+    /// Unmark the task as spawned.
+    #[inline(always)]
+    pub fn despawn(&self) {
+        self.state.fetch_and(!STATE_SPAWNED, Ordering::AcqRel);
+    }
+
+    /// Mark the task as run-queued if it's spawned and isn't already run-queued. Return true on success.
+    #[inline(always)]
+    pub fn run_enqueue(&self) -> bool {
+        self.state
+            .fetch_update(Ordering::SeqCst, Ordering::SeqCst, |state| {
+                // If already scheduled, or if not started,
+                if (state & STATE_RUN_QUEUED != 0) || (state & STATE_SPAWNED == 0) {
+                    None
+                } else {
+                    // Mark it as scheduled
+                    Some(state | STATE_RUN_QUEUED)
+                }
+            })
+            .is_ok()
+    }
+
+    /// Unmark the task as run-queued. Return whether the task is spawned.
+    #[inline(always)]
+    pub fn run_dequeue(&self) -> bool {
+        let state = self.state.fetch_and(!STATE_RUN_QUEUED, Ordering::AcqRel);
+        state & STATE_SPAWNED != 0
+    }
+
+    /// Mark the task as timer-queued. Return whether it was newly queued (i.e. not queued before)
+    #[cfg(feature = "integrated-timers")]
+    #[inline(always)]
+    pub fn timer_enqueue(&self) -> bool {
+        let old_state = self.state.fetch_or(STATE_TIMER_QUEUED, Ordering::AcqRel);
+        old_state & STATE_TIMER_QUEUED == 0
+    }
+
+    /// Unmark the task as timer-queued.
+    #[cfg(feature = "integrated-timers")]
+    #[inline(always)]
+    pub fn timer_dequeue(&self) {
+        self.state.fetch_and(!STATE_TIMER_QUEUED, Ordering::AcqRel);
+    }
+}

embassy-executor/src/raw/state_atomics_arm.rs

@@ -0,0 +1,103 @@
+use core::arch::asm;
+use core::sync::atomic::{compiler_fence, AtomicBool, AtomicU32, Ordering};
+
+// Must be kept in sync with the layout of `State`!
+pub(crate) const STATE_SPAWNED: u32 = 1 << 0;
+pub(crate) const STATE_RUN_QUEUED: u32 = 1 << 8;
+
+#[repr(C, align(4))]
+pub(crate) struct State {
+    /// Task is spawned (has a future)
+    spawned: AtomicBool,
+    /// Task is in the executor run queue
+    run_queued: AtomicBool,
+    /// Task is in the executor timer queue
+    timer_queued: AtomicBool,
+    pad: AtomicBool,
+}
+
+impl State {
+    pub const fn new() -> State {
+        Self {
+            spawned: AtomicBool::new(false),
+            run_queued: AtomicBool::new(false),
+            timer_queued: AtomicBool::new(false),
+            pad: AtomicBool::new(false),
+        }
+    }
+
+    fn as_u32(&self) -> &AtomicU32 {
+        unsafe { &*(self as *const _ as *const AtomicU32) }
+    }
+
+    /// If task is idle, mark it as spawned + run_queued and return true.
+    #[inline(always)]
+    pub fn spawn(&self) -> bool {
+        compiler_fence(Ordering::Release);
+        let r = self
+            .as_u32()
+            .compare_exchange(
+                0,
+                STATE_SPAWNED | STATE_RUN_QUEUED,
+                Ordering::Relaxed,
+                Ordering::Relaxed,
+            )
+            .is_ok();
+        compiler_fence(Ordering::Acquire);
+        r
+    }
+
+    /// Unmark the task as spawned.
+    #[inline(always)]
+    pub fn despawn(&self) {
+        compiler_fence(Ordering::Release);
+        self.spawned.store(false, Ordering::Relaxed);
+    }
+
+    /// Mark the task as run-queued if it's spawned and isn't already run-queued. Return true on success.
+    #[inline(always)]
+    pub fn run_enqueue(&self) -> bool {
+        unsafe {
+            loop {
+                let state: u32;
+                asm!("ldrex {}, [{}]", out(reg) state, in(reg) self, options(nostack));
+
+                if (state & STATE_RUN_QUEUED != 0) || (state & STATE_SPAWNED == 0) {
+                    asm!("clrex", options(nomem, nostack));
+                    return false;
+                }
+
+                let outcome: usize;
+                let new_state = state | STATE_RUN_QUEUED;
+                asm!("strex {}, {}, [{}]", out(reg) outcome, in(reg) new_state, in(reg) self, options(nostack));
+                if outcome == 0 {
+                    return true;
+                }
+            }
+        }
+    }
+
+    /// Unmark the task as run-queued. Return whether the task is spawned.
+    #[inline(always)]
+    pub fn run_dequeue(&self) -> bool {
+        compiler_fence(Ordering::Release);
+
+        let r = self.spawned.load(Ordering::Relaxed);
+        self.run_queued.store(false, Ordering::Relaxed);
+        r
+    }
+
+    /// Mark the task as timer-queued. Return whether it was newly queued (i.e. not queued before)
+    #[cfg(feature = "integrated-timers")]
+    #[inline(always)]
+    pub fn timer_enqueue(&self) -> bool {
+        !self.timer_queued.swap(true, Ordering::Relaxed)
+    }
+
+    /// Unmark the task as timer-queued.
+    #[cfg(feature = "integrated-timers")]
+    #[inline(always)]
+    pub fn timer_dequeue(&self) {
+        self.timer_queued.store(false, Ordering::Relaxed);
+    }
+}

embassy-executor/src/raw/state_critical_section.rs

@@ -0,0 +1,93 @@
+use core::cell::Cell;
+
+use critical_section::Mutex;
+
+/// Task is spawned (has a future)
+pub(crate) const STATE_SPAWNED: u32 = 1 << 0;
+/// Task is in the executor run queue
+pub(crate) const STATE_RUN_QUEUED: u32 = 1 << 1;
+/// Task is in the executor timer queue
+#[cfg(feature = "integrated-timers")]
+pub(crate) const STATE_TIMER_QUEUED: u32 = 1 << 2;
+
+pub(crate) struct State {
+    state: Mutex<Cell<u32>>,
+}
+
+impl State {
+    pub const fn new() -> State {
+        Self {
+            state: Mutex::new(Cell::new(0)),
+        }
+    }
+
+    fn update<R>(&self, f: impl FnOnce(&mut u32) -> R) -> R {
+        critical_section::with(|cs| {
+            let s = self.state.borrow(cs);
+            let mut val = s.get();
+            let r = f(&mut val);
+            s.set(val);
+            r
+        })
+    }
+
+    /// If task is idle, mark it as spawned + run_queued and return true.
+    #[inline(always)]
+    pub fn spawn(&self) -> bool {
+        self.update(|s| {
+            if *s == 0 {
+                *s = STATE_SPAWNED | STATE_RUN_QUEUED;
+                true
+            } else {
+                false
+            }
+        })
+    }
+
+    /// Unmark the task as spawned.
+    #[inline(always)]
+    pub fn despawn(&self) {
+        self.update(|s| *s &= !STATE_SPAWNED);
+    }
+
+    /// Mark the task as run-queued if it's spawned and isn't already run-queued. Return true on success.
+    #[inline(always)]
+    pub fn run_enqueue(&self) -> bool {
+        self.update(|s| {
+            if (*s & STATE_RUN_QUEUED != 0) || (*s & STATE_SPAWNED == 0) {
+                false
+            } else {
+                *s |= STATE_RUN_QUEUED;
+                true
+            }
+        })
+    }
+
+    /// Unmark the task as run-queued. Return whether the task is spawned.
+    #[inline(always)]
+    pub fn run_dequeue(&self) -> bool {
+        self.update(|s| {
+            let ok = *s & STATE_SPAWNED != 0;
+            *s &= !STATE_RUN_QUEUED;
+            ok
+        })
+    }
+
+    /// Mark the task as timer-queued. Return whether it was newly queued (i.e. not queued before)
+    #[cfg(feature = "integrated-timers")]
+    #[inline(always)]
+    pub fn timer_enqueue(&self) -> bool {
+        self.update(|s| {
+            let ok = *s & STATE_TIMER_QUEUED == 0;
+            *s |= STATE_TIMER_QUEUED;
+            ok
+        })
+    }
+
+    /// Unmark the task as timer-queued.
+    #[cfg(feature = "integrated-timers")]
+    #[inline(always)]
+    pub fn timer_dequeue(&self) {
+        self.update(|s| *s &= !STATE_TIMER_QUEUED);
+    }
+}

embassy-executor/src/raw/timer_queue.rs

@@ -1,9 +1,8 @@
 use core::cmp::min;
 
-use atomic_polyfill::Ordering;
 use embassy_time::Instant;
 
-use super::{TaskRef, STATE_TIMER_QUEUED};
+use super::TaskRef;
 use crate::raw::util::SyncUnsafeCell;
 
 pub(crate) struct TimerQueueItem {
@@ -32,10 +31,7 @@ impl TimerQueue {
     pub(crate) unsafe fn update(&self, p: TaskRef) {
         let task = p.header();
         if task.expires_at.get() != Instant::MAX {
-            let old_state = task.state.fetch_or(STATE_TIMER_QUEUED, Ordering::AcqRel);
+            if task.state.timer_enqueue() {
-            let is_new = old_state & STATE_TIMER_QUEUED == 0;
-
-            if is_new {
                 task.timer_queue_item.next.set(self.head.get());
                 self.head.set(Some(p));
             }
@@ -75,7 +71,7 @@ impl TimerQueue {
             } else {
                 // Remove it
                 prev.set(task.timer_queue_item.next.get());
-                task.state.fetch_and(!STATE_TIMER_QUEUED, Ordering::AcqRel);
+                task.state.timer_dequeue();
             }
         }
     }

embassy-futures/Cargo.toml

@@ -1,6 +1,6 @@
 [package]
 name = "embassy-futures"
-version = "0.1.0"
+version = "0.1.1"
 edition = "2021"
 description = "no-std, no-alloc utilities for working with futures"
 repository = "https://github.com/embassy-rs/embassy"

embassy-net-adin1110/Cargo.toml

@@ -10,7 +10,7 @@ edition = "2021"
 # See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
 
 [dependencies]
-heapless = "0.7.16"
+heapless = "0.8"
 defmt = { version = "0.3", optional = true }
 log = { version = "0.4", default-features = false, optional = true }
 embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-rc.1" }

embassy-net-esp-hosted/Cargo.toml

@@ -15,9 +15,9 @@ embassy-net-driver-channel = { version = "0.2.0", path = "../embassy-net-driver-
 embedded-hal = { version = "1.0.0-rc.1" }
 embedded-hal-async = { version = "=1.0.0-rc.1" }
 
-noproto = { git="https://github.com/embassy-rs/noproto", rev = "c90f3a78d7b5642415e0a07af401320b84d8ab6f", default-features = false, features = ["derive"] }
+noproto = { git="https://github.com/embassy-rs/noproto", rev = "f5e6d1f325b6ad4e344f60452b09576e24671f62", default-features = false, features = ["derive"] }
 #noproto = { version = "0.1", path = "/home/dirbaio/noproto", default-features = false, features = ["derive"] }
-heapless = "0.7.16"
+heapless = "0.8"
 
 [package.metadata.embassy_docs]
 src_base = "https://github.com/embassy-rs/embassy/blob/embassy-net-esp-hosted-v$VERSION/embassy-net-esp-hosted/src/"

embassy-net-esp-hosted/src/control.rs

@@ -97,8 +97,8 @@ impl<'a> Control<'a> {
 
     pub async fn connect(&mut self, ssid: &str, password: &str) -> Result<(), Error> {
         let req = proto::CtrlMsgReqConnectAp {
-            ssid: String::from(ssid),
+            ssid: unwrap!(String::try_from(ssid)),
-            pwd: String::from(password),
+            pwd: unwrap!(String::try_from(password)),
             bssid: String::new(),
             listen_interval: 3,
             is_wpa3_supported: false,

embassy-net/CHANGELOG.md

@@ -8,6 +8,8 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 ## Unreleased
 
 - Avoid never resolving `TcpIo::read` when the output buffer is empty.
+- Update to `smoltcp` git.
+- Forward constants from `smoltcp` in DNS query results so changing DNS result size in `smoltcp` properly propagates.
 
 ## 0.2.1 - 2023-10-31
 

embassy-net/Cargo.toml

@@ -25,7 +25,7 @@ features = ["nightly", "defmt", "tcp", "udp", "dns", "dhcpv4", "proto-ipv6", "me
 default = []
 std = []
 
-defmt = ["dep:defmt", "smoltcp/defmt", "embassy-net-driver/defmt"]
+defmt = ["dep:defmt", "smoltcp/defmt", "embassy-net-driver/defmt", "heapless/defmt-03"]
 
 nightly = ["dep:embedded-io-async", "dep:embedded-nal-async"]
 
@@ -46,7 +46,7 @@ igmp = ["smoltcp/proto-igmp"]
 defmt = { version = "0.3", optional = true }
 log = { version = "0.4.14", optional = true }
 
-smoltcp = { version = "0.10.0", default-features = false, features = [
+smoltcp = { git = "https://github.com/smoltcp-rs/smoltcp.git", rev = "b57e2f9e70e82a13f31d5ea17e55232c11cc2b2d", default-features = false, features = [
   "socket",
   "async",
 ] }
@@ -57,10 +57,10 @@ embassy-sync = { version = "0.4.0", path = "../embassy-sync" }
 embedded-io-async = { version = "0.6.0", optional = true }
 
 managed = { version = "0.8.0", default-features = false, features = [ "map" ] }
-heapless = { version = "0.7.5", default-features = false }
+heapless = { version = "0.8", default-features = false }
 as-slice = "0.2.1"
 generic-array = { version = "0.14.4", default-features = false }
 stable_deref_trait = { version = "1.2.0", default-features = false }
 futures = { version = "0.3.17", default-features = false, features = [ "async-await" ] }
 atomic-pool = "1.0"
-embedded-nal-async = { version = "0.6.0", optional = true }
+embedded-nal-async = { version = "0.7", optional = true }

embassy-net/src/dns.rs

@@ -63,7 +63,11 @@ where
     }
 
     /// Make a query for a given name and return the corresponding IP addresses.
-    pub async fn query(&self, name: &str, qtype: DnsQueryType) -> Result<Vec<IpAddress, 1>, Error> {
+    pub async fn query(
+        &self,
+        name: &str,
+        qtype: DnsQueryType,
+    ) -> Result<Vec<IpAddress, { smoltcp::config::DNS_MAX_RESULT_COUNT }>, Error> {
         self.stack.dns_query(name, qtype).await
     }
 }
@@ -101,7 +105,8 @@ where
     async fn get_host_by_address(
         &self,
         _addr: embedded_nal_async::IpAddr,
-    ) -> Result<heapless::String<256>, Self::Error> {
+        _result: &mut [u8],
+    ) -> Result<usize, Self::Error> {
         todo!()
     }
 }

embassy-net/src/lib.rs

@@ -494,7 +494,11 @@ impl<D: Driver> Stack<D> {
 
     /// Make a query for a given name and return the corresponding IP addresses.
     #[cfg(feature = "dns")]
-    pub async fn dns_query(&self, name: &str, qtype: dns::DnsQueryType) -> Result<Vec<IpAddress, 1>, dns::Error> {
+    pub async fn dns_query(
+        &self,
+        name: &str,
+        qtype: dns::DnsQueryType,
+    ) -> Result<Vec<IpAddress, { smoltcp::config::DNS_MAX_RESULT_COUNT }>, dns::Error> {
         // For A and AAAA queries we try detect whether `name` is just an IP address
         match qtype {
             #[cfg(feature = "proto-ipv4")]

embassy-net/src/tcp.rs

@@ -618,10 +618,7 @@ pub mod client {
         async fn connect<'a>(
             &'a self,
             remote: embedded_nal_async::SocketAddr,
-        ) -> Result<Self::Connection<'a>, Self::Error>
+        ) -> Result<Self::Connection<'a>, Self::Error> {
-        where
-            Self: 'a,
-        {
             let addr: crate::IpAddress = match remote.ip() {
                 #[cfg(feature = "proto-ipv4")]
                 IpAddr::V4(addr) => crate::IpAddress::Ipv4(crate::Ipv4Address::from_bytes(&addr.octets())),

embassy-nrf/src/buffered_uarte.rs

@@ -12,7 +12,7 @@ use core::cmp::min;
 use core::future::poll_fn;
 use core::marker::PhantomData;
 use core::slice;
-use core::sync::atomic::{compiler_fence, AtomicU8, AtomicUsize, Ordering};
+use core::sync::atomic::{compiler_fence, AtomicBool, AtomicU8, AtomicUsize, Ordering};
 use core::task::Poll;
 
 use embassy_hal_internal::atomic_ring_buffer::RingBuffer;
@@ -41,7 +41,9 @@ mod sealed {
 
         pub rx_waker: AtomicWaker,
         pub rx_buf: RingBuffer,
-        pub rx_bufs: AtomicU8,
+        pub rx_started: AtomicBool,
+        pub rx_started_count: AtomicU8,
+        pub rx_ended_count: AtomicU8,
         pub rx_ppi_ch: AtomicU8,
     }
 }
@@ -65,7 +67,9 @@ impl State {
 
             rx_waker: AtomicWaker::new(),
             rx_buf: RingBuffer::new(),
-            rx_bufs: AtomicU8::new(0),
+            rx_started: AtomicBool::new(false),
+            rx_started_count: AtomicU8::new(0),
+            rx_ended_count: AtomicU8::new(0),
             rx_ppi_ch: AtomicU8::new(0),
         }
     }
@@ -104,28 +108,20 @@ impl<U: UarteInstance> interrupt::typelevel::Handler<U::Interrupt> for Interrupt
             s.rx_waker.wake();
         }
 
-        // If not RXing, start.
+        if r.events_endrx.read().bits() != 0 {
-        if s.rx_bufs.load(Ordering::Relaxed) == 0 {
+            //trace!("  irq_rx: endrx");
-            let (ptr, len) = rx.push_buf();
+            r.events_endrx.reset();
-            if len >= half_len {
-                //trace!("  irq_rx: starting {:?}", half_len);
-                s.rx_bufs.store(1, Ordering::Relaxed);
 
-                // Set up the DMA read
+            let val = s.rx_ended_count.load(Ordering::Relaxed);
-                r.rxd.ptr.write(|w| unsafe { w.ptr().bits(ptr as u32) });
+            s.rx_ended_count.store(val.wrapping_add(1), Ordering::Relaxed);
-                r.rxd.maxcnt.write(|w| unsafe { w.maxcnt().bits(half_len as _) });
-
-                // Start UARTE Receive transaction
-                r.tasks_startrx.write(|w| unsafe { w.bits(1) });
-                rx.push_done(half_len);
-                r.intenset.write(|w| w.rxstarted().set());
-            }
         }
 
-        if r.events_rxstarted.read().bits() != 0 {
+        if r.events_rxstarted.read().bits() != 0 || !s.rx_started.load(Ordering::Relaxed) {
             //trace!("  irq_rx: rxstarted");
             let (ptr, len) = rx.push_buf();
             if len >= half_len {
+                r.events_rxstarted.reset();
+
                 //trace!("  irq_rx: starting second {:?}", half_len);
 
                 // Set up the DMA read
@@ -134,11 +130,50 @@ impl<U: UarteInstance> interrupt::typelevel::Handler<U::Interrupt> for Interrupt
 
                 let chn = s.rx_ppi_ch.load(Ordering::Relaxed);
 
+                // Enable endrx -> startrx PPI channel.
+                // From this point on, if endrx happens, startrx is automatically fired.
                 ppi::regs().chenset.write(|w| unsafe { w.bits(1 << chn) });
 
+                // It is possible that endrx happened BEFORE enabling the PPI. In this case
+                // the PPI channel doesn't trigger, and we'd hang. We have to detect this
+                // and manually start.
+
+                // check again in case endrx has happened between the last check and now.
+                if r.events_endrx.read().bits() != 0 {
+                    //trace!("  irq_rx: endrx");
+                    r.events_endrx.reset();
+
+                    let val = s.rx_ended_count.load(Ordering::Relaxed);
+                    s.rx_ended_count.store(val.wrapping_add(1), Ordering::Relaxed);
+                }
+
+                let rx_ended = s.rx_ended_count.load(Ordering::Relaxed);
+                let rx_started = s.rx_started_count.load(Ordering::Relaxed);
+
+                // If we started the same amount of transfers as ended, the last rxend has
+                // already occured.
+                let rxend_happened = rx_started == rx_ended;
+
+                // Check if the PPI channel is still enabled. The PPI channel disables itself
+                // when it fires, so if it's still enabled it hasn't fired.
+                let ppi_ch_enabled = ppi::regs().chen.read().bits() & (1 << chn) != 0;
+
+                // if rxend happened, and the ppi channel hasn't fired yet, the rxend got missed.
+                // this condition also naturally matches if `!started`, needed to kickstart the DMA.
+                if rxend_happened && ppi_ch_enabled {
+                    //trace!("manually starting.");
+
+                    // disable the ppi ch, it's of no use anymore.
+                    ppi::regs().chenclr.write(|w| unsafe { w.bits(1 << chn) });
+
+                    // manually start
+                    r.tasks_startrx.write(|w| unsafe { w.bits(1) });
+                }
+
                 rx.push_done(half_len);
 
-                r.events_rxstarted.reset();
+                s.rx_started_count.store(rx_started.wrapping_add(1), Ordering::Relaxed);
+                s.rx_started.store(true, Ordering::Relaxed);
             } else {
                 //trace!("  irq_rx: rxstarted no buf");
                 r.intenclr.write(|w| w.rxstarted().clear());
@@ -282,6 +317,8 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
 
         let r = U::regs();
 
+        let hwfc = cts.is_some();
+
         rxd.conf().write(|w| w.input().connect().drive().h0h1());
         r.psel.rxd.write(|w| unsafe { w.bits(rxd.psel_bits()) });
 
@@ -303,7 +340,8 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
         // Initialize state
         let s = U::buffered_state();
         s.tx_count.store(0, Ordering::Relaxed);
-        s.rx_bufs.store(0, Ordering::Relaxed);
+        s.rx_started_count.store(0, Ordering::Relaxed);
+        s.rx_ended_count.store(0, Ordering::Relaxed);
         let len = tx_buffer.len();
         unsafe { s.tx_buf.init(tx_buffer.as_mut_ptr(), len) };
         let len = rx_buffer.len();
@@ -311,7 +349,7 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
 
         // Configure
         r.config.write(|w| {
-            w.hwfc().bit(false);
+            w.hwfc().bit(hwfc);
             w.parity().variant(config.parity);
             w
         });
@@ -333,6 +371,7 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
             w.endtx().set();
             w.rxstarted().set();
             w.error().set();
+            w.endrx().set();
             w
         });
 

embassy-rp/Cargo.toml

@@ -94,5 +94,5 @@ pio = {version= "0.2.1" }
 rp2040-boot2 = "0.3"
 
 [dev-dependencies]
-embassy-executor = { version = "0.3.1", path = "../embassy-executor", features = ["nightly", "arch-std", "executor-thread"] }
+embassy-executor = { version = "0.3.3", path = "../embassy-executor", features = ["nightly", "arch-std", "executor-thread"] }
 static_cell = { version = "2" }

embassy-stm32-wpan/Cargo.toml

@@ -21,7 +21,7 @@ embassy-net-driver = { version = "0.2.0", path = "../embassy-net-driver", option
 
 defmt = { version = "0.3", optional = true }
 cortex-m = "0.7.6"
-heapless = "0.7.16"
+heapless = "0.8"
 aligned = "0.4.1"
 
 bit_field = "0.10.2"

embassy-stm32/Cargo.toml

@@ -18,7 +18,7 @@ flavors = [
     { regex_feature = "stm32f7.*", target = "thumbv7em-none-eabi" },
     { regex_feature = "stm32c0.*", target = "thumbv6m-none-eabi" },
     { regex_feature = "stm32g0.*", target = "thumbv6m-none-eabi" },
-    { regex_feature = "stm32g4.*", target = "thumbv7em-none-eabi" },
+    { regex_feature = "stm32g4.*", target = "thumbv7em-none-eabi", features = ["low-power"] },
     { regex_feature = "stm32h5.*", target = "thumbv8m.main-none-eabihf" },
     { regex_feature = "stm32h7.*", target = "thumbv7em-none-eabi" },
     { regex_feature = "stm32l0.*", target = "thumbv6m-none-eabi", features = ["low-power"] },
@@ -39,7 +39,7 @@ embassy-hal-internal = {version = "0.1.0", path = "../embassy-hal-internal", fea
 embassy-embedded-hal = {version = "0.1.0", path = "../embassy-embedded-hal" }
 embassy-net-driver = { version = "0.2.0", path = "../embassy-net-driver" }
 embassy-usb-driver = {version = "0.1.0", path = "../embassy-usb-driver", optional = true }
-embassy-executor = { version = "0.3.1", path = "../embassy-executor", optional = true }
+embassy-executor = { version = "0.3.3", path = "../embassy-executor", optional = true }
 
 embedded-hal-02 = { package = "embedded-hal", version = "0.2.6", features = ["unproven"] }
 embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-rc.1", optional = true}
@@ -58,7 +58,7 @@ rand_core = "0.6.3"
 sdio-host = "0.5.0"
 embedded-sdmmc = { git = "https://github.com/embassy-rs/embedded-sdmmc-rs", rev = "a4f293d3a6f72158385f79c98634cb8a14d0d2fc", optional = true }
 critical-section = "1.1"
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-1374ed622714ef4702826699ca21cc1f741f4133" }
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-fbb8f77326dd066aa6c0d66b3b46e76a569dda8b" }
 vcell = "0.1.3"
 bxcan = "0.7.0"
 nb = "1.0.0"
@@ -76,7 +76,7 @@ critical-section = { version = "1.1", features = ["std"] }
 [build-dependencies]
 proc-macro2 = "1.0.36"
 quote = "1.0.15"
-stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-1374ed622714ef4702826699ca21cc1f741f4133", default-features = false, features = ["metadata"]}
+stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-fbb8f77326dd066aa6c0d66b3b46e76a569dda8b", default-features = false, features = ["metadata"]}
 
 
 [features]

embassy-stm32/src/dma/gpdma.rs

@@ -299,19 +299,15 @@ impl<'a, C: Channel> Transfer<'a, C> {
 
     pub fn request_stop(&mut self) {
         let ch = self.channel.regs().ch(self.channel.num());
-
+        ch.cr().modify(|w| {
-        // Disable the channel. Keep the IEs enabled so the irqs still fire.
+            w.set_susp(true);
-        ch.cr().write(|w| {
-            w.set_tcie(true);
-            w.set_useie(true);
-            w.set_dteie(true);
-            w.set_suspie(true);
         })
     }
 
     pub fn is_running(&mut self) -> bool {
         let ch = self.channel.regs().ch(self.channel.num());
-        !ch.sr().read().tcf()
+        let sr = ch.sr().read();
+        !sr.tcf() && !sr.suspf()
     }
 
     /// Gets the total remaining transfers for the channel

embassy-stm32/src/rcc/f.rs

@@ -1,9 +1,12 @@
-use crate::pac::pwr::vals::Vos;
+use stm32_metapac::flash::vals::Latency;
+
 pub use crate::pac::rcc::vals::{
-    Hpre as AHBPrescaler, Pllm as PllPreDiv, Plln as PllMul, Pllp, Pllq, Pllr, Pllsrc as PllSource,
+    Hpre as AHBPrescaler, Pllm as PllPreDiv, Plln as PllMul, Pllp as PllPDiv, Pllq as PllQDiv, Pllr as PllRDiv,
-    Ppre as APBPrescaler, Sw as Sysclk,
+    Pllsrc as PllSource, Ppre as APBPrescaler, Sw as Sysclk,
 };
-use crate::pac::{FLASH, PWR, RCC};
+#[cfg(any(stm32f4, stm32f7))]
+use crate::pac::PWR;
+use crate::pac::{FLASH, RCC};
 use crate::rcc::{set_freqs, Clocks};
 use crate::time::Hertz;
 
@@ -49,11 +52,27 @@ pub struct Pll {
     pub mul: PllMul,
 
     /// PLL P division factor. If None, PLL P output is disabled.
-    pub divp: Option<Pllp>,
+    pub divp: Option<PllPDiv>,
     /// PLL Q division factor. If None, PLL Q output is disabled.
-    pub divq: Option<Pllq>,
+    pub divq: Option<PllQDiv>,
     /// PLL R division factor. If None, PLL R output is disabled.
-    pub divr: Option<Pllr>,
+    pub divr: Option<PllRDiv>,
+}
+
+/// Voltage range of the power supply used.
+///
+/// Used to calculate flash waitstates. See
+/// RM0033 - Table 3. Number of wait states according to Cortex®-M3 clock frequency
+#[cfg(stm32f2)]
+pub enum VoltageScale {
+    /// 2.7 to 3.6 V
+    Range0,
+    /// 2.4 to 2.7 V
+    Range1,
+    /// 2.1 to 2.4 V
+    Range2,
+    /// 1.8 to 2.1 V
+    Range3,
 }
 
 /// Configuration of the core clocks
@@ -66,7 +85,7 @@ pub struct Config {
     pub pll_src: PllSource,
 
     pub pll: Option<Pll>,
-    #[cfg(any(all(stm32f4, not(stm32f410)), stm32f7))]
+    #[cfg(any(stm32f2, all(stm32f4, not(stm32f410)), stm32f7))]
     pub plli2s: Option<Pll>,
     #[cfg(any(stm32f446, stm32f427, stm32f437, stm32f4x9, stm32f7))]
     pub pllsai: Option<Pll>,
@@ -76,6 +95,9 @@ pub struct Config {
     pub apb2_pre: APBPrescaler,
 
     pub ls: super::LsConfig,
+
+    #[cfg(stm32f2)]
+    pub voltage: VoltageScale,
 }
 
 impl Default for Config {
@@ -86,7 +108,7 @@ impl Default for Config {
             sys: Sysclk::HSI,
             pll_src: PllSource::HSI,
             pll: None,
-            #[cfg(any(all(stm32f4, not(stm32f410)), stm32f7))]
+            #[cfg(any(stm32f2, all(stm32f4, not(stm32f410)), stm32f7))]
             plli2s: None,
             #[cfg(any(stm32f446, stm32f427, stm32f437, stm32f4x9, stm32f7))]
             pllsai: None,
@@ -96,6 +118,9 @@ impl Default for Config {
             apb2_pre: APBPrescaler::DIV1,
 
             ls: Default::default(),
+
+            #[cfg(stm32f2)]
+            voltage: VoltageScale::Range3,
         }
     }
 }
@@ -103,14 +128,13 @@ impl Default for Config {
 pub(crate) unsafe fn init(config: Config) {
     // set VOS to SCALE1, if use PLL
     // TODO: check real clock speed before set VOS
+    #[cfg(any(stm32f4, stm32f7))]
     if config.pll.is_some() {
-        PWR.cr1().modify(|w| w.set_vos(Vos::SCALE1));
+        PWR.cr1().modify(|w| w.set_vos(crate::pac::pwr::vals::Vos::SCALE1));
     }
 
     // always enable overdrive for now. Make it configurable in the future.
-    #[cfg(not(any(
+    #[cfg(any(stm32f446, stm32f4x9, stm32f427, stm32f437, stm32f7))]
-        stm32f401, stm32f410, stm32f411, stm32f412, stm32f413, stm32f423, stm32f405, stm32f407, stm32f415, stm32f417
-    )))]
     {
         PWR.cr1().modify(|w| w.set_oden(true));
         while !PWR.csr1().read().odrdy() {}
@@ -158,7 +182,7 @@ pub(crate) unsafe fn init(config: Config) {
         source: config.pll_src,
     };
     let pll = init_pll(PllInstance::Pll, config.pll, &pll_input);
-    #[cfg(any(all(stm32f4, not(stm32f410)), stm32f7))]
+    #[cfg(any(stm32f2, all(stm32f4, not(stm32f410)), stm32f7))]
     let _plli2s = init_pll(PllInstance::Plli2s, config.plli2s, &pll_input);
     #[cfg(any(stm32f446, stm32f427, stm32f437, stm32f4x9, stm32f7))]
     let _pllsai = init_pll(PllInstance::Pllsai, config.pllsai, &pll_input);
@@ -182,7 +206,48 @@ pub(crate) unsafe fn init(config: Config) {
 
     let rtc = config.ls.init();
 
-    flash_setup(hclk);
+    #[cfg(stm32f2)]
+    let latency = match (config.voltage, hclk.0) {
+        (VoltageScale::Range3, ..=16_000_000) => Latency::WS0,
+        (VoltageScale::Range3, ..=32_000_000) => Latency::WS1,
+        (VoltageScale::Range3, ..=48_000_000) => Latency::WS2,
+        (VoltageScale::Range3, ..=64_000_000) => Latency::WS3,
+        (VoltageScale::Range3, ..=80_000_000) => Latency::WS4,
+        (VoltageScale::Range3, ..=96_000_000) => Latency::WS5,
+        (VoltageScale::Range3, ..=112_000_000) => Latency::WS6,
+        (VoltageScale::Range3, ..=120_000_000) => Latency::WS7,
+        (VoltageScale::Range2, ..=18_000_000) => Latency::WS0,
+        (VoltageScale::Range2, ..=36_000_000) => Latency::WS1,
+        (VoltageScale::Range2, ..=54_000_000) => Latency::WS2,
+        (VoltageScale::Range2, ..=72_000_000) => Latency::WS3,
+        (VoltageScale::Range2, ..=90_000_000) => Latency::WS4,
+        (VoltageScale::Range2, ..=108_000_000) => Latency::WS5,
+        (VoltageScale::Range2, ..=120_000_000) => Latency::WS6,
+        (VoltageScale::Range1, ..=24_000_000) => Latency::WS0,
+        (VoltageScale::Range1, ..=48_000_000) => Latency::WS1,
+        (VoltageScale::Range1, ..=72_000_000) => Latency::WS2,
+        (VoltageScale::Range1, ..=96_000_000) => Latency::WS3,
+        (VoltageScale::Range1, ..=120_000_000) => Latency::WS4,
+        (VoltageScale::Range0, ..=30_000_000) => Latency::WS0,
+        (VoltageScale::Range0, ..=60_000_000) => Latency::WS1,
+        (VoltageScale::Range0, ..=90_000_000) => Latency::WS2,
+        (VoltageScale::Range0, ..=120_000_000) => Latency::WS3,
+        _ => unreachable!(),
+    };
+
+    #[cfg(any(stm32f4, stm32f7))]
+    let latency = {
+        // Be conservative with voltage ranges
+        const FLASH_LATENCY_STEP: u32 = 30_000_000;
+
+        let latency = (hclk.0 - 1) / FLASH_LATENCY_STEP;
+        debug!("flash: latency={}", latency);
+
+        Latency::from_bits(latency as u8)
+    };
+
+    FLASH.acr().write(|w| w.set_latency(latency));
+    while FLASH.acr().read().latency() != latency {}
 
     RCC.cfgr().modify(|w| {
         w.set_sw(config.sys);
@@ -232,7 +297,7 @@ struct PllOutput {
 #[derive(PartialEq, Eq, Clone, Copy)]
 enum PllInstance {
     Pll,
-    #[cfg(any(all(stm32f4, not(stm32f410)), stm32f7))]
+    #[cfg(any(stm32f2, all(stm32f4, not(stm32f410)), stm32f7))]
     Plli2s,
     #[cfg(any(stm32f446, stm32f427, stm32f437, stm32f4x9, stm32f7))]
     Pllsai,
@@ -244,7 +309,7 @@ fn pll_enable(instance: PllInstance, enabled: bool) {
             RCC.cr().modify(|w| w.set_pllon(enabled));
             while RCC.cr().read().pllrdy() != enabled {}
         }
-        #[cfg(any(all(stm32f4, not(stm32f410)), stm32f7))]
+        #[cfg(any(stm32f2, all(stm32f4, not(stm32f410)), stm32f7))]
         PllInstance::Plli2s => {
             RCC.cr().modify(|w| w.set_plli2son(enabled));
             while RCC.cr().read().plli2srdy() != enabled {}
@@ -275,6 +340,18 @@ fn init_pll(instance: PllInstance, config: Option<Pll>, input: &PllInput) -> Pll
     let vco_freq = in_freq * pll.mul;
     assert!(max::PLL_VCO.contains(&vco_freq));
 
+    // stm32f2 plls are like swiss cheese
+    #[cfg(stm32f2)]
+    match instance {
+        PllInstance::Pll => {
+            assert!(pll.divr.is_none());
+        }
+        PllInstance::Plli2s => {
+            assert!(pll.divp.is_none());
+            assert!(pll.divq.is_none());
+        }
+    }
+
     let p = pll.divp.map(|div| vco_freq / div);
     let q = pll.divq.map(|div| vco_freq / div);
     let r = pll.divr.map(|div| vco_freq / div);
@@ -288,6 +365,7 @@ fn init_pll(instance: PllInstance, config: Option<Pll>, input: &PllInput) -> Pll
             if let Some(divq) = pll.divq {
                 $w.set_pllq(divq);
             }
+            #[cfg(any(stm32f4, stm32f7))]
             if let Some(divr) = pll.divr {
                 $w.set_pllr(divr);
             }
@@ -304,6 +382,12 @@ fn init_pll(instance: PllInstance, config: Option<Pll>, input: &PllInput) -> Pll
         PllInstance::Plli2s => RCC.plli2scfgr().write(|w| {
             write_fields!(w);
         }),
+        #[cfg(stm32f2)]
+        PllInstance::Plli2s => RCC.plli2scfgr().write(|w| {
+            if let Some(divr) = pll.divr {
+                w.set_pllr(divr);
+            }
+        }),
         #[cfg(any(stm32f446, stm32f427, stm32f437, stm32f4x9, stm32f7))]
         PllInstance::Pllsai => RCC.pllsaicfgr().write(|w| {
             write_fields!(w);
@@ -316,22 +400,6 @@ fn init_pll(instance: PllInstance, config: Option<Pll>, input: &PllInput) -> Pll
     PllOutput { p, q, r }
 }
 
-fn flash_setup(clk: Hertz) {
-    use crate::pac::flash::vals::Latency;
-
-    // Be conservative with voltage ranges
-    const FLASH_LATENCY_STEP: u32 = 30_000_000;
-
-    let latency = (clk.0 - 1) / FLASH_LATENCY_STEP;
-    debug!("flash: latency={}", latency);
-
-    let latency = Latency::from_bits(latency as u8);
-    FLASH.acr().write(|w| {
-        w.set_latency(latency);
-    });
-    while FLASH.acr().read().latency() != latency {}
-}
-
 #[cfg(stm32f7)]
 mod max {
     use core::ops::RangeInclusive;
@@ -380,3 +448,22 @@ mod max {
     pub(crate) const PLL_IN: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(2_100_000);
     pub(crate) const PLL_VCO: RangeInclusive<Hertz> = Hertz(100_000_000)..=Hertz(432_000_000);
 }
+
+#[cfg(stm32f2)]
+mod max {
+    use core::ops::RangeInclusive;
+
+    use crate::time::Hertz;
+
+    pub(crate) const HSE_OSC: RangeInclusive<Hertz> = Hertz(4_000_000)..=Hertz(26_000_000);
+    pub(crate) const HSE_BYP: RangeInclusive<Hertz> = Hertz(1_000_000)..=Hertz(26_000_000);
+
+    pub(crate) const SYSCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(120_000_000);
+
+    pub(crate) const HCLK: RangeInclusive<Hertz> = Hertz(0)..=Hertz(SYSCLK.end().0);
+    pub(crate) const PCLK1: RangeInclusive<Hertz> = Hertz(0)..=Hertz(SYSCLK.end().0 / 4);
+    pub(crate) const PCLK2: RangeInclusive<Hertz> = Hertz(0)..=Hertz(SYSCLK.end().0 / 2);
+
+    pub(crate) const PLL_IN: RangeInclusive<Hertz> = Hertz(0_950_000)..=Hertz(2_100_000);
+    pub(crate) const PLL_VCO: RangeInclusive<Hertz> = Hertz(192_000_000)..=Hertz(432_000_000);
+}

embassy-stm32/src/rcc/f2.rs

@@ -1,320 +0,0 @@
-use crate::pac::flash::vals::Latency;
-use crate::pac::rcc::vals::Sw;
-pub use crate::pac::rcc::vals::{
-    Hpre as AHBPrescaler, Pllm as PLLPreDiv, Plln as PLLMul, Pllp as PLLPDiv, Pllq as PLLQDiv, Pllsrc as PLLSrc,
-    Ppre as APBPrescaler,
-};
-use crate::pac::{FLASH, RCC};
-use crate::rcc::{set_freqs, Clocks};
-use crate::time::Hertz;
-
-/// HSI speed
-pub const HSI_FREQ: Hertz = Hertz(16_000_000);
-
-#[derive(Clone, Copy)]
-pub struct HSEConfig {
-    pub frequency: Hertz,
-    pub source: HSESrc,
-}
-
-/// System clock mux source
-#[derive(Clone, Copy)]
-pub enum ClockSrc {
-    HSE,
-    HSI,
-    PLL,
-}
-
-/// HSE clock source
-#[derive(Clone, Copy)]
-pub enum HSESrc {
-    /// Crystal/ceramic resonator
-    Crystal,
-    /// External clock source, HSE bypassed
-    Bypass,
-}
-
-#[derive(Clone, Copy)]
-pub struct PLLConfig {
-    pub pre_div: PLLPreDiv,
-    pub mul: PLLMul,
-    pub p_div: PLLPDiv,
-    pub q_div: PLLQDiv,
-}
-
-impl Default for PLLConfig {
-    fn default() -> Self {
-        PLLConfig {
-            pre_div: PLLPreDiv::DIV16,
-            mul: PLLMul::MUL192,
-            p_div: PLLPDiv::DIV2,
-            q_div: PLLQDiv::DIV4,
-        }
-    }
-}
-
-impl PLLConfig {
-    pub fn clocks(&self, src_freq: Hertz) -> PLLClocks {
-        let in_freq = src_freq / self.pre_div;
-        let vco_freq = src_freq / self.pre_div * self.mul;
-        let main_freq = vco_freq / self.p_div;
-        let pll48_freq = vco_freq / self.q_div;
-        PLLClocks {
-            in_freq,
-            vco_freq,
-            main_freq,
-            pll48_freq,
-        }
-    }
-}
-#[derive(Clone, Copy, PartialEq)]
-pub struct PLLClocks {
-    pub in_freq: Hertz,
-    pub vco_freq: Hertz,
-    pub main_freq: Hertz,
-    pub pll48_freq: Hertz,
-}
-
-/// Voltage range of the power supply used.
-///
-/// Used to calculate flash waitstates. See
-/// RM0033 - Table 3. Number of wait states according to Cortex®-M3 clock frequency
-pub enum VoltageScale {
-    /// 2.7 to 3.6 V
-    Range0,
-    /// 2.4 to 2.7 V
-    Range1,
-    /// 2.1 to 2.4 V
-    Range2,
-    /// 1.8 to 2.1 V
-    Range3,
-}
-
-impl VoltageScale {
-    const fn wait_states(&self, ahb_freq: Hertz) -> Option<Latency> {
-        let ahb_freq = ahb_freq.0;
-        // Reference: RM0033 - Table 3. Number of wait states according to Cortex®-M3 clock
-        // frequency
-        match self {
-            VoltageScale::Range3 => {
-                if ahb_freq <= 16_000_000 {
-                    Some(Latency::WS0)
-                } else if ahb_freq <= 32_000_000 {
-                    Some(Latency::WS1)
-                } else if ahb_freq <= 48_000_000 {
-                    Some(Latency::WS2)
-                } else if ahb_freq <= 64_000_000 {
-                    Some(Latency::WS3)
-                } else if ahb_freq <= 80_000_000 {
-                    Some(Latency::WS4)
-                } else if ahb_freq <= 96_000_000 {
-                    Some(Latency::WS5)
-                } else if ahb_freq <= 112_000_000 {
-                    Some(Latency::WS6)
-                } else if ahb_freq <= 120_000_000 {
-                    Some(Latency::WS7)
-                } else {
-                    None
-                }
-            }
-            VoltageScale::Range2 => {
-                if ahb_freq <= 18_000_000 {
-                    Some(Latency::WS0)
-                } else if ahb_freq <= 36_000_000 {
-                    Some(Latency::WS1)
-                } else if ahb_freq <= 54_000_000 {
-                    Some(Latency::WS2)
-                } else if ahb_freq <= 72_000_000 {
-                    Some(Latency::WS3)
-                } else if ahb_freq <= 90_000_000 {
-                    Some(Latency::WS4)
-                } else if ahb_freq <= 108_000_000 {
-                    Some(Latency::WS5)
-                } else if ahb_freq <= 120_000_000 {
-                    Some(Latency::WS6)
-                } else {
-                    None
-                }
-            }
-            VoltageScale::Range1 => {
-                if ahb_freq <= 24_000_000 {
-                    Some(Latency::WS0)
-                } else if ahb_freq <= 48_000_000 {
-                    Some(Latency::WS1)
-                } else if ahb_freq <= 72_000_000 {
-                    Some(Latency::WS2)
-                } else if ahb_freq <= 96_000_000 {
-                    Some(Latency::WS3)
-                } else if ahb_freq <= 120_000_000 {
-                    Some(Latency::WS4)
-                } else {
-                    None
-                }
-            }
-            VoltageScale::Range0 => {
-                if ahb_freq <= 30_000_000 {
-                    Some(Latency::WS0)
-                } else if ahb_freq <= 60_000_000 {
-                    Some(Latency::WS1)
-                } else if ahb_freq <= 90_000_000 {
-                    Some(Latency::WS2)
-                } else if ahb_freq <= 120_000_000 {
-                    Some(Latency::WS3)
-                } else {
-                    None
-                }
-            }
-        }
-    }
-}
-
-/// Clocks configuration
-pub struct Config {
-    pub hse: Option<HSEConfig>,
-    pub hsi: bool,
-    pub pll_mux: PLLSrc,
-    pub pll: PLLConfig,
-    pub mux: ClockSrc,
-    pub voltage: VoltageScale,
-    pub ahb_pre: AHBPrescaler,
-    pub apb1_pre: APBPrescaler,
-    pub apb2_pre: APBPrescaler,
-    pub ls: super::LsConfig,
-}
-
-impl Default for Config {
-    #[inline]
-    fn default() -> Config {
-        Config {
-            hse: None,
-            hsi: true,
-            pll_mux: PLLSrc::HSI,
-            pll: PLLConfig::default(),
-            voltage: VoltageScale::Range3,
-            mux: ClockSrc::HSI,
-            ahb_pre: AHBPrescaler::DIV1,
-            apb1_pre: APBPrescaler::DIV1,
-            apb2_pre: APBPrescaler::DIV1,
-            ls: Default::default(),
-        }
-    }
-}
-
-pub(crate) unsafe fn init(config: Config) {
-    // Make sure HSI is enabled
-    RCC.cr().write(|w| w.set_hsion(true));
-    while !RCC.cr().read().hsirdy() {}
-
-    if let Some(hse_config) = config.hse {
-        RCC.cr().modify(|w| {
-            w.set_hsebyp(match hse_config.source {
-                HSESrc::Bypass => true,
-                HSESrc::Crystal => false,
-            });
-            w.set_hseon(true)
-        });
-        while !RCC.cr().read().hserdy() {}
-    }
-
-    let pll_src_freq = match config.pll_mux {
-        PLLSrc::HSE => {
-            let hse_config = config
-                .hse
-                .unwrap_or_else(|| panic!("HSE must be configured to be used as PLL input"));
-            hse_config.frequency
-        }
-        PLLSrc::HSI => HSI_FREQ,
-    };
-
-    // Reference: STM32F215xx/217xx datasheet Table 33. Main PLL characteristics
-    let pll_clocks = config.pll.clocks(pll_src_freq);
-    assert!(Hertz(950_000) <= pll_clocks.in_freq && pll_clocks.in_freq <= Hertz(2_100_000));
-    assert!(Hertz(192_000_000) <= pll_clocks.vco_freq && pll_clocks.vco_freq <= Hertz(432_000_000));
-    assert!(Hertz(24_000_000) <= pll_clocks.main_freq && pll_clocks.main_freq <= Hertz(120_000_000));
-    // USB actually requires == 48 MHz, but other PLL48 peripherals are fine with <= 48MHz
-    assert!(pll_clocks.pll48_freq <= Hertz(48_000_000));
-
-    RCC.pllcfgr().write(|w| {
-        w.set_pllsrc(config.pll_mux);
-        w.set_pllm(config.pll.pre_div);
-        w.set_plln(config.pll.mul);
-        w.set_pllp(config.pll.p_div);
-        w.set_pllq(config.pll.q_div);
-    });
-
-    let (sys_clk, sw) = match config.mux {
-        ClockSrc::HSI => {
-            assert!(config.hsi, "HSI must be enabled to be used as system clock");
-            (HSI_FREQ, Sw::HSI)
-        }
-        ClockSrc::HSE => {
-            let hse_config = config
-                .hse
-                .unwrap_or_else(|| panic!("HSE must be configured to be used as PLL input"));
-            (hse_config.frequency, Sw::HSE)
-        }
-        ClockSrc::PLL => {
-            RCC.cr().modify(|w| w.set_pllon(true));
-            while !RCC.cr().read().pllrdy() {}
-            (pll_clocks.main_freq, Sw::PLL1_P)
-        }
-    };
-    // RM0033 Figure 9. Clock tree suggests max SYSCLK/HCLK is 168 MHz, but datasheet specifies PLL
-    // max output to be 120 MHz, so there's no way to get higher frequencies
-    assert!(sys_clk <= Hertz(120_000_000));
-
-    let ahb_freq = sys_clk / config.ahb_pre;
-    // Reference: STM32F215xx/217xx datasheet Table 13. General operating conditions
-    assert!(ahb_freq <= Hertz(120_000_000));
-
-    let (apb1_freq, apb1_tim_freq) = match config.apb1_pre {
-        APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
-        pre => {
-            let freq = ahb_freq / pre;
-            (freq, Hertz(freq.0 * 2))
-        }
-    };
-    // Reference: STM32F215xx/217xx datasheet Table 13. General operating conditions
-    assert!(apb1_freq <= Hertz(30_000_000));
-
-    let (apb2_freq, apb2_tim_freq) = match config.apb2_pre {
-        APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
-        pre => {
-            let freq = ahb_freq / pre;
-            (freq, Hertz(freq.0 * 2))
-        }
-    };
-    // Reference: STM32F215xx/217xx datasheet Table 13. General operating conditions
-    assert!(apb2_freq <= Hertz(60_000_000));
-
-    let flash_ws = unwrap!(config.voltage.wait_states(ahb_freq));
-    FLASH.acr().modify(|w| w.set_latency(flash_ws));
-
-    RCC.cfgr().modify(|w| {
-        w.set_sw(sw.into());
-        w.set_hpre(config.ahb_pre);
-        w.set_ppre1(config.apb1_pre);
-        w.set_ppre2(config.apb2_pre);
-    });
-    while RCC.cfgr().read().sws().to_bits() != sw.to_bits() {}
-
-    // Turn off HSI to save power if we don't need it
-    if !config.hsi {
-        RCC.cr().modify(|w| w.set_hsion(false));
-    }
-
-    let rtc = config.ls.init();
-
-    set_freqs(Clocks {
-        sys: sys_clk,
-        hclk1: ahb_freq,
-        hclk2: ahb_freq,
-        hclk3: ahb_freq,
-        pclk1: apb1_freq,
-        pclk1_tim: apb1_tim_freq,
-        pclk2: apb2_freq,
-        pclk2_tim: apb2_tim_freq,
-        pll1_q: Some(pll_clocks.pll48_freq),
-        rtc,
-    });
-}

embassy-stm32/src/rcc/g0.rs

@@ -28,7 +28,7 @@ pub enum ClockSrc {
 #[derive(Clone, Copy)]
 pub struct PllConfig {
     /// The source from which the PLL receives a clock signal
-    pub source: PllSrc,
+    pub source: PllSource,
     /// The initial divisor of that clock signal
     pub m: Pllm,
     /// The PLL VCO multiplier, which must be in the range `8..=86`.
@@ -48,7 +48,7 @@ impl Default for PllConfig {
     fn default() -> PllConfig {
         // HSI / 1 * 8 / 2 = 64 MHz
         PllConfig {
-            source: PllSrc::HSI,
+            source: PllSource::HSI,
             m: Pllm::DIV1,
             n: Plln::MUL8,
             r: Pllr::DIV2,
@@ -59,7 +59,7 @@ impl Default for PllConfig {
 }
 
 #[derive(Clone, Copy, Eq, PartialEq)]
-pub enum PllSrc {
+pub enum PllSource {
     HSI,
     HSE(Hertz),
 }
@@ -89,8 +89,8 @@ impl Default for Config {
 impl PllConfig {
     pub(crate) fn init(self) -> Hertz {
         let (src, input_freq) = match self.source {
-            PllSrc::HSI => (vals::Pllsrc::HSI, HSI_FREQ),
+            PllSource::HSI => (vals::Pllsrc::HSI, HSI_FREQ),
-            PllSrc::HSE(freq) => (vals::Pllsrc::HSE, freq),
+            PllSource::HSE(freq) => (vals::Pllsrc::HSE, freq),
         };
 
         let m_freq = input_freq / self.m;
@@ -121,11 +121,11 @@ impl PllConfig {
         // > 3. Change the desired parameter.
         // Enable whichever clock source we're using, and wait for it to become ready
         match self.source {
-            PllSrc::HSI => {
+            PllSource::HSI => {
                 RCC.cr().write(|w| w.set_hsion(true));
                 while !RCC.cr().read().hsirdy() {}
             }
-            PllSrc::HSE(_) => {
+            PllSource::HSE(_) => {
                 RCC.cr().write(|w| w.set_hseon(true));
                 while !RCC.cr().read().hserdy() {}
             }

embassy-stm32/src/rcc/g4.rs

@@ -23,16 +23,16 @@ pub enum ClockSrc {
 
 /// PLL clock input source
 #[derive(Clone, Copy, Debug)]
-pub enum PllSrc {
+pub enum PllSource {
     HSI,
     HSE(Hertz),
 }
 
-impl Into<Pllsrc> for PllSrc {
+impl Into<Pllsrc> for PllSource {
     fn into(self) -> Pllsrc {
         match self {
-            PllSrc::HSE(..) => Pllsrc::HSE,
+            PllSource::HSE(..) => Pllsrc::HSE,
-            PllSrc::HSI => Pllsrc::HSI,
+            PllSource::HSI => Pllsrc::HSI,
         }
     }
 }
@@ -44,7 +44,7 @@ impl Into<Pllsrc> for PllSrc {
 /// frequency ranges for each of these settings.
 pub struct Pll {
     /// PLL Source clock selection.
-    pub source: PllSrc,
+    pub source: PllSource,
 
     /// PLL pre-divider
     pub prediv_m: PllM,
@@ -118,13 +118,13 @@ pub struct PllFreq {
 pub(crate) unsafe fn init(config: Config) {
     let pll_freq = config.pll.map(|pll_config| {
         let src_freq = match pll_config.source {
-            PllSrc::HSI => {
+            PllSource::HSI => {
                 RCC.cr().write(|w| w.set_hsion(true));
                 while !RCC.cr().read().hsirdy() {}
 
                 HSI_FREQ
             }
-            PllSrc::HSE(freq) => {
+            PllSource::HSE(freq) => {
                 RCC.cr().write(|w| w.set_hseon(true));
                 while !RCC.cr().read().hserdy() {}
                 freq

embassy-stm32/src/rcc/l.rs

@@ -1,12 +1,13 @@
+#[cfg(any(stm32l0, stm32l1))]
+pub use crate::pac::pwr::vals::Vos as VoltageScale;
 use crate::pac::rcc::regs::Cfgr;
-#[cfg(any(stm32l4, stm32l5, stm32wb))]
+#[cfg(any(stm32l4, stm32l5, stm32wb, stm32wl))]
+pub use crate::pac::rcc::vals::Adcsel as AdcClockSource;
+#[cfg(any(rcc_l0_v2, stm32l4, stm32l5, stm32wb))]
 pub use crate::pac::rcc::vals::Clk48sel as Clk48Src;
 #[cfg(any(stm32wb, stm32wl))]
 pub use crate::pac::rcc::vals::Hsepre as HsePrescaler;
-pub use crate::pac::rcc::vals::{
+pub use crate::pac::rcc::vals::{Hpre as AHBPrescaler, Msirange as MSIRange, Ppre as APBPrescaler, Sw as ClockSrc};
-    Adcsel as AdcClockSource, Hpre as AHBPrescaler, Msirange as MSIRange, Pllm as PllPreDiv, Plln as PllMul,
-    Pllp as PllPDiv, Pllq as PllQDiv, Pllr as PllRDiv, Pllsrc as PLLSource, Ppre as APBPrescaler, Sw as ClockSrc,
-};
 use crate::pac::{FLASH, RCC};
 use crate::rcc::{set_freqs, Clocks};
 use crate::time::Hertz;
@@ -33,25 +34,6 @@ pub struct Hse {
     pub prescaler: HsePrescaler,
 }
 
-#[derive(Clone, Copy)]
-pub struct Pll {
-    /// PLL source
-    pub source: PLLSource,
-
-    /// PLL pre-divider (DIVM).
-    pub prediv: PllPreDiv,
-
-    /// PLL multiplication factor.
-    pub mul: PllMul,
-
-    /// PLL P division factor. If None, PLL P output is disabled.
-    pub divp: Option<PllPDiv>,
-    /// PLL Q division factor. If None, PLL Q output is disabled.
-    pub divq: Option<PllQDiv>,
-    /// PLL R division factor. If None, PLL R output is disabled.
-    pub divr: Option<PllRDiv>,
-}
-
 /// Clocks configuration
 pub struct Config {
     // base clock sources
@@ -79,13 +61,17 @@ pub struct Config {
     pub shared_ahb_pre: AHBPrescaler,
 
     // muxes
-    #[cfg(any(stm32l4, stm32l5, stm32wb))]
+    #[cfg(any(rcc_l0_v2, stm32l4, stm32l5, stm32wb))]
     pub clk48_src: Clk48Src,
 
     // low speed LSI/LSE/RTC
     pub ls: super::LsConfig,
 
+    #[cfg(any(stm32l4, stm32l5, stm32wb, stm32wl))]
     pub adc_clock_source: AdcClockSource,
+
+    #[cfg(any(stm32l0, stm32l1))]
+    pub voltage_scale: VoltageScale,
 }
 
 impl Default for Config {
@@ -110,10 +96,13 @@ impl Default for Config {
             pllsai2: None,
             #[cfg(crs)]
             hsi48: Some(Default::default()),
-            #[cfg(any(stm32l4, stm32l5, stm32wb))]
+            #[cfg(any(rcc_l0_v2, stm32l4, stm32l5, stm32wb))]
             clk48_src: Clk48Src::HSI48,
             ls: Default::default(),
+            #[cfg(any(stm32l4, stm32l5, stm32wb, stm32wl))]
             adc_clock_source: AdcClockSource::SYS,
+            #[cfg(any(stm32l0, stm32l1))]
+            voltage_scale: VoltageScale::RANGE1,
         }
     }
 }
@@ -135,7 +124,7 @@ pub const WPAN_DEFAULT: Config = Config {
     ls: super::LsConfig::default_lse(),
 
     pll: Some(Pll {
-        source: PLLSource::HSE,
+        source: PllSource::HSE,
         prediv: PllPreDiv::DIV2,
         mul: PllMul::MUL12,
         divp: Some(PllPDiv::DIV3), // 32 / 2 * 12 / 3 = 64Mhz
@@ -152,20 +141,26 @@ pub const WPAN_DEFAULT: Config = Config {
     adc_clock_source: AdcClockSource::SYS,
 };
 
+fn msi_enable(range: MSIRange) {
+    #[cfg(any(stm32l4, stm32l5, stm32wb, stm32wl))]
+    RCC.cr().modify(|w| {
+        #[cfg(not(stm32wb))]
+        w.set_msirgsel(crate::pac::rcc::vals::Msirgsel::CR);
+        w.set_msirange(range);
+        w.set_msipllen(false);
+    });
+    #[cfg(any(stm32l0, stm32l1))]
+    RCC.icscr().modify(|w| w.set_msirange(range));
+
+    RCC.cr().modify(|w| w.set_msion(true));
+    while !RCC.cr().read().msirdy() {}
+}
+
 pub(crate) unsafe fn init(config: Config) {
     // Switch to MSI to prevent problems with PLL configuration.
     if !RCC.cr().read().msion() {
         // Turn on MSI and configure it to 4MHz.
-        RCC.cr().modify(|w| {
+        msi_enable(MSIRange::RANGE4M)
-            #[cfg(not(stm32wb))]
-            w.set_msirgsel(crate::pac::rcc::vals::Msirgsel::CR);
-            w.set_msirange(MSIRange::RANGE4M);
-            w.set_msipllen(false);
-            w.set_msion(true)
-        });
-
-        // Wait until MSI is running
-        while !RCC.cr().read().msirdy() {}
     }
     if RCC.cfgr().read().sws() != ClockSrc::MSI {
         // Set MSI as a clock source, reset prescalers.
@@ -174,6 +169,14 @@ pub(crate) unsafe fn init(config: Config) {
         while RCC.cfgr().read().sws() != ClockSrc::MSI {}
     }
 
+    // Set voltage scale
+    #[cfg(any(stm32l0, stm32l1))]
+    {
+        while crate::pac::PWR.csr().read().vosf() {}
+        crate::pac::PWR.cr().write(|w| w.set_vos(config.voltage_scale));
+        while crate::pac::PWR.csr().read().vosf() {}
+    }
+
     #[cfg(stm32l5)]
     crate::pac::PWR.cr1().modify(|w| {
         w.set_vos(crate::pac::pwr::vals::Vos::RANGE0);
@@ -182,21 +185,16 @@ pub(crate) unsafe fn init(config: Config) {
     let rtc = config.ls.init();
 
     let msi = config.msi.map(|range| {
-        // Enable MSI
+        msi_enable(range);
-        RCC.cr().modify(|w| {
-            #[cfg(not(stm32wb))]
-            w.set_msirgsel(crate::pac::rcc::vals::Msirgsel::CR);
-            w.set_msirange(range);
-            w.set_msion(true);
-
-            // If LSE is enabled, enable calibration of MSI
-            w.set_msipllen(config.ls.lse.is_some());
-        });
-        while !RCC.cr().read().msirdy() {}
-
         msirange_to_hertz(range)
     });
 
+    // If LSE is enabled and the right freq, enable calibration of MSI
+    #[cfg(any(stm32l4, stm32l5, stm32wb, stm32wl))]
+    if config.ls.lse.map(|x| x.frequency) == Some(Hertz(32_768)) {
+        RCC.cr().modify(|w| w.set_msipllen(true));
+    }
+
     let hsi = config.hsi.then(|| {
         RCC.cr().modify(|w| w.set_hsion(true));
         while !RCC.cr().read().hsirdy() {}
@@ -218,7 +216,10 @@ pub(crate) unsafe fn init(config: Config) {
     });
 
     #[cfg(crs)]
-    let _hsi48 = config.hsi48.map(super::init_hsi48);
+    let _hsi48 = config.hsi48.map(|config| {
+        //
+        super::init_hsi48(config)
+    });
     #[cfg(not(crs))]
     let _hsi48: Option<Hertz> = None;
 
@@ -251,7 +252,12 @@ pub(crate) unsafe fn init(config: Config) {
         }),
     };
 
-    let pll_input = PllInput { hse, hsi, msi };
+    let pll_input = PllInput {
+        hse,
+        hsi,
+        #[cfg(any(stm32l4, stm32l5, stm32wb, stm32wl))]
+        msi,
+    };
     let pll = init_pll(PllInstance::Pll, config.pll, &pll_input);
     #[cfg(any(stm32l4, stm32l5, stm32wb))]
     let pllsai1 = init_pll(PllInstance::Pllsai1, config.pllsai1, &pll_input);
@@ -265,10 +271,13 @@ pub(crate) unsafe fn init(config: Config) {
         ClockSrc::PLL1_R => pll.r.unwrap(),
     };
 
-    #[cfg(stm32l4)]
+    #[cfg(any(rcc_l0_v2, stm32l4, stm32l5, stm32wb))]
     RCC.ccipr().modify(|w| w.set_clk48sel(config.clk48_src));
-    #[cfg(stm32l5)]
+    #[cfg(any(rcc_l0_v2))]
-    RCC.ccipr1().modify(|w| w.set_clk48sel(config.clk48_src));
+    let _clk48 = match config.clk48_src {
+        Clk48Src::HSI48 => _hsi48,
+        Clk48Src::PLL1_VCO_DIV_2 => pll.clk48,
+    };
     #[cfg(any(stm32l4, stm32l5, stm32wb))]
     let _clk48 = match config.clk48_src {
         Clk48Src::HSI48 => _hsi48,
@@ -285,16 +294,23 @@ pub(crate) unsafe fn init(config: Config) {
     let hclk1 = sys_clk / config.ahb_pre;
     let (pclk1, pclk1_tim) = super::util::calc_pclk(hclk1, config.apb1_pre);
     let (pclk2, pclk2_tim) = super::util::calc_pclk(hclk1, config.apb2_pre);
-    #[cfg(not(any(stm32wl5x, stm32wb)))]
+    #[cfg(any(stm32l4, stm32l5, stm32wlex))]
     let hclk2 = hclk1;
     #[cfg(any(stm32wl5x, stm32wb))]
     let hclk2 = sys_clk / config.core2_ahb_pre;
-    #[cfg(not(any(stm32wl, stm32wb)))]
+    #[cfg(any(stm32l4, stm32l5, stm32wlex))]
     let hclk3 = hclk1;
-    #[cfg(any(stm32wl, stm32wb))]
+    #[cfg(any(stm32wl5x, stm32wb))]
     let hclk3 = sys_clk / config.shared_ahb_pre;
 
     // Set flash wait states
+    #[cfg(any(stm32l0, stm32l1))]
+    let latency = match (config.voltage_scale, sys_clk.0) {
+        (VoltageScale::RANGE1, ..=16_000_000) => false,
+        (VoltageScale::RANGE2, ..=8_000_000) => false,
+        (VoltageScale::RANGE3, ..=4_200_000) => false,
+        _ => true,
+    };
     #[cfg(stm32l4)]
     let latency = match hclk1.0 {
         0..=16_000_000 => 0,
@@ -330,6 +346,10 @@ pub(crate) unsafe fn init(config: Config) {
         _ => 4,
     };
 
+    #[cfg(stm32l1)]
+    FLASH.acr().write(|w| w.set_acc64(true));
+    #[cfg(not(stm32l5))]
+    FLASH.acr().modify(|w| w.set_prften(true));
     FLASH.acr().modify(|w| w.set_latency(latency));
     while FLASH.acr().read().latency() != latency {}
 
@@ -341,9 +361,7 @@ pub(crate) unsafe fn init(config: Config) {
     });
     while RCC.cfgr().read().sws() != config.mux {}
 
-    #[cfg(stm32l5)]
+    #[cfg(any(stm32l4, stm32l5, stm32wb, stm32wl))]
-    RCC.ccipr1().modify(|w| w.set_adcsel(config.adc_clock_source));
-    #[cfg(not(stm32l5))]
     RCC.ccipr().modify(|w| w.set_adcsel(config.adc_clock_source));
 
     #[cfg(any(stm32wl, stm32wb))]
@@ -361,7 +379,9 @@ pub(crate) unsafe fn init(config: Config) {
     set_freqs(Clocks {
         sys: sys_clk,
         hclk1,
+        #[cfg(any(stm32l4, stm32l5, stm32wb, stm32wl))]
         hclk2,
+        #[cfg(any(stm32l4, stm32l5, stm32wb, stm32wl))]
         hclk3,
         pclk1,
         pclk2,
@@ -389,6 +409,12 @@ pub(crate) unsafe fn init(config: Config) {
     });
 }
 
+#[cfg(any(stm32l0, stm32l1))]
+fn msirange_to_hertz(range: MSIRange) -> Hertz {
+    Hertz(32_768 * (1 << (range as u8 + 1)))
+}
+
+#[cfg(any(stm32l4, stm32l5, stm32wb, stm32wl))]
 fn msirange_to_hertz(range: MSIRange) -> Hertz {
     match range {
         MSIRange::RANGE100K => Hertz(100_000),
@@ -407,20 +433,6 @@ fn msirange_to_hertz(range: MSIRange) -> Hertz {
     }
 }
 
-struct PllInput {
-    hsi: Option<Hertz>,
-    hse: Option<Hertz>,
-    msi: Option<Hertz>,
-}
-
-#[allow(unused)]
-#[derive(Default)]
-struct PllOutput {
-    p: Option<Hertz>,
-    q: Option<Hertz>,
-    r: Option<Hertz>,
-}
-
 #[derive(PartialEq, Eq, Clone, Copy)]
 enum PllInstance {
     Pll,
@@ -449,20 +461,124 @@ fn pll_enable(instance: PllInstance, enabled: bool) {
     }
 }
 
-fn init_pll(instance: PllInstance, config: Option<Pll>, input: &PllInput) -> PllOutput {
+pub use pll::*;
+
+#[cfg(any(stm32l0, stm32l1))]
+mod pll {
+    use super::{pll_enable, PllInstance};
+    pub use crate::pac::rcc::vals::{Plldiv as PllDiv, Pllmul as PllMul, Pllsrc as PllSource};
+    use crate::pac::RCC;
+    use crate::time::Hertz;
+
+    #[derive(Clone, Copy)]
+    pub struct Pll {
+        /// PLL source
+        pub source: PllSource,
+
+        /// PLL multiplication factor.
+        pub mul: PllMul,
+
+        /// PLL main output division factor.
+        pub div: PllDiv,
+    }
+
+    pub(super) struct PllInput {
+        pub hsi: Option<Hertz>,
+        pub hse: Option<Hertz>,
+    }
+
+    #[allow(unused)]
+    #[derive(Default)]
+    pub(super) struct PllOutput {
+        pub r: Option<Hertz>,
+        pub clk48: Option<Hertz>,
+    }
+
+    pub(super) fn init_pll(instance: PllInstance, config: Option<Pll>, input: &PllInput) -> PllOutput {
         // Disable PLL
         pll_enable(instance, false);
 
         let Some(pll) = config else { return PllOutput::default() };
 
         let pll_src = match pll.source {
-        PLLSource::DISABLE => panic!("must not select PLL source as DISABLE"),
+            PllSource::HSE => unwrap!(input.hse),
-        PLLSource::HSE => input.hse,
+            PllSource::HSI => unwrap!(input.hsi),
-        PLLSource::HSI => input.hsi,
-        PLLSource::MSI => input.msi,
         };
 
-    let pll_src = pll_src.unwrap();
+        let vco_freq = pll_src * pll.mul;
+
+        let r = vco_freq / pll.div;
+        let clk48 = (vco_freq == Hertz(96_000_000)).then_some(Hertz(48_000_000));
+
+        assert!(r <= Hertz(32_000_000));
+
+        RCC.cfgr().write(move |w| {
+            w.set_pllmul(pll.mul);
+            w.set_plldiv(pll.div);
+            w.set_pllsrc(pll.source);
+        });
+
+        // Enable PLL
+        pll_enable(instance, true);
+
+        PllOutput { r: Some(r), clk48 }
+    }
+}
+
+#[cfg(any(stm32l4, stm32l5, stm32wb, stm32wl))]
+mod pll {
+    use super::{pll_enable, PllInstance};
+    pub use crate::pac::rcc::vals::{
+        Pllm as PllPreDiv, Plln as PllMul, Pllp as PllPDiv, Pllq as PllQDiv, Pllr as PllRDiv, Pllsrc as PllSource,
+    };
+    use crate::pac::RCC;
+    use crate::time::Hertz;
+
+    #[derive(Clone, Copy)]
+    pub struct Pll {
+        /// PLL source
+        pub source: PllSource,
+
+        /// PLL pre-divider (DIVM).
+        pub prediv: PllPreDiv,
+
+        /// PLL multiplication factor.
+        pub mul: PllMul,
+
+        /// PLL P division factor. If None, PLL P output is disabled.
+        pub divp: Option<PllPDiv>,
+        /// PLL Q division factor. If None, PLL Q output is disabled.
+        pub divq: Option<PllQDiv>,
+        /// PLL R division factor. If None, PLL R output is disabled.
+        pub divr: Option<PllRDiv>,
+    }
+
+    pub(super) struct PllInput {
+        pub hsi: Option<Hertz>,
+        pub hse: Option<Hertz>,
+        pub msi: Option<Hertz>,
+    }
+
+    #[allow(unused)]
+    #[derive(Default)]
+    pub(super) struct PllOutput {
+        pub p: Option<Hertz>,
+        pub q: Option<Hertz>,
+        pub r: Option<Hertz>,
+    }
+
+    pub(super) fn init_pll(instance: PllInstance, config: Option<Pll>, input: &PllInput) -> PllOutput {
+        // Disable PLL
+        pll_enable(instance, false);
+
+        let Some(pll) = config else { return PllOutput::default() };
+
+        let pll_src = match pll.source {
+            PllSource::DISABLE => panic!("must not select PLL source as DISABLE"),
+            PllSource::HSE => unwrap!(input.hse),
+            PllSource::HSI => unwrap!(input.hsi),
+            PllSource::MSI => unwrap!(input.msi),
+        };
 
         let vco_freq = pll_src / pll.prediv * pll.mul;
 
@@ -523,3 +639,4 @@ fn init_pll(instance: PllInstance, config: Option<Pll>, input: &PllInput) -> Pll
 
         PllOutput { p, q, r }
     }
+}

embassy-stm32/src/rcc/l0l1.rs

@@ -1,190 +0,0 @@
-pub use crate::pac::pwr::vals::Vos as VoltageScale;
-pub use crate::pac::rcc::vals::{
-    Hpre as AHBPrescaler, Msirange as MSIRange, Plldiv as PLLDiv, Plldiv as PllDiv, Pllmul as PLLMul, Pllmul as PllMul,
-    Pllsrc as PLLSource, Ppre as APBPrescaler, Sw as ClockSrc,
-};
-use crate::pac::{FLASH, PWR, RCC};
-use crate::rcc::{set_freqs, Clocks};
-use crate::time::Hertz;
-
-/// HSI speed
-pub const HSI_FREQ: Hertz = Hertz(16_000_000);
-
-#[derive(Clone, Copy, Eq, PartialEq)]
-pub enum HseMode {
-    /// crystal/ceramic oscillator (HSEBYP=0)
-    Oscillator,
-    /// external analog clock (low swing) (HSEBYP=1)
-    Bypass,
-}
-
-#[derive(Clone, Copy, Eq, PartialEq)]
-pub struct Hse {
-    /// HSE frequency.
-    pub freq: Hertz,
-    /// HSE mode.
-    pub mode: HseMode,
-}
-
-#[derive(Clone, Copy)]
-pub struct Pll {
-    /// PLL source
-    pub source: PLLSource,
-
-    /// PLL multiplication factor.
-    pub mul: PllMul,
-
-    /// PLL main output division factor.
-    pub div: PllDiv,
-}
-
-/// Clocks configutation
-pub struct Config {
-    // base clock sources
-    pub msi: Option<MSIRange>,
-    pub hsi: bool,
-    pub hse: Option<Hse>,
-    #[cfg(crs)]
-    pub hsi48: Option<super::Hsi48Config>,
-
-    pub pll: Option<Pll>,
-
-    pub mux: ClockSrc,
-    pub ahb_pre: AHBPrescaler,
-    pub apb1_pre: APBPrescaler,
-    pub apb2_pre: APBPrescaler,
-
-    pub ls: super::LsConfig,
-    pub voltage_scale: VoltageScale,
-}
-
-impl Default for Config {
-    #[inline]
-    fn default() -> Config {
-        Config {
-            msi: Some(MSIRange::RANGE5),
-            hse: None,
-            hsi: false,
-            #[cfg(crs)]
-            hsi48: Some(Default::default()),
-
-            pll: None,
-
-            mux: ClockSrc::MSI,
-            ahb_pre: AHBPrescaler::DIV1,
-            apb1_pre: APBPrescaler::DIV1,
-            apb2_pre: APBPrescaler::DIV1,
-            voltage_scale: VoltageScale::RANGE1,
-            ls: Default::default(),
-        }
-    }
-}
-
-pub(crate) unsafe fn init(config: Config) {
-    // Set voltage scale
-    while PWR.csr().read().vosf() {}
-    PWR.cr().write(|w| w.set_vos(config.voltage_scale));
-    while PWR.csr().read().vosf() {}
-
-    let rtc = config.ls.init();
-
-    let msi = config.msi.map(|range| {
-        RCC.icscr().modify(|w| w.set_msirange(range));
-
-        RCC.cr().modify(|w| w.set_msion(true));
-        while !RCC.cr().read().msirdy() {}
-
-        Hertz(32_768 * (1 << (range as u8 + 1)))
-    });
-
-    let hsi = config.hsi.then(|| {
-        RCC.cr().modify(|w| w.set_hsion(true));
-        while !RCC.cr().read().hsirdy() {}
-
-        HSI_FREQ
-    });
-
-    let hse = config.hse.map(|hse| {
-        RCC.cr().modify(|w| {
-            w.set_hsebyp(hse.mode == HseMode::Bypass);
-            w.set_hseon(true);
-        });
-        while !RCC.cr().read().hserdy() {}
-
-        hse.freq
-    });
-
-    let pll = config.pll.map(|pll| {
-        let freq = match pll.source {
-            PLLSource::HSE => hse.unwrap(),
-            PLLSource::HSI => hsi.unwrap(),
-        };
-
-        // Disable PLL
-        RCC.cr().modify(|w| w.set_pllon(false));
-        while RCC.cr().read().pllrdy() {}
-
-        let freq = freq * pll.mul / pll.div;
-
-        assert!(freq <= Hertz(32_000_000));
-
-        RCC.cfgr().write(move |w| {
-            w.set_pllmul(pll.mul);
-            w.set_plldiv(pll.div);
-            w.set_pllsrc(pll.source);
-        });
-
-        // Enable PLL
-        RCC.cr().modify(|w| w.set_pllon(true));
-        while !RCC.cr().read().pllrdy() {}
-
-        freq
-    });
-
-    let sys_clk = match config.mux {
-        ClockSrc::HSE => hse.unwrap(),
-        ClockSrc::HSI => hsi.unwrap(),
-        ClockSrc::MSI => msi.unwrap(),
-        ClockSrc::PLL1_P => pll.unwrap(),
-    };
-
-    let wait_states = match (config.voltage_scale, sys_clk.0) {
-        (VoltageScale::RANGE1, ..=16_000_000) => 0,
-        (VoltageScale::RANGE2, ..=8_000_000) => 0,
-        (VoltageScale::RANGE3, ..=4_200_000) => 0,
-        _ => 1,
-    };
-
-    #[cfg(stm32l1)]
-    FLASH.acr().write(|w| w.set_acc64(true));
-    FLASH.acr().modify(|w| w.set_prften(true));
-    FLASH.acr().modify(|w| w.set_latency(wait_states != 0));
-
-    RCC.cfgr().modify(|w| {
-        w.set_sw(config.mux);
-        w.set_hpre(config.ahb_pre);
-        w.set_ppre1(config.apb1_pre);
-        w.set_ppre2(config.apb2_pre);
-    });
-
-    let hclk1 = sys_clk / config.ahb_pre;
-    let (pclk1, pclk1_tim) = super::util::calc_pclk(hclk1, config.apb1_pre);
-    let (pclk2, pclk2_tim) = super::util::calc_pclk(hclk1, config.apb2_pre);
-
-    #[cfg(crs)]
-    let _hsi48 = config.hsi48.map(|config| {
-        // Select HSI48 as USB clock
-        RCC.ccipr().modify(|w| w.set_hsi48msel(true));
-        super::init_hsi48(config)
-    });
-
-    set_freqs(Clocks {
-        sys: sys_clk,
-        hclk1,
-        pclk1,
-        pclk2,
-        pclk1_tim,
-        pclk2_tim,
-        rtc,
-    });
-}

embassy-stm32/src/rcc/mod.rs

@@ -15,16 +15,14 @@ mod hsi48;
 pub use hsi48::*;
 
 #[cfg_attr(rcc_f0, path = "f0.rs")]
-#[cfg_attr(any(rcc_f1, rcc_f100, rcc_f1cl), path = "f1.rs")]
+#[cfg_attr(any(stm32f1), path = "f1.rs")]
-#[cfg_attr(rcc_f2, path = "f2.rs")]
+#[cfg_attr(any(stm32f3), path = "f3.rs")]
-#[cfg_attr(any(rcc_f3, rcc_f3_v2), path = "f3.rs")]
+#[cfg_attr(any(stm32f2, stm32f4, stm32f7), path = "f.rs")]
-#[cfg_attr(any(rcc_f4, rcc_f410, rcc_f7), path = "f4f7.rs")]
 #[cfg_attr(rcc_c0, path = "c0.rs")]
 #[cfg_attr(rcc_g0, path = "g0.rs")]
 #[cfg_attr(rcc_g4, path = "g4.rs")]
-#[cfg_attr(any(rcc_h5, rcc_h50, rcc_h7, rcc_h7rm0433, rcc_h7ab), path = "h.rs")]
+#[cfg_attr(any(stm32h5, stm32h7), path = "h.rs")]
-#[cfg_attr(any(rcc_l0, rcc_l0_v2, rcc_l1), path = "l0l1.rs")]
+#[cfg_attr(any(stm32l0, stm32l1, stm32l4, stm32l5, stm32wb, stm32wl), path = "l.rs")]
-#[cfg_attr(any(rcc_l4, rcc_l4plus, rcc_l5, rcc_wl5, rcc_wle, rcc_wb), path = "l4l5.rs")]
 #[cfg_attr(rcc_u5, path = "u5.rs")]
 #[cfg_attr(rcc_wba, path = "wba.rs")]
 mod _version;

embassy-stm32/src/rcc/u5.rs

@@ -35,7 +35,7 @@ impl Default for ClockSrc {
 #[derive(Clone, Copy)]
 pub struct PllConfig {
     /// The clock source for the PLL.
-    pub source: PllSrc,
+    pub source: PllSource,
     /// The PLL prescaler.
     ///
     /// The clock speed of the `source` divided by `m` must be between 4 and 16 MHz.
@@ -57,7 +57,7 @@ impl PllConfig {
     /// A configuration for HSI / 1 * 10 / 1 = 160 MHz
     pub const fn hsi_160mhz() -> Self {
         PllConfig {
-            source: PllSrc::HSI,
+            source: PllSource::HSI,
             m: Pllm::DIV1,
             n: Plln::MUL10,
             r: Plldiv::DIV1,
@@ -67,7 +67,7 @@ impl PllConfig {
     /// A configuration for MSIS @ 48 MHz / 3 * 10 / 1 = 160 MHz
     pub const fn msis_160mhz() -> Self {
         PllConfig {
-            source: PllSrc::MSIS(Msirange::RANGE_48MHZ),
+            source: PllSource::MSIS(Msirange::RANGE_48MHZ),
             m: Pllm::DIV3,
             n: Plln::MUL10,
             r: Plldiv::DIV1,
@@ -76,7 +76,7 @@ impl PllConfig {
 }
 
 #[derive(Clone, Copy)]
-pub enum PllSrc {
+pub enum PllSource {
     /// Use an internal medium speed oscillator as the PLL source.
     MSIS(Msirange),
     /// Use the external high speed clock as the system PLL source.
@@ -88,12 +88,12 @@ pub enum PllSrc {
     HSI,
 }
 
-impl Into<Pllsrc> for PllSrc {
+impl Into<Pllsrc> for PllSource {
     fn into(self) -> Pllsrc {
         match self {
-            PllSrc::MSIS(..) => Pllsrc::MSIS,
+            PllSource::MSIS(..) => Pllsrc::MSIS,
-            PllSrc::HSE(..) => Pllsrc::HSE,
+            PllSource::HSE(..) => Pllsrc::HSE,
-            PllSrc::HSI => Pllsrc::HSI,
+            PllSource::HSI => Pllsrc::HSI,
         }
     }
 }
@@ -216,9 +216,9 @@ pub(crate) unsafe fn init(config: Config) {
         ClockSrc::PLL1_R(pll) => {
             // Configure the PLL source
             let source_clk = match pll.source {
-                PllSrc::MSIS(range) => config.init_msis(range),
+                PllSource::MSIS(range) => config.init_msis(range),
-                PllSrc::HSE(hertz) => config.init_hse(hertz),
+                PllSource::HSE(hertz) => config.init_hse(hertz),
-                PllSrc::HSI => config.init_hsi(),
+                PllSource::HSI => config.init_hsi(),
             };
 
             // Calculate the reference clock, which is the source divided by m

embassy-stm32/src/rcc/wba.rs

@@ -17,16 +17,16 @@ pub enum ClockSrc {
 }
 
 #[derive(Clone, Copy, Debug)]
-pub enum PllSrc {
+pub enum PllSource {
     HSE(Hertz),
     HSI,
 }
 
-impl Into<Pllsrc> for PllSrc {
+impl Into<Pllsrc> for PllSource {
     fn into(self) -> Pllsrc {
         match self {
-            PllSrc::HSE(..) => Pllsrc::HSE,
+            PllSource::HSE(..) => Pllsrc::HSE,
-            PllSrc::HSI => Pllsrc::HSI,
+            PllSource::HSI => Pllsrc::HSI,
         }
     }
 }

embassy-stm32/src/rtc/mod.rs

@@ -33,6 +33,61 @@ use embassy_hal_internal::Peripheral;
 use crate::peripherals::RTC;
 use crate::rtc::sealed::Instance;
 
+#[allow(dead_code)]
+#[repr(u8)]
+#[derive(Clone, Copy, Debug)]
+pub(crate) enum WakeupPrescaler {
+    Div2 = 2,
+    Div4 = 4,
+    Div8 = 8,
+    Div16 = 16,
+}
+
+#[cfg(any(stm32wb, stm32f4, stm32l0, stm32g4))]
+impl From<WakeupPrescaler> for crate::pac::rtc::vals::Wucksel {
+    fn from(val: WakeupPrescaler) -> Self {
+        use crate::pac::rtc::vals::Wucksel;
+
+        match val {
+            WakeupPrescaler::Div2 => Wucksel::DIV2,
+            WakeupPrescaler::Div4 => Wucksel::DIV4,
+            WakeupPrescaler::Div8 => Wucksel::DIV8,
+            WakeupPrescaler::Div16 => Wucksel::DIV16,
+        }
+    }
+}
+
+#[cfg(any(stm32wb, stm32f4, stm32l0, stm32g4))]
+impl From<crate::pac::rtc::vals::Wucksel> for WakeupPrescaler {
+    fn from(val: crate::pac::rtc::vals::Wucksel) -> Self {
+        use crate::pac::rtc::vals::Wucksel;
+
+        match val {
+            Wucksel::DIV2 => WakeupPrescaler::Div2,
+            Wucksel::DIV4 => WakeupPrescaler::Div4,
+            Wucksel::DIV8 => WakeupPrescaler::Div8,
+            Wucksel::DIV16 => WakeupPrescaler::Div16,
+            _ => unreachable!(),
+        }
+    }
+}
+
+#[cfg(feature = "low-power")]
+impl WakeupPrescaler {
+    pub fn compute_min(val: u32) -> Self {
+        *[
+            WakeupPrescaler::Div2,
+            WakeupPrescaler::Div4,
+            WakeupPrescaler::Div8,
+            WakeupPrescaler::Div16,
+        ]
+        .iter()
+        .skip_while(|psc| **psc as u32 <= val)
+        .next()
+        .unwrap_or(&WakeupPrescaler::Div16)
+    }
+}
+
 /// Errors that can occur on methods on [RtcClock]
 #[non_exhaustive]
 #[derive(Clone, Debug, PartialEq, Eq)]
@@ -277,6 +332,114 @@ impl Rtc {
     pub fn write_backup_register(&self, register: usize, value: u32) {
         RTC::write_backup_register(&RTC::regs(), register, value)
     }
+
+    #[cfg(feature = "low-power")]
+    /// start the wakeup alarm and wtih a duration that is as close to but less than
+    /// the requested duration, and record the instant the wakeup alarm was started
+    pub(crate) fn start_wakeup_alarm(
+        &self,
+        requested_duration: embassy_time::Duration,
+        cs: critical_section::CriticalSection,
+    ) {
+        use embassy_time::{Duration, TICK_HZ};
+
+        #[cfg(any(rtc_v3, rtc_v3u5))]
+        use crate::pac::rtc::vals::Calrf;
+
+        // Panic if the rcc mod knows we're not using low-power rtc
+        #[cfg(any(rcc_wb, rcc_f4, rcc_f410))]
+        unsafe { crate::rcc::get_freqs() }.rtc.unwrap();
+
+        let requested_duration = requested_duration.as_ticks().clamp(0, u32::MAX as u64);
+        let rtc_hz = Self::frequency().0 as u64;
+        let rtc_ticks = requested_duration * rtc_hz / TICK_HZ;
+        let prescaler = WakeupPrescaler::compute_min((rtc_ticks / u16::MAX as u64) as u32);
+
+        // adjust the rtc ticks to the prescaler and subtract one rtc tick
+        let rtc_ticks = rtc_ticks / prescaler as u64;
+        let rtc_ticks = rtc_ticks.clamp(0, (u16::MAX - 1) as u64).saturating_sub(1) as u16;
+
+        self.write(false, |regs| {
+            regs.cr().modify(|w| w.set_wute(false));
+
+            #[cfg(any(
+                rtc_v2f0, rtc_v2f2, rtc_v2f3, rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l1, rtc_v2l4, rtc_v2wb
+            ))]
+            {
+                regs.isr().modify(|w| w.set_wutf(false));
+                while !regs.isr().read().wutwf() {}
+            }
+
+            #[cfg(any(rtc_v3, rtc_v3u5))]
+            {
+                regs.scr().write(|w| w.set_cwutf(Calrf::CLEAR));
+                while !regs.icsr().read().wutwf() {}
+            }
+
+            regs.cr().modify(|w| w.set_wucksel(prescaler.into()));
+            regs.wutr().write(|w| w.set_wut(rtc_ticks));
+            regs.cr().modify(|w| w.set_wute(true));
+            regs.cr().modify(|w| w.set_wutie(true));
+        });
+
+        let instant = self.instant().unwrap();
+        trace!(
+            "rtc: start wakeup alarm for {} ms (psc: {}, ticks: {}) at {}",
+            Duration::from_ticks(rtc_ticks as u64 * TICK_HZ * prescaler as u64 / rtc_hz).as_millis(),
+            prescaler as u32,
+            rtc_ticks,
+            instant,
+        );
+
+        assert!(self.stop_time.borrow(cs).replace(Some(instant)).is_none())
+    }
+
+    #[cfg(feature = "low-power")]
+    /// stop the wakeup alarm and return the time elapsed since `start_wakeup_alarm`
+    /// was called, otherwise none
+    pub(crate) fn stop_wakeup_alarm(&self, cs: critical_section::CriticalSection) -> Option<embassy_time::Duration> {
+        use crate::interrupt::typelevel::Interrupt;
+        #[cfg(any(rtc_v3, rtc_v3u5))]
+        use crate::pac::rtc::vals::Calrf;
+
+        let instant = self.instant().unwrap();
+        if RTC::regs().cr().read().wute() {
+            trace!("rtc: stop wakeup alarm at {}", instant);
+
+            self.write(false, |regs| {
+                regs.cr().modify(|w| w.set_wutie(false));
+                regs.cr().modify(|w| w.set_wute(false));
+
+                #[cfg(any(
+                    rtc_v2f0, rtc_v2f2, rtc_v2f3, rtc_v2f4, rtc_v2f7, rtc_v2h7, rtc_v2l0, rtc_v2l1, rtc_v2l4, rtc_v2wb
+                ))]
+                regs.isr().modify(|w| w.set_wutf(false));
+
+                #[cfg(any(rtc_v3, rtc_v3u5))]
+                regs.scr().write(|w| w.set_cwutf(Calrf::CLEAR));
+
+                crate::pac::EXTI
+                    .pr(0)
+                    .modify(|w| w.set_line(RTC::EXTI_WAKEUP_LINE, true));
+
+                <RTC as crate::rtc::sealed::Instance>::WakeupInterrupt::unpend();
+            });
+        }
+
+        self.stop_time.borrow(cs).take().map(|stop_time| instant - stop_time)
+    }
+
+    #[cfg(feature = "low-power")]
+    pub(crate) fn enable_wakeup_line(&self) {
+        use crate::interrupt::typelevel::Interrupt;
+        use crate::pac::EXTI;
+
+        <RTC as crate::rtc::sealed::Instance>::WakeupInterrupt::unpend();
+        unsafe { <RTC as crate::rtc::sealed::Instance>::WakeupInterrupt::enable() };
+
+        EXTI.rtsr(0).modify(|w| w.set_line(RTC::EXTI_WAKEUP_LINE, true));
+        EXTI.imr(0).modify(|w| w.set_line(RTC::EXTI_WAKEUP_LINE, true));
+    }
 }
 
 pub(crate) fn byte_to_bcd2(byte: u8) -> (u8, u8) {

embassy-stm32/src/rtc/v2.rs

@@ -6,145 +6,7 @@ use crate::peripherals::RTC;
 use crate::rtc::sealed::Instance;
 
 #[allow(dead_code)]
-#[repr(u8)]
-#[derive(Clone, Copy, Debug)]
-pub(crate) enum WakeupPrescaler {
-    Div2 = 2,
-    Div4 = 4,
-    Div8 = 8,
-    Div16 = 16,
-}
-
-#[cfg(any(stm32wb, stm32f4, stm32l0))]
-impl From<WakeupPrescaler> for crate::pac::rtc::vals::Wucksel {
-    fn from(val: WakeupPrescaler) -> Self {
-        use crate::pac::rtc::vals::Wucksel;
-
-        match val {
-            WakeupPrescaler::Div2 => Wucksel::DIV2,
-            WakeupPrescaler::Div4 => Wucksel::DIV4,
-            WakeupPrescaler::Div8 => Wucksel::DIV8,
-            WakeupPrescaler::Div16 => Wucksel::DIV16,
-        }
-    }
-}
-
-#[cfg(any(stm32wb, stm32f4, stm32l0))]
-impl From<crate::pac::rtc::vals::Wucksel> for WakeupPrescaler {
-    fn from(val: crate::pac::rtc::vals::Wucksel) -> Self {
-        use crate::pac::rtc::vals::Wucksel;
-
-        match val {
-            Wucksel::DIV2 => WakeupPrescaler::Div2,
-            Wucksel::DIV4 => WakeupPrescaler::Div4,
-            Wucksel::DIV8 => WakeupPrescaler::Div8,
-            Wucksel::DIV16 => WakeupPrescaler::Div16,
-            _ => unreachable!(),
-        }
-    }
-}
-
-#[allow(dead_code)]
-impl WakeupPrescaler {
-    pub fn compute_min(val: u32) -> Self {
-        *[
-            WakeupPrescaler::Div2,
-            WakeupPrescaler::Div4,
-            WakeupPrescaler::Div8,
-            WakeupPrescaler::Div16,
-        ]
-        .iter()
-        .skip_while(|psc| **psc as u32 <= val)
-        .next()
-        .unwrap_or(&WakeupPrescaler::Div16)
-    }
-}
-
 impl super::Rtc {
-    #[cfg(feature = "low-power")]
-    /// start the wakeup alarm and wtih a duration that is as close to but less than
-    /// the requested duration, and record the instant the wakeup alarm was started
-    pub(crate) fn start_wakeup_alarm(
-        &self,
-        requested_duration: embassy_time::Duration,
-        cs: critical_section::CriticalSection,
-    ) {
-        use embassy_time::{Duration, TICK_HZ};
-
-        // Panic if the rcc mod knows we're not using low-power rtc
-        #[cfg(any(rcc_wb, rcc_f4, rcc_f410))]
-        unsafe { crate::rcc::get_freqs() }.rtc.unwrap();
-
-        let requested_duration = requested_duration.as_ticks().clamp(0, u32::MAX as u64);
-        let rtc_hz = Self::frequency().0 as u64;
-        let rtc_ticks = requested_duration * rtc_hz / TICK_HZ;
-        let prescaler = WakeupPrescaler::compute_min((rtc_ticks / u16::MAX as u64) as u32);
-
-        // adjust the rtc ticks to the prescaler and subtract one rtc tick
-        let rtc_ticks = rtc_ticks / prescaler as u64;
-        let rtc_ticks = rtc_ticks.clamp(0, (u16::MAX - 1) as u64).saturating_sub(1) as u16;
-
-        self.write(false, |regs| {
-            regs.cr().modify(|w| w.set_wute(false));
-            regs.isr().modify(|w| w.set_wutf(false));
-            while !regs.isr().read().wutwf() {}
-
-            regs.cr().modify(|w| w.set_wucksel(prescaler.into()));
-            regs.wutr().write(|w| w.set_wut(rtc_ticks));
-            regs.cr().modify(|w| w.set_wute(true));
-            regs.cr().modify(|w| w.set_wutie(true));
-        });
-
-        let instant = self.instant().unwrap();
-        trace!(
-            "rtc: start wakeup alarm for {} ms (psc: {}, ticks: {}) at {}",
-            Duration::from_ticks(rtc_ticks as u64 * TICK_HZ * prescaler as u64 / rtc_hz).as_millis(),
-            prescaler as u32,
-            rtc_ticks,
-            instant,
-        );
-
-        assert!(self.stop_time.borrow(cs).replace(Some(instant)).is_none())
-    }
-
-    #[cfg(feature = "low-power")]
-    /// stop the wakeup alarm and return the time elapsed since `start_wakeup_alarm`
-    /// was called, otherwise none
-    pub(crate) fn stop_wakeup_alarm(&self, cs: critical_section::CriticalSection) -> Option<embassy_time::Duration> {
-        use crate::interrupt::typelevel::Interrupt;
-
-        let instant = self.instant().unwrap();
-        if RTC::regs().cr().read().wute() {
-            trace!("rtc: stop wakeup alarm at {}", instant);
-
-            self.write(false, |regs| {
-                regs.cr().modify(|w| w.set_wutie(false));
-                regs.cr().modify(|w| w.set_wute(false));
-                regs.isr().modify(|w| w.set_wutf(false));
-
-                crate::pac::EXTI
-                    .pr(0)
-                    .modify(|w| w.set_line(RTC::EXTI_WAKEUP_LINE, true));
-
-                <RTC as crate::rtc::sealed::Instance>::WakeupInterrupt::unpend();
-            });
-        }
-
-        self.stop_time.borrow(cs).take().map(|stop_time| instant - stop_time)
-    }
-
-    #[cfg(feature = "low-power")]
-    pub(crate) fn enable_wakeup_line(&self) {
-        use crate::interrupt::typelevel::Interrupt;
-        use crate::pac::EXTI;
-
-        <RTC as crate::rtc::sealed::Instance>::WakeupInterrupt::unpend();
-        unsafe { <RTC as crate::rtc::sealed::Instance>::WakeupInterrupt::enable() };
-
-        EXTI.rtsr(0).modify(|w| w.set_line(RTC::EXTI_WAKEUP_LINE, true));
-        EXTI.imr(0).modify(|w| w.set_line(RTC::EXTI_WAKEUP_LINE, true));
-    }
-
     /// Applies the RTC config
     /// It this changes the RTC clock source the time will be reset
     pub(super) fn configure(&mut self, async_psc: u8, sync_psc: u16) {

embassy-stm32/src/rtc/v3.rs

@@ -95,7 +95,7 @@ impl super::Rtc {
         })
     }
 
-    pub(super) fn write<F, R>(&mut self, init_mode: bool, f: F) -> R
+    pub(super) fn write<F, R>(&self, init_mode: bool, f: F) -> R
     where
         F: FnOnce(&crate::pac::rtc::Rtc) -> R,
     {
@@ -129,6 +129,12 @@ impl super::Rtc {
 impl sealed::Instance for crate::peripherals::RTC {
     const BACKUP_REGISTER_COUNT: usize = 32;
 
+    #[cfg(all(feature = "low-power", stm32g4))]
+    const EXTI_WAKEUP_LINE: usize = 20;
+
+    #[cfg(all(feature = "low-power", stm32g4))]
+    type WakeupInterrupt = crate::interrupt::typelevel::RTC_WKUP;
+
     fn read_backup_register(_rtc: &Rtc, register: usize) -> Option<u32> {
         #[allow(clippy::if_same_then_else)]
         if register < Self::BACKUP_REGISTER_COUNT {

embassy-sync/Cargo.toml

@@ -33,7 +33,7 @@ log = { version = "0.4.14", optional = true }
 
 futures-util = { version = "0.3.17", default-features = false }
 critical-section = "1.1"
-heapless = "0.7.5"
+heapless = "0.8"
 cfg-if = "1.0.0"
 embedded-io-async = { version = "0.6.0", optional = true }
 

embassy-time/Cargo.toml

@@ -248,7 +248,7 @@ embedded-hal-async = { version = "=1.0.0-rc.1", optional = true}
 futures-util = { version = "0.3.17", default-features = false }
 critical-section = "1.1"
 cfg-if = "1.0.0"
-heapless = "0.7"
+heapless = "0.8"
 
 # WASM dependencies
 wasm-bindgen = { version = "0.2.81", optional = true }
@@ -258,4 +258,4 @@ wasm-timer = { version = "0.2.5", optional = true }
 [dev-dependencies]
 serial_test = "0.9"
 critical-section = { version = "1.1", features = ["std"] }
-embassy-executor = { version = "0.3.1", path = "../embassy-executor", features = ["nightly"] }
+embassy-executor = { version = "0.3.3", path = "../embassy-executor", features = ["nightly"] }

embassy-usb/Cargo.toml

@@ -45,7 +45,7 @@ embassy-net-driver-channel = { version = "0.2.0", path = "../embassy-net-driver-
 
 defmt = { version = "0.3", optional = true }
 log = { version = "0.4.14", optional = true }
-heapless = "0.7.10"
+heapless = "0.8"
 
 # for HID
 usbd-hid = { version = "0.6.0", optional = true }

examples/boot/application/nrf/Cargo.toml

@@ -6,7 +6,7 @@ license = "MIT OR Apache-2.0"
 
 [dependencies]
 embassy-sync = { version = "0.4.0", path = "../../../../embassy-sync" }
-embassy-executor = { version = "0.3.1", path = "../../../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "nightly", "integrated-timers", "arch-cortex-m", "executor-thread"] }
+embassy-executor = { version = "0.3.3", path = "../../../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "nightly", "integrated-timers", "arch-cortex-m", "executor-thread"] }
 embassy-time = { version = "0.1.5", path = "../../../../embassy-time", features = ["nightly"] }
 embassy-nrf = { version = "0.1.0", path = "../../../../embassy-nrf", features = ["time-driver-rtc1", "gpiote", "nightly"] }
 embassy-boot = { version = "0.1.0", path = "../../../../embassy-boot/boot", features = ["nightly"] }

examples/boot/application/rp/Cargo.toml

@@ -6,7 +6,7 @@ license = "MIT OR Apache-2.0"
 
 [dependencies]
 embassy-sync = { version = "0.4.0", path = "../../../../embassy-sync" }
-embassy-executor = { version = "0.3.1", path = "../../../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "nightly", "integrated-timers", "arch-cortex-m", "executor-thread"] }
+embassy-executor = { version = "0.3.3", path = "../../../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "nightly", "integrated-timers", "arch-cortex-m", "executor-thread"] }
 embassy-time = { version = "0.1.5", path = "../../../../embassy-time", features = ["nightly"] }
 embassy-rp = { version = "0.1.0", path = "../../../../embassy-rp", features = ["time-driver", "unstable-traits", "nightly"] }
 embassy-boot-rp = { version = "0.1.0", path = "../../../../embassy-boot/rp", features = ["nightly"] }

examples/boot/application/stm32f3/Cargo.toml

@@ -6,7 +6,7 @@ license = "MIT OR Apache-2.0"
 
 [dependencies]
 embassy-sync = { version = "0.4.0", path = "../../../../embassy-sync" }
-embassy-executor = { version = "0.3.1", path = "../../../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "nightly", "integrated-timers"] }
+embassy-executor = { version = "0.3.3", path = "../../../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "nightly", "integrated-timers"] }
 embassy-time = { version = "0.1.5", path = "../../../../embassy-time", features = ["nightly", "tick-hz-32_768"] }
 embassy-stm32 = { version = "0.1.0", path = "../../../../embassy-stm32", features = ["unstable-traits", "nightly", "stm32f303re", "time-driver-any", "exti"]  }
 embassy-boot-stm32 = { version = "0.1.0", path = "../../../../embassy-boot/stm32", features = ["nightly"] }

examples/boot/application/stm32f7/Cargo.toml

@@ -6,7 +6,7 @@ license = "MIT OR Apache-2.0"
 
 [dependencies]
 embassy-sync = { version = "0.4.0", path = "../../../../embassy-sync" }
-embassy-executor = { version = "0.3.1", path = "../../../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "nightly", "integrated-timers"] }
+embassy-executor = { version = "0.3.3", path = "../../../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "nightly", "integrated-timers"] }
 embassy-time = { version = "0.1.5", path = "../../../../embassy-time", features = ["nightly", "tick-hz-32_768"] }
 embassy-stm32 = { version = "0.1.0", path = "../../../../embassy-stm32", features = ["unstable-traits", "nightly", "stm32f767zi", "time-driver-any", "exti"]  }
 embassy-boot-stm32 = { version = "0.1.0", path = "../../../../embassy-boot/stm32", features = ["nightly"] }

examples/boot/application/stm32h7/Cargo.toml

@@ -6,7 +6,7 @@ license = "MIT OR Apache-2.0"
 
 [dependencies]
 embassy-sync = { version = "0.4.0", path = "../../../../embassy-sync" }
-embassy-executor = { version = "0.3.1", path = "../../../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "nightly", "integrated-timers"] }
+embassy-executor = { version = "0.3.3", path = "../../../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "nightly", "integrated-timers"] }
 embassy-time = { version = "0.1.5", path = "../../../../embassy-time", features = ["nightly", "tick-hz-32_768"] }
 embassy-stm32 = { version = "0.1.0", path = "../../../../embassy-stm32", features = ["unstable-traits", "nightly", "stm32h743zi", "time-driver-any", "exti"]  }
 embassy-boot-stm32 = { version = "0.1.0", path = "../../../../embassy-boot/stm32", features = ["nightly"] }

examples/boot/application/stm32l0/Cargo.toml

@@ -6,7 +6,7 @@ license = "MIT OR Apache-2.0"
 
 [dependencies]
 embassy-sync = { version = "0.4.0", path = "../../../../embassy-sync" }
-embassy-executor = { version = "0.3.1", path = "../../../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "nightly", "integrated-timers"] }
+embassy-executor = { version = "0.3.3", path = "../../../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "nightly", "integrated-timers"] }
 embassy-time = { version = "0.1.5", path = "../../../../embassy-time", features = ["nightly", "tick-hz-32_768"] }
 embassy-stm32 = { version = "0.1.0", path = "../../../../embassy-stm32", features = ["unstable-traits", "nightly", "stm32l072cz", "time-driver-any", "exti", "memory-x"]  }
 embassy-boot-stm32 = { version = "0.1.0", path = "../../../../embassy-boot/stm32", features = ["nightly"] }

examples/boot/application/stm32l1/Cargo.toml

@@ -6,7 +6,7 @@ license = "MIT OR Apache-2.0"
 
 [dependencies]
 embassy-sync = { version = "0.4.0", path = "../../../../embassy-sync" }
-embassy-executor = { version = "0.3.1", path = "../../../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "nightly", "integrated-timers"] }
+embassy-executor = { version = "0.3.3", path = "../../../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "nightly", "integrated-timers"] }
 embassy-time = { version = "0.1.5", path = "../../../../embassy-time", features = ["nightly", "tick-hz-32_768"] }
 embassy-stm32 = { version = "0.1.0", path = "../../../../embassy-stm32", features = ["unstable-traits", "nightly", "stm32l151cb-a", "time-driver-any", "exti"]  }
 embassy-boot-stm32 = { version = "0.1.0", path = "../../../../embassy-boot/stm32", features = ["nightly"] }

examples/boot/application/stm32l4/Cargo.toml

@@ -6,7 +6,7 @@ license = "MIT OR Apache-2.0"
 
 [dependencies]
 embassy-sync = { version = "0.4.0", path = "../../../../embassy-sync" }
-embassy-executor = { version = "0.3.1", path = "../../../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "nightly", "integrated-timers"] }
+embassy-executor = { version = "0.3.3", path = "../../../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "nightly", "integrated-timers"] }
 embassy-time = { version = "0.1.5", path = "../../../../embassy-time", features = ["nightly", "tick-hz-32_768"] }
 embassy-stm32 = { version = "0.1.0", path = "../../../../embassy-stm32", features = ["unstable-traits", "nightly", "stm32l475vg", "time-driver-any", "exti"]  }
 embassy-boot-stm32 = { version = "0.1.0", path = "../../../../embassy-boot/stm32", features = ["nightly"] }

examples/boot/application/stm32wl/Cargo.toml

@@ -6,7 +6,7 @@ license = "MIT OR Apache-2.0"
 
 [dependencies]
 embassy-sync = { version = "0.4.0", path = "../../../../embassy-sync" }
-embassy-executor = { version = "0.3.1", path = "../../../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "nightly", "integrated-timers"] }
+embassy-executor = { version = "0.3.3", path = "../../../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "nightly", "integrated-timers"] }
 embassy-time = { version = "0.1.5", path = "../../../../embassy-time", features = ["nightly", "tick-hz-32_768"] }
 embassy-stm32 = { version = "0.1.0", path = "../../../../embassy-stm32", features = ["unstable-traits", "nightly", "stm32wl55jc-cm4", "time-driver-any", "exti"]  }
 embassy-boot-stm32 = { version = "0.1.0", path = "../../../../embassy-boot/stm32", features = ["nightly"] }

examples/nrf-rtos-trace/Cargo.toml

@@ -17,7 +17,7 @@ log = [
 
 [dependencies]
 embassy-sync = { version = "0.4.0", path = "../../embassy-sync" }
-embassy-executor = { version = "0.3.1", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "rtos-trace", "rtos-trace-interrupt", "integrated-timers"] }
+embassy-executor = { version = "0.3.3", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "rtos-trace", "rtos-trace-interrupt", "integrated-timers"] }
 embassy-time = { version = "0.1.5", path = "../../embassy-time" }
 embassy-nrf = { version = "0.1.0", path = "../../embassy-nrf", features = ["nrf52840", "time-driver-rtc1", "gpiote", "unstable-pac"] }
 

examples/nrf52840/Cargo.toml

@@ -30,7 +30,7 @@ nightly = [
 [dependencies]
 embassy-futures = { version = "0.1.0", path = "../../embassy-futures" }
 embassy-sync = { version = "0.4.0", path = "../../embassy-sync", features = ["defmt"] }
-embassy-executor = { version = "0.3.1", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "executor-interrupt", "defmt", "integrated-timers"] }
+embassy-executor = { version = "0.3.3", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "executor-interrupt", "defmt", "integrated-timers"] }
 embassy-time = { version = "0.1.5", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime"] }
 embassy-nrf = { version = "0.1.0", path = "../../embassy-nrf", features = ["defmt", "nrf52840", "time-driver-rtc1", "gpiote", "unstable-pac", "time"] }
 embassy-net = { version = "0.2.0", path = "../../embassy-net", features = ["defmt", "tcp", "dhcpv4", "medium-ethernet"], optional = true }

examples/nrf5340/Cargo.toml

@@ -9,7 +9,7 @@ embassy-futures = { version = "0.1.0", path = "../../embassy-futures" }
 embassy-sync = { version = "0.4.0", path = "../../embassy-sync", features = [
     "defmt",
 ] }
-embassy-executor = { version = "0.3.1", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", 
+embassy-executor = { version = "0.3.3", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", 
     "nightly",
     "defmt",
     "integrated-timers",

examples/rp/Cargo.toml

@@ -8,7 +8,7 @@ license = "MIT OR Apache-2.0"
 [dependencies]
 embassy-embedded-hal = { version = "0.1.0", path = "../../embassy-embedded-hal", features = ["defmt"] }
 embassy-sync = { version = "0.4.0", path = "../../embassy-sync", features = ["defmt"] }
-embassy-executor = { version = "0.3.1", path = "../../embassy-executor", features = ["nightly", "arch-cortex-m", "executor-thread", "executor-interrupt", "defmt", "integrated-timers"] }
+embassy-executor = { version = "0.3.3", path = "../../embassy-executor", features = ["nightly", "arch-cortex-m", "executor-thread", "executor-interrupt", "defmt", "integrated-timers"] }
 embassy-time = { version = "0.1.5", path = "../../embassy-time", features = ["nightly", "unstable-traits", "defmt", "defmt-timestamp-uptime"] }
 embassy-rp = { version = "0.1.0", path = "../../embassy-rp", features = ["defmt", "unstable-traits", "nightly", "unstable-pac", "time-driver", "critical-section-impl"] }
 embassy-usb = { version = "0.1.0", path = "../../embassy-usb", features = ["defmt"] }
@@ -39,7 +39,7 @@ st7789 = "0.6.1"
 display-interface = "0.4.1"
 byte-slice-cast = { version = "1.2.0", default-features = false }
 smart-leds = "0.3.0"
-heapless = "0.7.15"
+heapless = "0.8"
 usbd-hid = "0.6.1"
 
 embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-rc.1" }

examples/std/Cargo.toml

@@ -6,7 +6,7 @@ license = "MIT OR Apache-2.0"
 
 [dependencies]
 embassy-sync = { version = "0.4.0", path = "../../embassy-sync", features = ["log"] }
-embassy-executor = { version = "0.3.1", path = "../../embassy-executor", features = ["arch-std", "executor-thread", "log", "nightly", "integrated-timers"] }
+embassy-executor = { version = "0.3.3", path = "../../embassy-executor", features = ["arch-std", "executor-thread", "log", "nightly", "integrated-timers"] }
 embassy-time = { version = "0.1.5", path = "../../embassy-time", features = ["log", "std", "nightly"] }
 embassy-net = { version = "0.2.0", path = "../../embassy-net", features=[ "std", "nightly", "log", "medium-ethernet", "medium-ip", "tcp", "udp", "dns", "dhcpv4", "proto-ipv6"] }
 embassy-net-tuntap = { version = "0.1.0", path = "../../embassy-net-tuntap" }
@@ -14,7 +14,6 @@ embassy-net-ppp = { version = "0.1.0", path = "../../embassy-net-ppp", features
 embedded-io-async = { version = "0.6.0" }
 embedded-io-adapters = { version = "0.6.0", features = ["futures-03"] }
 critical-section = { version = "1.1", features = ["std"] }
-smoltcp = { version = "0.10.0", features = ["dns-max-server-count-4"] }
 
 async-io = "1.6.0"
 env_logger = "0.9.0"
@@ -23,7 +22,7 @@ log = "0.4.14"
 nix = "0.26.2"
 clap = { version = "3.0.0-beta.5", features = ["derive"] }
 rand_core = { version = "0.6.3", features = ["std"] }
-heapless = { version = "0.7.5", default-features = false }
+heapless = { version = "0.8", default-features = false }
 static_cell = { version = "2", features = ["nightly"]}
 
 [profile.release]

examples/stm32c0/Cargo.toml

@@ -8,7 +8,7 @@ license = "MIT OR Apache-2.0"
 # Change stm32c031c6 to your chip name, if necessary.
 embassy-stm32 = { version = "0.1.0", path = "../../embassy-stm32", features = ["nightly", "defmt", "time-driver-any", "stm32c031c6", "memory-x", "unstable-pac", "exti"]  }
 embassy-sync = { version = "0.4.0", path = "../../embassy-sync", features = ["defmt"] }
-embassy-executor = { version = "0.3.1", path = "../../embassy-executor", features = ["nightly", "arch-cortex-m", "executor-thread", "defmt", "integrated-timers"] }
+embassy-executor = { version = "0.3.3", path = "../../embassy-executor", features = ["nightly", "arch-cortex-m", "executor-thread", "defmt", "integrated-timers"] }
 embassy-time = { version = "0.1.5", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
 
 defmt = "0.3"
@@ -19,7 +19,7 @@ cortex-m-rt = "0.7.0"
 embedded-hal = "0.2.6"
 panic-probe = { version = "0.3", features = ["print-defmt"] }
 futures = { version = "0.3.17", default-features = false, features = ["async-await"] }
-heapless = { version = "0.7.5", default-features = false }
+heapless = { version = "0.8", default-features = false }
 
 [profile.release]
 debug = 2

examples/stm32f0/Cargo.toml

@@ -15,7 +15,7 @@ defmt = "0.3"
 defmt-rtt = "0.4"
 panic-probe = "0.3"
 embassy-sync = { version = "0.4.0", path = "../../embassy-sync", features = ["defmt"] }
-embassy-executor = { version = "0.3.1", path = "../../embassy-executor", features = ["nightly", "arch-cortex-m", "executor-thread", "executor-interrupt", "defmt", "integrated-timers"] }
+embassy-executor = { version = "0.3.3", path = "../../embassy-executor", features = ["nightly", "arch-cortex-m", "executor-thread", "executor-interrupt", "defmt", "integrated-timers"] }
 embassy-time = { version = "0.1.5", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
 static_cell = { version = "2", features = ["nightly"]}
 portable-atomic = { version = "1.5", features = ["unsafe-assume-single-core"] }

examples/stm32f1/Cargo.toml

@@ -8,7 +8,7 @@ license = "MIT OR Apache-2.0"
 # Change stm32f103c8 to your chip name, if necessary.
 embassy-stm32 = { version = "0.1.0", path = "../../embassy-stm32", features = ["nightly", "defmt", "stm32f103c8", "unstable-pac", "memory-x", "time-driver-any", "unstable-traits" ]  }
 embassy-sync = { version = "0.4.0", path = "../../embassy-sync", features = ["defmt"] }
-embassy-executor = { version = "0.3.1", path = "../../embassy-executor", features = ["nightly", "arch-cortex-m", "executor-thread", "defmt", "integrated-timers"] }
+embassy-executor = { version = "0.3.3", path = "../../embassy-executor", features = ["nightly", "arch-cortex-m", "executor-thread", "defmt", "integrated-timers"] }
 embassy-time = { version = "0.1.5", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
 embassy-usb = { version = "0.1.0", path = "../../embassy-usb", features = ["defmt"] }
 embassy-futures = { version = "0.1.0", path = "../../embassy-futures" }
@@ -21,7 +21,7 @@ cortex-m-rt = "0.7.0"
 embedded-hal = "0.2.6"
 panic-probe = { version = "0.3", features = ["print-defmt"] }
 futures = { version = "0.3.17", default-features = false, features = ["async-await"] }
-heapless = { version = "0.7.5", default-features = false }
+heapless = { version = "0.8", default-features = false }
 nb = "1.0.0"
 
 [profile.dev]

examples/stm32f2/Cargo.toml

@@ -8,7 +8,7 @@ license = "MIT OR Apache-2.0"
 # Change stm32f207zg to your chip name, if necessary.
 embassy-stm32 = { version = "0.1.0", path = "../../embassy-stm32", features = ["nightly", "defmt", "stm32f207zg", "unstable-pac", "memory-x", "time-driver-any", "exti"]  }
 embassy-sync = { version = "0.4.0", path = "../../embassy-sync", features = ["defmt"] }
-embassy-executor = { version = "0.3.1", path = "../../embassy-executor", features = ["nightly", "arch-cortex-m", "executor-thread", "defmt", "integrated-timers"] }
+embassy-executor = { version = "0.3.3", path = "../../embassy-executor", features = ["nightly", "arch-cortex-m", "executor-thread", "defmt", "integrated-timers"] }
 embassy-time = { version = "0.1.5", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
 
 defmt = "0.3"
@@ -19,7 +19,7 @@ cortex-m-rt = "0.7.0"
 embedded-hal = "0.2.6"
 panic-probe = { version = "0.3", features = ["print-defmt"] }
 futures = { version = "0.3.17", default-features = false, features = ["async-await"] }
-heapless = { version = "0.7.5", default-features = false }
+heapless = { version = "0.8", default-features = false }
 nb = "1.0.0"
 
 [profile.release]

examples/stm32f2/src/bin/pll.rs

@@ -6,9 +6,6 @@ use core::convert::TryFrom;
 
 use defmt::*;
 use embassy_executor::Spawner;
-use embassy_stm32::rcc::{
-    APBPrescaler, ClockSrc, HSEConfig, HSESrc, PLLConfig, PLLMul, PLLPDiv, PLLPreDiv, PLLQDiv, PLLSrc,
-};
 use embassy_stm32::time::Hertz;
 use embassy_stm32::Config;
 use embassy_time::Timer;
@@ -19,29 +16,35 @@ async fn main(_spawner: Spawner) {
     // Example config for maximum performance on a NUCLEO-F207ZG board
 
     let mut config = Config::default();
+
+    {
+        use embassy_stm32::rcc::*;
+
         // By default, HSE on the board comes from a 8 MHz clock signal (not a crystal)
-    config.rcc.hse = Some(HSEConfig {
+        config.rcc.hse = Some(Hse {
-        frequency: Hertz(8_000_000),
+            freq: Hertz(8_000_000),
-        source: HSESrc::Bypass,
+            mode: HseMode::Bypass,
         });
         // PLL uses HSE as the clock source
-    config.rcc.pll_mux = PLLSrc::HSE;
+        config.rcc.pll_src = PllSource::HSE;
-    config.rcc.pll = PLLConfig {
+        config.rcc.pll = Some(Pll {
             // 8 MHz clock source / 8 = 1 MHz PLL input
-        pre_div: unwrap!(PLLPreDiv::try_from(8)),
+            prediv: unwrap!(PllPreDiv::try_from(8)),
             // 1 MHz PLL input * 240 = 240 MHz PLL VCO
-        mul: unwrap!(PLLMul::try_from(240)),
+            mul: unwrap!(PllMul::try_from(240)),
             // 240 MHz PLL VCO / 2 = 120 MHz main PLL output
-        p_div: PLLPDiv::DIV2,
+            divp: Some(PllPDiv::DIV2),
             // 240 MHz PLL VCO / 5 = 48 MHz PLL48 output
-        q_div: PLLQDiv::DIV5,
+            divq: Some(PllQDiv::DIV5),
-    };
+            divr: None,
+        });
         // System clock comes from PLL (= the 120 MHz main PLL output)
-    config.rcc.mux = ClockSrc::PLL;
+        config.rcc.sys = Sysclk::PLL1_P;
         // 120 MHz / 4 = 30 MHz APB1 frequency
         config.rcc.apb1_pre = APBPrescaler::DIV4;
         // 120 MHz / 2 = 60 MHz APB2 frequency
         config.rcc.apb2_pre = APBPrescaler::DIV2;
+    }
 
     let _p = embassy_stm32::init(config);
 

examples/stm32f3/Cargo.toml

@@ -8,7 +8,7 @@ license = "MIT OR Apache-2.0"
 # Change stm32f303ze to your chip name, if necessary.
 embassy-stm32 = { version = "0.1.0", path = "../../embassy-stm32", features = ["nightly", "defmt", "stm32f303ze", "unstable-pac", "memory-x", "time-driver-any", "exti"]  }
 embassy-sync = { version = "0.4.0", path = "../../embassy-sync", features = ["defmt"] }
-embassy-executor = { version = "0.3.1", path = "../../embassy-executor", features = ["nightly", "arch-cortex-m", "executor-thread", "executor-interrupt", "defmt", "integrated-timers"] }
+embassy-executor = { version = "0.3.3", path = "../../embassy-executor", features = ["nightly", "arch-cortex-m", "executor-thread", "executor-interrupt", "defmt", "integrated-timers"] }
 embassy-time = { version = "0.1.5", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
 embassy-usb = { version = "0.1.0", path = "../../embassy-usb", features = ["defmt"] }
 embassy-futures = { version = "0.1.0", path = "../../embassy-futures" }
@@ -21,7 +21,7 @@ cortex-m-rt = "0.7.0"
 embedded-hal = "0.2.6"
 panic-probe = { version = "0.3", features = ["print-defmt"] }
 futures = { version = "0.3.17", default-features = false, features = ["async-await"] }
-heapless = { version = "0.7.5", default-features = false }
+heapless = { version = "0.8", default-features = false }
 nb = "1.0.0"
 embedded-storage = "0.3.0"
 static_cell = { version = "2", features = ["nightly"]}

examples/stm32f334/Cargo.toml

@@ -6,7 +6,7 @@ license = "MIT OR Apache-2.0"
 
 [dependencies]
 embassy-sync = { version = "0.4.0", path = "../../embassy-sync", features = ["defmt"] }
-embassy-executor = { version = "0.3.1", path = "../../embassy-executor", features = ["nightly", "arch-cortex-m", "executor-thread", "executor-interrupt", "defmt", "integrated-timers"] }
+embassy-executor = { version = "0.3.3", path = "../../embassy-executor", features = ["nightly", "arch-cortex-m", "executor-thread", "executor-interrupt", "defmt", "integrated-timers"] }
 embassy-time = { version = "0.1.0", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
 embassy-stm32 = { version = "0.1.0", path = "../../embassy-stm32", features = ["nightly", "defmt", "stm32f334r8", "unstable-pac", "memory-x", "time-driver-any", "exti"]  }
 embassy-usb = { version = "0.1.0", path = "../../embassy-usb", features = ["defmt"] }
@@ -20,7 +20,7 @@ cortex-m-rt = "0.7.0"
 embedded-hal = "0.2.6"
 panic-probe = { version = "0.3", features = ["print-defmt"] }
 futures = { version = "0.3.17", default-features = false, features = ["async-await"] }
-heapless = { version = "0.7.5", default-features = false }
+heapless = { version = "0.8", default-features = false }
 nb = "1.0.0"
 embedded-storage = "0.3.0"
 static_cell = { version = "2", features = ["nightly"]}

examples/stm32f4/Cargo.toml

@@ -8,7 +8,7 @@ license = "MIT OR Apache-2.0"
 # Change stm32f429zi to your chip name, if necessary.
 embassy-stm32 = { version = "0.1.0", path = "../../embassy-stm32", features = ["nightly", "unstable-traits", "defmt", "stm32f429zi", "unstable-pac", "memory-x", "time-driver-any", "exti", "embedded-sdmmc", "chrono"]  }
 embassy-sync = { version = "0.4.0", path = "../../embassy-sync", features = ["defmt"] }
-embassy-executor = { version = "0.3.1", path = "../../embassy-executor", features = ["nightly", "arch-cortex-m", "executor-thread", "executor-interrupt", "defmt", "integrated-timers"] }
+embassy-executor = { version = "0.3.3", path = "../../embassy-executor", features = ["nightly", "arch-cortex-m", "executor-thread", "executor-interrupt", "defmt", "integrated-timers"] }
 embassy-time = { version = "0.1.5", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "unstable-traits", "tick-hz-32_768"] }
 embassy-usb = { version = "0.1.0", path = "../../embassy-usb", features = ["defmt" ] }
 embassy-net = { version = "0.2.0", path = "../../embassy-net", features = ["defmt", "tcp", "dhcpv4", "medium-ethernet", "nightly"] }
@@ -23,7 +23,7 @@ embedded-io = { version = "0.6.0" }
 embedded-io-async = { version = "0.6.0" }
 panic-probe = { version = "0.3", features = ["print-defmt"] }
 futures = { version = "0.3.17", default-features = false, features = ["async-await"] }
-heapless = { version = "0.7.5", default-features = false }
+heapless = { version = "0.8", default-features = false }
 nb = "1.0.0"
 embedded-storage = "0.3.0"
 micromath = "2.0.0"

examples/stm32f4/src/bin/eth.rs

@@ -42,7 +42,7 @@ async fn main(spawner: Spawner) -> ! {
         config.rcc.pll = Some(Pll {
             prediv: PllPreDiv::DIV4,
             mul: PllMul::MUL180,
-            divp: Some(Pllp::DIV2), // 8mhz / 4 * 180 / 2 = 180Mhz.
+            divp: Some(PllPDiv::DIV2), // 8mhz / 4 * 180 / 2 = 180Mhz.
             divq: None,
             divr: None,
         });

examples/stm32f4/src/bin/sdmmc.rs

@@ -30,8 +30,8 @@ async fn main(_spawner: Spawner) {
         config.rcc.pll = Some(Pll {
             prediv: PllPreDiv::DIV4,
             mul: PllMul::MUL168,
-            divp: Some(Pllp::DIV2), // 8mhz / 4 * 168 / 2 = 168Mhz.
+            divp: Some(PllPDiv::DIV2), // 8mhz / 4 * 168 / 2 = 168Mhz.
-            divq: Some(Pllq::DIV7), // 8mhz / 4 * 168 / 7 = 48Mhz.
+            divq: Some(PllQDiv::DIV7), // 8mhz / 4 * 168 / 7 = 48Mhz.
             divr: None,
         });
         config.rcc.ahb_pre = AHBPrescaler::DIV1;

examples/stm32f4/src/bin/usb_ethernet.rs

@@ -56,8 +56,8 @@ async fn main(spawner: Spawner) {
         config.rcc.pll = Some(Pll {
             prediv: PllPreDiv::DIV4,
             mul: PllMul::MUL168,
-            divp: Some(Pllp::DIV2), // 8mhz / 4 * 168 / 2 = 168Mhz.
+            divp: Some(PllPDiv::DIV2), // 8mhz / 4 * 168 / 2 = 168Mhz.
-            divq: Some(Pllq::DIV7), // 8mhz / 4 * 168 / 7 = 48Mhz.
+            divq: Some(PllQDiv::DIV7), // 8mhz / 4 * 168 / 7 = 48Mhz.
             divr: None,
         });
         config.rcc.ahb_pre = AHBPrescaler::DIV1;

examples/stm32f4/src/bin/usb_raw.rs

@@ -85,8 +85,8 @@ async fn main(_spawner: Spawner) {
         config.rcc.pll = Some(Pll {
             prediv: PllPreDiv::DIV4,
             mul: PllMul::MUL168,
-            divp: Some(Pllp::DIV2), // 8mhz / 4 * 168 / 2 = 168Mhz.
+            divp: Some(PllPDiv::DIV2), // 8mhz / 4 * 168 / 2 = 168Mhz.
-            divq: Some(Pllq::DIV7), // 8mhz / 4 * 168 / 7 = 48Mhz.
+            divq: Some(PllQDiv::DIV7), // 8mhz / 4 * 168 / 7 = 48Mhz.
             divr: None,
         });
         config.rcc.ahb_pre = AHBPrescaler::DIV1;

examples/stm32f4/src/bin/usb_serial.rs

@@ -32,8 +32,8 @@ async fn main(_spawner: Spawner) {
         config.rcc.pll = Some(Pll {
             prediv: PllPreDiv::DIV4,
             mul: PllMul::MUL168,
-            divp: Some(Pllp::DIV2), // 8mhz / 4 * 168 / 2 = 168Mhz.
+            divp: Some(PllPDiv::DIV2), // 8mhz / 4 * 168 / 2 = 168Mhz.
-            divq: Some(Pllq::DIV7), // 8mhz / 4 * 168 / 7 = 48Mhz.
+            divq: Some(PllQDiv::DIV7), // 8mhz / 4 * 168 / 7 = 48Mhz.
             divr: None,
         });
         config.rcc.ahb_pre = AHBPrescaler::DIV1;

examples/stm32f7/Cargo.toml

@@ -8,7 +8,7 @@ license = "MIT OR Apache-2.0"
 # Change stm32f767zi to your chip name, if necessary.
 embassy-stm32 = { version = "0.1.0", path = "../../embassy-stm32", features = ["nightly", "defmt", "stm32f767zi", "memory-x", "unstable-pac", "time-driver-any", "exti"]  }
 embassy-sync = { version = "0.4.0", path = "../../embassy-sync", features = ["defmt"] }
-embassy-executor = { version = "0.3.1", path = "../../embassy-executor", features = ["nightly", "arch-cortex-m", "executor-thread", "defmt", "integrated-timers"] }
+embassy-executor = { version = "0.3.3", path = "../../embassy-executor", features = ["nightly", "arch-cortex-m", "executor-thread", "defmt", "integrated-timers"] }
 embassy-time = { version = "0.1.5", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
 embassy-net = { version = "0.2.0", path = "../../embassy-net", features = ["defmt", "nightly", "tcp", "dhcpv4", "medium-ethernet"] }
 embedded-io-async = { version = "0.6.0" }
@@ -22,7 +22,7 @@ cortex-m-rt = "0.7.0"
 embedded-hal = "0.2.6"
 panic-probe = { version = "0.3", features = ["print-defmt"] }
 futures = { version = "0.3.17", default-features = false, features = ["async-await"] }
-heapless = { version = "0.7.5", default-features = false }
+heapless = { version = "0.8", default-features = false }
 nb = "1.0.0"
 rand_core = "0.6.3"
 critical-section = "1.1"

examples/stm32f7/src/bin/eth.rs

@@ -43,7 +43,7 @@ async fn main(spawner: Spawner) -> ! {
         config.rcc.pll = Some(Pll {
             prediv: PllPreDiv::DIV4,
             mul: PllMul::MUL216,
-            divp: Some(Pllp::DIV2), // 8mhz / 4 * 216 / 2 = 216Mhz
+            divp: Some(PllPDiv::DIV2), // 8mhz / 4 * 216 / 2 = 216Mhz
             divq: None,
             divr: None,
         });

examples/stm32f7/src/bin/sdmmc.rs

@@ -26,8 +26,8 @@ async fn main(_spawner: Spawner) {
         config.rcc.pll = Some(Pll {
             prediv: PllPreDiv::DIV4,
             mul: PllMul::MUL216,
-            divp: Some(Pllp::DIV2), // 8mhz / 4 * 216 / 2 = 216Mhz
+            divp: Some(PllPDiv::DIV2), // 8mhz / 4 * 216 / 2 = 216Mhz
-            divq: Some(Pllq::DIV9), // 8mhz / 4 * 216 / 9 = 48Mhz
+            divq: Some(PllQDiv::DIV9), // 8mhz / 4 * 216 / 9 = 48Mhz
             divr: None,
         });
         config.rcc.ahb_pre = AHBPrescaler::DIV1;

examples/stm32f7/src/bin/usb_serial.rs

@@ -32,8 +32,8 @@ async fn main(_spawner: Spawner) {
         config.rcc.pll = Some(Pll {
             prediv: PllPreDiv::DIV4,
             mul: PllMul::MUL216,
-            divp: Some(Pllp::DIV2), // 8mhz / 4 * 216 / 2 = 216Mhz
+            divp: Some(PllPDiv::DIV2), // 8mhz / 4 * 216 / 2 = 216Mhz
-            divq: Some(Pllq::DIV9), // 8mhz / 4 * 216 / 9 = 48Mhz
+            divq: Some(PllQDiv::DIV9), // 8mhz / 4 * 216 / 9 = 48Mhz
             divr: None,
         });
         config.rcc.ahb_pre = AHBPrescaler::DIV1;

examples/stm32g0/Cargo.toml

@@ -8,7 +8,7 @@ license = "MIT OR Apache-2.0"
 # Change stm32g071rb to your chip name, if necessary.
 embassy-stm32 = { version = "0.1.0", path = "../../embassy-stm32", features = ["nightly", "defmt", "time-driver-any", "stm32g071rb", "memory-x", "unstable-pac", "exti"]  }
 embassy-sync = { version = "0.4.0", path = "../../embassy-sync", features = ["defmt"] }
-embassy-executor = { version = "0.3.1", path = "../../embassy-executor", features = ["nightly", "arch-cortex-m", "executor-thread", "defmt", "integrated-timers"] }
+embassy-executor = { version = "0.3.3", path = "../../embassy-executor", features = ["nightly", "arch-cortex-m", "executor-thread", "defmt", "integrated-timers"] }
 embassy-time = { version = "0.1.5", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
 
 defmt = "0.3"
@@ -19,7 +19,7 @@ cortex-m-rt = "0.7.0"
 embedded-hal = "0.2.6"
 panic-probe = { version = "0.3", features = ["print-defmt"] }
 futures = { version = "0.3.17", default-features = false, features = ["async-await"] }
-heapless = { version = "0.7.5", default-features = false }
+heapless = { version = "0.8", default-features = false }
 portable-atomic = { version = "1.5", features = ["unsafe-assume-single-core"] }
 
 [profile.release]

examples/stm32g4/Cargo.toml

@@ -8,7 +8,7 @@ license = "MIT OR Apache-2.0"
 # Change stm32g491re to your chip name, if necessary.
 embassy-stm32 = { version = "0.1.0", path = "../../embassy-stm32", features = ["nightly", "defmt", "time-driver-any", "stm32g491re", "memory-x", "unstable-pac", "exti"]  }
 embassy-sync = { version = "0.4.0", path = "../../embassy-sync", features = ["defmt"] }
-embassy-executor = { version = "0.3.1", path = "../../embassy-executor", features = ["nightly", "arch-cortex-m", "executor-thread", "defmt", "integrated-timers"] }
+embassy-executor = { version = "0.3.3", path = "../../embassy-executor", features = ["nightly", "arch-cortex-m", "executor-thread", "defmt", "integrated-timers"] }
 embassy-time = { version = "0.1.5", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
 embassy-usb = { version = "0.1.0", path = "../../embassy-usb", features = ["defmt"] }
 embassy-futures = { version = "0.1.0", path = "../../embassy-futures" }
@@ -22,7 +22,7 @@ cortex-m-rt = "0.7.0"
 embedded-hal = "0.2.6"
 panic-probe = { version = "0.3", features = ["print-defmt"] }
 futures = { version = "0.3.17", default-features = false, features = ["async-await"] }
-heapless = { version = "0.7.5", default-features = false }
+heapless = { version = "0.8", default-features = false }
 
 [profile.release]
 debug = 2

examples/stm32g4/src/bin/adc.rs

@@ -5,7 +5,7 @@
 use defmt::*;
 use embassy_executor::Spawner;
 use embassy_stm32::adc::{Adc, SampleTime};
-use embassy_stm32::rcc::{AdcClockSource, ClockSrc, Pll, PllM, PllN, PllR, PllSrc};
+use embassy_stm32::rcc::{AdcClockSource, ClockSrc, Pll, PllM, PllN, PllR, PllSource};
 use embassy_stm32::Config;
 use embassy_time::{Delay, Timer};
 use {defmt_rtt as _, panic_probe as _};
@@ -15,7 +15,7 @@ async fn main(_spawner: Spawner) {
     let mut config = Config::default();
 
     config.rcc.pll = Some(Pll {
-        source: PllSrc::HSI,
+        source: PllSource::HSI,
         prediv_m: PllM::DIV4,
         mul_n: PllN::MUL85,
         div_p: None,

examples/stm32g4/src/bin/pll.rs

@@ -4,7 +4,7 @@
 
 use defmt::*;
 use embassy_executor::Spawner;
-use embassy_stm32::rcc::{ClockSrc, Pll, PllM, PllN, PllR, PllSrc};
+use embassy_stm32::rcc::{ClockSrc, Pll, PllM, PllN, PllR, PllSource};
 use embassy_stm32::Config;
 use embassy_time::Timer;
 use {defmt_rtt as _, panic_probe as _};
@@ -14,7 +14,7 @@ async fn main(_spawner: Spawner) {
     let mut config = Config::default();
 
     config.rcc.pll = Some(Pll {
-        source: PllSrc::HSI,
+        source: PllSource::HSI,
         prediv_m: PllM::DIV4,
         mul_n: PllN::MUL85,
         div_p: None,

examples/stm32g4/src/bin/usb_serial.rs

@@ -4,7 +4,7 @@
 
 use defmt::{panic, *};
 use embassy_executor::Spawner;
-use embassy_stm32::rcc::{Clock48MhzSrc, ClockSrc, Hsi48Config, Pll, PllM, PllN, PllQ, PllR, PllSrc};
+use embassy_stm32::rcc::{Clock48MhzSrc, ClockSrc, Hsi48Config, Pll, PllM, PllN, PllQ, PllR, PllSource};
 use embassy_stm32::time::Hertz;
 use embassy_stm32::usb::{self, Driver, Instance};
 use embassy_stm32::{bind_interrupts, peripherals, Config};
@@ -25,14 +25,14 @@ async fn main(_spawner: Spawner) {
     // Change this to `false` to use the HSE clock source for the USB. This example assumes an 8MHz HSE.
     const USE_HSI48: bool = true;
 
-    let pllq_div = if USE_HSI48 { None } else { Some(PllQ::DIV6) };
+    let plldivq = if USE_HSI48 { None } else { Some(PllQ::DIV6) };
 
     config.rcc.pll = Some(Pll {
-        source: PllSrc::HSE(Hertz(8_000_000)),
+        source: PllSource::HSE(Hertz(8_000_000)),
         prediv_m: PllM::DIV2,
         mul_n: PllN::MUL72,
         div_p: None,
-        div_q: pllq_div,
+        div_q: plldivq,
         // Main system clock at 144 MHz
         div_r: Some(PllR::DIV2),
     });

examples/stm32h5/Cargo.toml

@@ -8,7 +8,7 @@ license = "MIT OR Apache-2.0"
 # Change stm32h563zi to your chip name, if necessary.
 embassy-stm32 = { version = "0.1.0", path = "../../embassy-stm32", features = ["nightly", "defmt", "stm32h563zi", "memory-x", "time-driver-any", "exti", "unstable-pac", "unstable-traits"] }
 embassy-sync = { version = "0.4.0", path = "../../embassy-sync", features = ["defmt"] }
-embassy-executor = { version = "0.3.1", path = "../../embassy-executor", features = ["nightly", "arch-cortex-m", "executor-thread", "defmt", "integrated-timers"] }
+embassy-executor = { version = "0.3.3", path = "../../embassy-executor", features = ["nightly", "arch-cortex-m", "executor-thread", "defmt", "integrated-timers"] }
 embassy-time = { version = "0.1.5", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "unstable-traits", "tick-hz-32_768"] }
 embassy-net = { version = "0.2.0", path = "../../embassy-net", features = ["defmt", "nightly", "tcp", "dhcpv4", "medium-ethernet", "proto-ipv6"] }
 embedded-io-async = { version = "0.6.0" }
@@ -22,10 +22,10 @@ cortex-m-rt = "0.7.0"
 embedded-hal = "0.2.6"
 embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-rc.1" }
 embedded-hal-async = { version = "=1.0.0-rc.1" }
-embedded-nal-async = { version = "0.6.0" }
+embedded-nal-async = { version = "0.7" }
 panic-probe = { version = "0.3", features = ["print-defmt"] }
 futures = { version = "0.3.17", default-features = false, features = ["async-await"] }
-heapless = { version = "0.7.5", default-features = false }
+heapless = { version = "0.8", default-features = false }
 rand_core = "0.6.3"
 critical-section = "1.1"
 micromath = "2.0.0"

examples/stm32h7/Cargo.toml

@@ -8,9 +8,9 @@ license = "MIT OR Apache-2.0"
 # Change stm32h743bi to your chip name, if necessary.
 embassy-stm32 = { version = "0.1.0", path = "../../embassy-stm32", features = ["nightly", "defmt", "stm32h743bi", "time-driver-any", "exti", "memory-x", "unstable-pac", "unstable-traits", "chrono"] }
 embassy-sync = { version = "0.4.0", path = "../../embassy-sync", features = ["defmt"] }
-embassy-executor = { version = "0.3.1", path = "../../embassy-executor", features = ["nightly", "arch-cortex-m", "executor-thread", "defmt", "integrated-timers"] }
+embassy-executor = { version = "0.3.3", path = "../../embassy-executor", features = ["nightly", "arch-cortex-m", "executor-thread", "defmt", "integrated-timers"] }
 embassy-time = { version = "0.1.5", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "unstable-traits", "tick-hz-32_768"] }
-embassy-net = { version = "0.2.0", path = "../../embassy-net", features = ["defmt", "nightly", "tcp", "dhcpv4", "medium-ethernet", "proto-ipv6"] }
+embassy-net = { version = "0.2.0", path = "../../embassy-net", features = ["defmt", "nightly", "tcp", "dhcpv4", "medium-ethernet", "proto-ipv6", "dns"] }
 embedded-io-async = { version = "0.6.0" }
 embassy-usb = { version = "0.1.0", path = "../../embassy-usb", features = ["defmt"] }
 
@@ -22,10 +22,10 @@ cortex-m-rt = "0.7.0"
 embedded-hal = "0.2.6"
 embedded-hal-1 = { package = "embedded-hal", version = "=1.0.0-rc.1" }
 embedded-hal-async = { version = "=1.0.0-rc.1" }
-embedded-nal-async = { version = "0.6.0" }
+embedded-nal-async = { version = "0.7" }
 panic-probe = { version = "0.3", features = ["print-defmt"] }
 futures = { version = "0.3.17", default-features = false, features = ["async-await"] }
-heapless = { version = "0.7.5", default-features = false }
+heapless = { version = "0.8", default-features = false }
 rand_core = "0.6.3"
 critical-section = "1.1"
 micromath = "2.0.0"

examples/stm32l0/Cargo.toml

@@ -13,7 +13,7 @@ nightly = ["embassy-stm32/nightly", "embassy-time/nightly", "embassy-time/unstab
 # Change stm32l072cz to your chip name, if necessary.
 embassy-stm32 = { version = "0.1.0", path = "../../embassy-stm32", features = ["defmt", "stm32l072cz", "time-driver-any", "exti", "unstable-traits", "memory-x"]  }
 embassy-sync = { version = "0.4.0", path = "../../embassy-sync", features = ["defmt"] }
-embassy-executor = { version = "0.3.1", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "defmt", "integrated-timers"] }
+embassy-executor = { version = "0.3.3", path = "../../embassy-executor", features = ["arch-cortex-m", "executor-thread", "defmt", "integrated-timers"] }
 embassy-time = { version = "0.1.5", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
 embassy-lora = { version = "0.1.0", path = "../../embassy-lora", features = ["time", "defmt"], optional = true }
 lora-phy = { version = "2", optional = true }
@@ -31,7 +31,7 @@ cortex-m = { version = "0.7.6", features = ["inline-asm", "critical-section-sing
 cortex-m-rt = "0.7.0"
 panic-probe = { version = "0.3", features = ["print-defmt"] }
 futures = { version = "0.3.17", default-features = false, features = ["async-await"] }
-heapless = { version = "0.7.5", default-features = false }
+heapless = { version = "0.8", default-features = false }
 embedded-hal = "0.2.6"
 static_cell = { version = "2" }
 portable-atomic = { version = "1.5", features = ["unsafe-assume-single-core"] }

examples/stm32l1/Cargo.toml

@@ -6,7 +6,7 @@ license = "MIT OR Apache-2.0"
 
 [dependencies]
 embassy-sync = { version = "0.4.0", path = "../../embassy-sync", features = ["defmt"] }
-embassy-executor = { version = "0.3.1", path = "../../embassy-executor", features = ["nightly", "arch-cortex-m", "executor-thread", "defmt", "integrated-timers"] }
+embassy-executor = { version = "0.3.3", path = "../../embassy-executor", features = ["nightly", "arch-cortex-m", "executor-thread", "defmt", "integrated-timers"] }
 embassy-time = { version = "0.1.5", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
 embassy-stm32 = { version = "0.1.0", path = "../../embassy-stm32", features = ["nightly", "defmt", "stm32l151cb-a", "time-driver-any", "memory-x"]  }
 
@@ -18,7 +18,7 @@ cortex-m-rt = "0.7.0"
 embedded-hal = "0.2.6"
 panic-probe = { version = "0.3", features = ["print-defmt"] }
 futures = { version = "0.3.17", default-features = false, features = ["async-await"] }
-heapless = { version = "0.7.5", default-features = false }
+heapless = { version = "0.8", default-features = false }
 embedded-storage = "0.3.0"
 
 [profile.release]

examples/stm32l4/Cargo.toml

@@ -8,7 +8,7 @@ license = "MIT OR Apache-2.0"
 # Change stm32l4s5vi to your chip name, if necessary.
 embassy-stm32 = { version = "0.1.0", path = "../../embassy-stm32", features = ["nightly", "defmt", "unstable-pac", "stm32l4s5qi", "memory-x", "time-driver-any", "exti", "unstable-traits", "chrono"]  }
 embassy-sync = { version = "0.4.0", path = "../../embassy-sync", features = ["defmt"] }
-embassy-executor = { version = "0.3.1", path = "../../embassy-executor", features = ["nightly", "arch-cortex-m", "executor-thread", "defmt", "integrated-timers"] }
+embassy-executor = { version = "0.3.3", path = "../../embassy-executor", features = ["nightly", "arch-cortex-m", "executor-thread", "defmt", "integrated-timers"] }
 embassy-time = { version = "0.1.5", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768", "unstable-traits", "nightly"] }
 embassy-embedded-hal = { version = "0.1.0", path = "../../embassy-embedded-hal" }
 embassy-usb = { version = "0.1.0", path = "../../embassy-usb", features = ["defmt"] }
@@ -29,7 +29,7 @@ embedded-hal-async = { version = "=1.0.0-rc.1" }
 embedded-hal-bus = { version = "=0.1.0-rc.1", features = ["async"] }
 panic-probe = { version = "0.3", features = ["print-defmt"] }
 futures = { version = "0.3.17", default-features = false, features = ["async-await"] }
-heapless = { version = "0.7.5", default-features = false }
+heapless = { version = "0.8", default-features = false }
 chrono = { version = "^0.4", default-features = false }
 rand = { version = "0.8.5", default-features = false }
 static_cell = { version = "2", features = ["nightly"]}

examples/stm32l4/src/bin/rng.rs

@@ -4,7 +4,7 @@
 
 use defmt::*;
 use embassy_executor::Spawner;
-use embassy_stm32::rcc::{ClockSrc, PLLSource, Pll, PllMul, PllPreDiv, PllQDiv, PllRDiv};
+use embassy_stm32::rcc::{ClockSrc, Pll, PllMul, PllPreDiv, PllQDiv, PllRDiv, PllSource};
 use embassy_stm32::rng::Rng;
 use embassy_stm32::{bind_interrupts, peripherals, rng, Config};
 use {defmt_rtt as _, panic_probe as _};
@@ -19,7 +19,7 @@ async fn main(_spawner: Spawner) {
     config.rcc.mux = ClockSrc::PLL1_R;
     config.rcc.hsi = true;
     config.rcc.pll = Some(Pll {
-        source: PLLSource::HSI,
+        source: PllSource::HSI,
         prediv: PllPreDiv::DIV1,
         mul: PllMul::MUL18,
         divp: None,

examples/stm32l4/src/bin/rtc.rs

@@ -22,7 +22,7 @@ async fn main(_spawner: Spawner) {
             mode: HseMode::Oscillator,
         });
         config.rcc.pll = Some(Pll {
-            source: PLLSource::HSE,
+            source: PllSource::HSE,
             prediv: PllPreDiv::DIV1,
             mul: PllMul::MUL20,
             divp: None,

examples/stm32l4/src/bin/spe_adin1110_http_server.rs

@@ -75,7 +75,7 @@ async fn main(spawner: Spawner) {
     let mut config = embassy_stm32::Config::default();
     {
         use embassy_stm32::rcc::*;
-        // 80Mhz clock (Source: 8 / SrcDiv: 1 * PLLMul 20 / ClkDiv 2)
+        // 80Mhz clock (Source: 8 / SrcDiv: 1 * PllMul 20 / ClkDiv 2)
         // 80MHz highest frequency for flash 0 wait.
         config.rcc.mux = ClockSrc::PLL1_R;
         config.rcc.hse = Some(Hse {
@@ -83,7 +83,7 @@ async fn main(spawner: Spawner) {
             mode: HseMode::Oscillator,
         });
         config.rcc.pll = Some(Pll {
-            source: PLLSource::HSE,
+            source: PllSource::HSE,
             prediv: PllPreDiv::DIV1,
             mul: PllMul::MUL20,
             divp: None,

examples/stm32l4/src/bin/usb_serial.rs

@@ -27,7 +27,7 @@ async fn main(_spawner: Spawner) {
     config.rcc.mux = ClockSrc::PLL1_R;
     config.rcc.hsi = true;
     config.rcc.pll = Some(Pll {
-        source: PLLSource::HSI,
+        source: PllSource::HSI,
         prediv: PllPreDiv::DIV1,
         mul: PllMul::MUL10,
         divp: None,

examples/stm32l5/Cargo.toml

@@ -8,7 +8,7 @@ license = "MIT OR Apache-2.0"
 # Change stm32l552ze to your chip name, if necessary.
 embassy-stm32 = { version = "0.1.0", path = "../../embassy-stm32", features = ["nightly", "defmt", "unstable-pac", "stm32l552ze", "time-driver-any", "exti", "unstable-traits", "memory-x"]  }
 embassy-sync = { version = "0.4.0", path = "../../embassy-sync", features = ["defmt"] }
-embassy-executor = { version = "0.3.1", path = "../../embassy-executor", features = ["nightly", "arch-cortex-m", "executor-thread", "defmt", "integrated-timers"] }
+embassy-executor = { version = "0.3.3", path = "../../embassy-executor", features = ["nightly", "arch-cortex-m", "executor-thread", "defmt", "integrated-timers"] }
 embassy-time = { version = "0.1.5", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
 embassy-usb = { version = "0.1.0", path = "../../embassy-usb", features = ["defmt"] }
 embassy-net = { version = "0.2.0", path = "../../embassy-net", features = ["defmt", "nightly", "tcp", "dhcpv4", "medium-ethernet"] }
@@ -23,7 +23,7 @@ cortex-m = { version = "0.7.6", features = ["inline-asm", "critical-section-sing
 cortex-m-rt = "0.7.0"
 embedded-hal = "0.2.6"
 futures = { version = "0.3.17", default-features = false, features = ["async-await"] }
-heapless = { version = "0.7.5", default-features = false }
+heapless = { version = "0.8", default-features = false }
 rand_core = { version = "0.6.3", default-features = false }
 embedded-io-async = { version = "0.6.0" }
 static_cell = { version = "2", features = ["nightly"]}

examples/stm32l5/src/bin/rng.rs

@@ -4,7 +4,7 @@
 
 use defmt::*;
 use embassy_executor::Spawner;
-use embassy_stm32::rcc::{ClockSrc, PLLSource, Pll, PllMul, PllPreDiv, PllRDiv};
+use embassy_stm32::rcc::{ClockSrc, Pll, PllMul, PllPreDiv, PllRDiv, PllSource};
 use embassy_stm32::rng::Rng;
 use embassy_stm32::{bind_interrupts, peripherals, rng, Config};
 use {defmt_rtt as _, panic_probe as _};
@@ -20,7 +20,7 @@ async fn main(_spawner: Spawner) {
     config.rcc.mux = ClockSrc::PLL1_R;
     config.rcc.pll = Some(Pll {
         // 64Mhz clock (16 / 1 * 8 / 2)
-        source: PLLSource::HSI,
+        source: PllSource::HSI,
         prediv: PllPreDiv::DIV1,
         mul: PllMul::MUL8,
         divp: None,

examples/stm32l5/src/bin/usb_ethernet.rs

@@ -49,7 +49,7 @@ async fn main(spawner: Spawner) {
     config.rcc.mux = ClockSrc::PLL1_R;
     config.rcc.pll = Some(Pll {
         // 80Mhz clock (16 / 1 * 10 / 2)
-        source: PLLSource::HSI,
+        source: PllSource::HSI,
         prediv: PllPreDiv::DIV1,
         mul: PllMul::MUL10,
         divp: None,

examples/stm32l5/src/bin/usb_hid_mouse.rs

@@ -26,7 +26,7 @@ async fn main(_spawner: Spawner) {
     config.rcc.mux = ClockSrc::PLL1_R;
     config.rcc.pll = Some(Pll {
         // 80Mhz clock (16 / 1 * 10 / 2)
-        source: PLLSource::HSI,
+        source: PllSource::HSI,
         prediv: PllPreDiv::DIV1,
         mul: PllMul::MUL10,
         divp: None,

examples/stm32l5/src/bin/usb_serial.rs

@@ -24,7 +24,7 @@ async fn main(_spawner: Spawner) {
     config.rcc.mux = ClockSrc::PLL1_R;
     config.rcc.pll = Some(Pll {
         // 80Mhz clock (16 / 1 * 10 / 2)
-        source: PLLSource::HSI,
+        source: PllSource::HSI,
         prediv: PllPreDiv::DIV1,
         mul: PllMul::MUL10,
         divp: None,

examples/stm32u5/Cargo.toml

@@ -8,7 +8,7 @@ license = "MIT OR Apache-2.0"
 # Change stm32u585ai to your chip name, if necessary.
 embassy-stm32 = { version = "0.1.0", path = "../../embassy-stm32", features = ["nightly", "defmt", "unstable-pac", "stm32u585ai", "time-driver-any", "memory-x" ]  }
 embassy-sync = { version = "0.4.0", path = "../../embassy-sync", features = ["defmt"] }
-embassy-executor = { version = "0.3.1", path = "../../embassy-executor", features = ["nightly", "arch-cortex-m", "executor-thread", "defmt", "integrated-timers"] }
+embassy-executor = { version = "0.3.3", path = "../../embassy-executor", features = ["nightly", "arch-cortex-m", "executor-thread", "defmt", "integrated-timers"] }
 embassy-time = { version = "0.1.5", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
 embassy-usb = { version = "0.1.0", path = "../../embassy-usb", features = ["defmt"] }
 
@@ -20,7 +20,7 @@ cortex-m-rt = "0.7.0"
 embedded-hal = "0.2.6"
 panic-probe = { version = "0.3", features = ["print-defmt"] }
 futures = { version = "0.3.17", default-features = false, features = ["async-await"] }
-heapless = { version = "0.7.5", default-features = false }
+heapless = { version = "0.8", default-features = false }
 
 micromath = "2.0.0"
 

examples/stm32u5/src/bin/usb_serial.rs

@@ -24,7 +24,7 @@ async fn main(_spawner: Spawner) {
 
     let mut config = Config::default();
     config.rcc.mux = ClockSrc::PLL1_R(PllConfig {
-        source: PllSrc::HSI,
+        source: PllSource::HSI,
         m: Pllm::DIV2,
         n: Plln::MUL10,
         r: Plldiv::DIV1,

examples/stm32wb/Cargo.toml

@@ -9,7 +9,7 @@ license = "MIT OR Apache-2.0"
 embassy-stm32 = { version = "0.1.0", path = "../../embassy-stm32", features = ["nightly", "defmt", "stm32wb55rg", "time-driver-any", "memory-x", "exti"]  }
 embassy-stm32-wpan = { version = "0.1.0", path = "../../embassy-stm32-wpan", features = ["defmt", "stm32wb55rg"] }
 embassy-sync = { version = "0.4.0", path = "../../embassy-sync", features = ["defmt"] }
-embassy-executor = { version = "0.3.1", path = "../../embassy-executor", features = ["nightly", "arch-cortex-m", "executor-thread", "defmt", "integrated-timers"] }
+embassy-executor = { version = "0.3.3", path = "../../embassy-executor", features = ["nightly", "arch-cortex-m", "executor-thread", "defmt", "integrated-timers"] }
 embassy-time = { version = "0.1.5", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
 embassy-net = { version = "0.2.0", path = "../../embassy-net", features = ["defmt", "udp", "proto-ipv6", "medium-ieee802154", "nightly"], optional=true }
 
@@ -21,7 +21,7 @@ cortex-m-rt = "0.7.0"
 embedded-hal = "0.2.6"
 panic-probe = { version = "0.3", features = ["print-defmt"] }
 futures = { version = "0.3.17", default-features = false, features = ["async-await"] }
-heapless = { version = "0.7.5", default-features = false }
+heapless = { version = "0.8", default-features = false }
 static_cell = { version = "2", features = ["nightly"]}
 
 [features]

examples/stm32wba/Cargo.toml

@@ -7,7 +7,7 @@ license = "MIT OR Apache-2.0"
 [dependencies]
 embassy-stm32 = { version = "0.1.0", path = "../../embassy-stm32", features = ["nightly", "defmt", "stm32wba52cg", "time-driver-any", "memory-x", "exti"]  }
 embassy-sync = { version = "0.4.0", path = "../../embassy-sync", features = ["defmt"] }
-embassy-executor = { version = "0.3.1", path = "../../embassy-executor", features = ["nightly", "arch-cortex-m", "executor-thread", "defmt", "integrated-timers"] }
+embassy-executor = { version = "0.3.3", path = "../../embassy-executor", features = ["nightly", "arch-cortex-m", "executor-thread", "defmt", "integrated-timers"] }
 embassy-time = { version = "0.1.5", path = "../../embassy-time", features = ["defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
 embassy-net = { version = "0.2.0", path = "../../embassy-net", features = ["defmt", "udp", "proto-ipv6", "medium-ieee802154", "nightly"], optional=true }
 
@@ -19,7 +19,7 @@ cortex-m-rt = "0.7.0"
 embedded-hal = "0.2.6"
 panic-probe = { version = "0.3", features = ["print-defmt"] }
 futures = { version = "0.3.17", default-features = false, features = ["async-await"] }
-heapless = { version = "0.7.5", default-features = false }
+heapless = { version = "0.8", default-features = false }
 static_cell = { version = "2", features = ["nightly"]}
 
 [profile.release]

examples/stm32wl/Cargo.toml

@@ -8,7 +8,7 @@ license = "MIT OR Apache-2.0"
 # Change stm32wl55jc-cm4 to your chip name, if necessary.
 embassy-stm32 = { version = "0.1.0", path = "../../embassy-stm32", features = ["nightly", "unstable-traits", "defmt", "stm32wl55jc-cm4", "time-driver-any", "memory-x", "unstable-pac", "exti", "chrono"] }
 embassy-sync = { version = "0.4.0", path = "../../embassy-sync", features = ["defmt"] }
-embassy-executor = { version = "0.3.1", path = "../../embassy-executor", features = ["nightly", "arch-cortex-m", "executor-thread", "defmt", "integrated-timers"] }
+embassy-executor = { version = "0.3.3", path = "../../embassy-executor", features = ["nightly", "arch-cortex-m", "executor-thread", "defmt", "integrated-timers"] }
 embassy-time = { version = "0.1.5", path = "../../embassy-time", features = ["nightly", "unstable-traits", "defmt", "defmt-timestamp-uptime", "tick-hz-32_768"] }
 embassy-embedded-hal = { version = "0.1.0", path = "../../embassy-embedded-hal" }
 embassy-lora = { version = "0.1.0", path = "../../embassy-lora", features = ["stm32wl", "time", "defmt"] }
@@ -25,7 +25,7 @@ embedded-hal = "0.2.6"
 embedded-storage = "0.3.0"
 panic-probe = { version = "0.3", features = ["print-defmt"] }
 futures = { version = "0.3.17", default-features = false, features = ["async-await"] }
-heapless = { version = "0.7.5", default-features = false }
+heapless = { version = "0.8", default-features = false }
 chrono = { version = "^0.4", default-features = false }
 
 [profile.release]

examples/stm32wl/src/bin/lora_lorawan.rs

@@ -44,7 +44,7 @@ async fn main(_spawner: Spawner) {
         });
         config.rcc.mux = ClockSrc::PLL1_R;
         config.rcc.pll = Some(Pll {
-            source: PLLSource::HSE,
+            source: PllSource::HSE,
             prediv: PllPreDiv::DIV2,
             mul: PllMul::MUL6,
             divp: None,

examples/stm32wl/src/bin/lora_p2p_receive.rs

@@ -37,7 +37,7 @@ async fn main(_spawner: Spawner) {
         });
         config.rcc.mux = ClockSrc::PLL1_R;
         config.rcc.pll = Some(Pll {
-            source: PLLSource::HSE,
+            source: PllSource::HSE,
             prediv: PllPreDiv::DIV2,
             mul: PllMul::MUL6,
             divp: None,

examples/stm32wl/src/bin/lora_p2p_send.rs

@@ -37,7 +37,7 @@ async fn main(_spawner: Spawner) {
         });
         config.rcc.mux = ClockSrc::PLL1_R;
         config.rcc.pll = Some(Pll {
-            source: PLLSource::HSE,
+            source: PllSource::HSE,
             prediv: PllPreDiv::DIV2,
             mul: PllMul::MUL6,
             divp: None,

examples/stm32wl/src/bin/random.rs

@@ -25,7 +25,7 @@ async fn main(_spawner: Spawner) {
         });
         config.rcc.mux = ClockSrc::PLL1_R;
         config.rcc.pll = Some(Pll {
-            source: PLLSource::HSE,
+            source: PllSource::HSE,
             prediv: PllPreDiv::DIV2,
             mul: PllMul::MUL6,
             divp: None,