#![macro_use] use core::convert::Infallible; use embassy_hal_common::{impl_peripheral, into_ref, PeripheralRef}; use crate::pac::gpio::{self, vals}; use crate::{pac, peripherals, Peripheral}; /// GPIO flexible pin. /// /// This pin can either be a disconnected, input, or output pin, or both. The level register bit will remain /// set while not in output mode, so the pin's level will be 'remembered' when it is not in output /// mode. pub struct Flex<'d, T: Pin> { pub(crate) pin: PeripheralRef<'d, T>, } impl<'d, T: Pin> Flex<'d, T> { /// Wrap the pin in a `Flex`. /// /// The pin remains disconnected. The initial output level is unspecified, but can be changed /// before the pin is put into output mode. /// #[inline] pub fn new(pin: impl Peripheral
+ 'd) -> Self {
into_ref!(pin);
// Pin will be in disconnected state.
Self { pin }
}
#[inline]
pub fn degrade(self) -> Flex<'d, AnyPin> {
// Safety: We are about to drop the other copy of this pin, so
// this clone is safe.
let pin = unsafe { self.pin.clone_unchecked() };
// We don't want to run the destructor here, because that would
// deconfigure the pin.
core::mem::forget(self);
Flex {
pin: pin.map_into:: + 'd, pull: Pull) -> Self {
let mut pin = Flex::new(pin);
pin.set_as_input(pull);
Self { pin }
}
#[inline]
pub fn degrade(self) -> Input<'d, AnyPin> {
Input {
pin: self.pin.degrade(),
}
}
#[inline]
pub fn is_high(&self) -> bool {
self.pin.is_high()
}
#[inline]
pub fn is_low(&self) -> bool {
self.pin.is_low()
}
#[inline]
pub fn get_level(&self) -> Level {
self.pin.get_level()
}
}
/// Digital input or output level.
#[derive(Debug, Eq, PartialEq, Copy, Clone)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Level {
Low,
High,
}
impl From + 'd, initial_output: Level, speed: Speed) -> Self {
let mut pin = Flex::new(pin);
match initial_output {
Level::High => pin.set_high(),
Level::Low => pin.set_low(),
}
pin.set_as_output(speed);
Self { pin }
}
#[inline]
pub fn degrade(self) -> Output<'d, AnyPin> {
Output {
pin: self.pin.degrade(),
}
}
/// Set the output as high.
#[inline]
pub fn set_high(&mut self) {
self.pin.set_high();
}
/// Set the output as low.
#[inline]
pub fn set_low(&mut self) {
self.pin.set_low();
}
/// Set the output level.
#[inline]
pub fn set_level(&mut self, level: Level) {
self.pin.set_level(level)
}
/// Is the output pin set as high?
#[inline]
pub fn is_set_high(&self) -> bool {
self.pin.is_set_high()
}
/// Is the output pin set as low?
#[inline]
pub fn is_set_low(&self) -> bool {
self.pin.is_set_low()
}
/// What level output is set to
#[inline]
pub fn get_output_level(&self) -> Level {
self.pin.get_output_level()
}
/// Toggle pin output
#[inline]
pub fn toggle(&mut self) {
self.pin.toggle();
}
}
/// GPIO output open-drain driver.
pub struct OutputOpenDrain<'d, T: Pin> {
pub(crate) pin: Flex<'d, T>,
}
impl<'d, T: Pin> OutputOpenDrain<'d, T> {
#[inline]
pub fn new(pin: impl Peripheral + 'd, initial_output: Level, speed: Speed, pull: Pull) -> Self {
let mut pin = Flex::new(pin);
match initial_output {
Level::High => pin.set_high(),
Level::Low => pin.set_low(),
}
pin.set_as_input_output(speed, pull);
Self { pin }
}
#[inline]
pub fn degrade(self) -> Output<'d, AnyPin> {
Output {
pin: self.pin.degrade(),
}
}
#[inline]
pub fn is_high(&self) -> bool {
!self.pin.is_low()
}
#[inline]
pub fn is_low(&self) -> bool {
self.pin.is_low()
}
/// Returns current pin level
#[inline]
pub fn get_level(&self) -> Level {
self.pin.get_level()
}
/// Set the output as high.
#[inline]
pub fn set_high(&mut self) {
self.pin.set_high();
}
/// Set the output as low.
#[inline]
pub fn set_low(&mut self) {
self.pin.set_low();
}
/// Set the output level.
#[inline]
pub fn set_level(&mut self, level: Level) {
self.pin.set_level(level);
}
/// Is the output pin set as high?
#[inline]
pub fn is_set_high(&self) -> bool {
self.pin.is_set_high()
}
/// Is the output pin set as low?
#[inline]
pub fn is_set_low(&self) -> bool {
self.pin.is_set_low()
}
/// What level output is set to
#[inline]
pub fn get_output_level(&self) -> Level {
self.pin.get_output_level()
}
/// Toggle pin output
#[inline]
pub fn toggle(&mut self) {
self.pin.toggle()
}
}
pub(crate) mod sealed {
use super::*;
/// Alternate function type settings
#[derive(Debug, Copy, Clone)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum AFType {
Input,
OutputPushPull,
OutputOpenDrain,
}
pub trait Pin {
fn pin_port(&self) -> u8;
#[inline]
fn _pin(&self) -> u8 {
self.pin_port() % 16
}
#[inline]
fn _port(&self) -> u8 {
self.pin_port() / 16
}
#[inline]
fn block(&self) -> gpio::Gpio {
pac::GPIO(self._port() as _)
}
/// Set the output as high.
#[inline]
fn set_high(&self) {
let n = self._pin() as _;
self.block().bsrr().write(|w| w.set_bs(n, true));
}
/// Set the output as low.
#[inline]
fn set_low(&self) {
let n = self._pin() as _;
self.block().bsrr().write(|w| w.set_br(n, true));
}
#[inline]
fn set_as_af(&self, af_num: u8, af_type: AFType) {
self.set_as_af_pull(af_num, af_type, Pull::None);
}
#[cfg(gpio_v1)]
#[inline]
fn set_as_af_pull(&self, _af_num: u8, af_type: AFType, pull: Pull) {
// F1 uses the AFIO register for remapping.
// For now, this is not implemented, so af_num is ignored
// _af_num should be zero here, since it is not set by stm32-data
let r = self.block();
let n = self._pin() as usize;
let crlh = if n < 8 { 0 } else { 1 };
match af_type {
AFType::Input => {
let cnf = match pull {
Pull::Up => {
r.bsrr().write(|w| w.set_bs(n, true));
vals::CnfIn::PULL
}
Pull::Down => {
r.bsrr().write(|w| w.set_br(n, true));
vals::CnfIn::PULL
}
Pull::None => vals::CnfIn::FLOATING,
};
r.cr(crlh).modify(|w| {
w.set_mode(n % 8, vals::Mode::INPUT);
w.set_cnf_in(n % 8, cnf);
});
}
AFType::OutputPushPull => {
r.cr(crlh).modify(|w| {
w.set_mode(n % 8, vals::Mode::OUTPUT50MHZ);
w.set_cnf_out(n % 8, vals::CnfOut::ALTPUSHPULL);
});
}
AFType::OutputOpenDrain => {
r.cr(crlh).modify(|w| {
w.set_mode(n % 8, vals::Mode::OUTPUT50MHZ);
w.set_cnf_out(n % 8, vals::CnfOut::ALTOPENDRAIN);
});
}
}
}
#[cfg(gpio_v2)]
#[inline]
fn set_as_af_pull(&self, af_num: u8, af_type: AFType, pull: Pull) {
let pin = self._pin() as usize;
let block = self.block();
block.afr(pin / 8).modify(|w| w.set_afr(pin % 8, af_num));
match af_type {
AFType::Input => {}
AFType::OutputPushPull => block.otyper().modify(|w| w.set_ot(pin, vals::Ot::PUSHPULL)),
AFType::OutputOpenDrain => block.otyper().modify(|w| w.set_ot(pin, vals::Ot::OPENDRAIN)),
}
block.pupdr().modify(|w| w.set_pupdr(pin, pull.into()));
block.moder().modify(|w| w.set_moder(pin, vals::Moder::ALTERNATE));
}
#[inline]
fn set_as_analog(&self) {
let pin = self._pin() as usize;
let block = self.block();
#[cfg(gpio_v1)]
{
let crlh = if pin < 8 { 0 } else { 1 };
block.cr(crlh).modify(|w| {
w.set_mode(pin % 8, vals::Mode::INPUT);
w.set_cnf_in(pin % 8, vals::CnfIn::ANALOG);
});
}
#[cfg(gpio_v2)]
block.moder().modify(|w| w.set_moder(pin, vals::Moder::ANALOG));
}
/// Set the pin as "disconnected", ie doing nothing and consuming the lowest
/// amount of power possible.
///
/// This is currently the same as set_as_analog but is semantically different really.
/// Drivers should set_as_disconnected pins when dropped.
#[inline]
fn set_as_disconnected(&self) {
self.set_as_analog();
}
#[inline]
fn set_speed(&self, speed: Speed) {
let pin = self._pin() as usize;
#[cfg(gpio_v1)]
{
let crlh = if pin < 8 { 0 } else { 1 };
self.block().cr(crlh).modify(|w| {
w.set_mode(pin % 8, speed.into());
});
}
#[cfg(gpio_v2)]
self.block().ospeedr().modify(|w| w.set_ospeedr(pin, speed.into()));
}
}
}
pub trait Pin: Peripheral + Into