417 lines
11 KiB
Rust
417 lines
11 KiB
Rust
use core::fmt::{Debug, Display};
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use bitfield::{bitfield, bitfield_bitrange, bitfield_fields};
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#[allow(non_camel_case_types)]
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#[derive(Debug, Copy, Clone)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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#[repr(u16)]
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/// SPI REGISTER DETAILS
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/// Table 38.
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pub enum SpiRegisters {
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IDVER = 0x00,
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PHYID = 0x01,
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CAPABILITY = 0x02,
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RESET = 0x03,
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CONFIG0 = 0x04,
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CONFIG2 = 0x06,
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STATUS0 = 0x08,
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STATUS1 = 0x09,
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IMASK0 = 0x0C,
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IMASK1 = 0x0D,
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MDIO_ACC = 0x20,
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TX_FSIZE = 0x30,
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TX = 0x31,
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TX_SPACE = 0x32,
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FIFO_CLR = 0x36,
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ADDR_FILT_UPR0 = 0x50,
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ADDR_FILT_LWR0 = 0x51,
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ADDR_FILT_UPR1 = 0x52,
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ADDR_FILT_LWR1 = 0x53,
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ADDR_MSK_LWR0 = 0x70,
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ADDR_MSK_UPR0 = 0x71,
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ADDR_MSK_LWR1 = 0x72,
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ADDR_MSK_UPR1 = 0x73,
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RX_FSIZE = 0x90,
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RX = 0x91,
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}
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impl Display for SpiRegisters {
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fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
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write!(f, "{self:?}")
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}
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}
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impl From<SpiRegisters> for u16 {
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fn from(val: SpiRegisters) -> Self {
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val as u16
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}
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}
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impl From<u16> for SpiRegisters {
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fn from(value: u16) -> Self {
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match value {
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0x00 => Self::IDVER,
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0x01 => Self::PHYID,
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0x02 => Self::CAPABILITY,
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0x03 => Self::RESET,
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0x04 => Self::CONFIG0,
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0x06 => Self::CONFIG2,
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0x08 => Self::STATUS0,
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0x09 => Self::STATUS1,
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0x0C => Self::IMASK0,
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0x0D => Self::IMASK1,
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0x20 => Self::MDIO_ACC,
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0x30 => Self::TX_FSIZE,
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0x31 => Self::TX,
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0x32 => Self::TX_SPACE,
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0x36 => Self::FIFO_CLR,
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0x50 => Self::ADDR_FILT_UPR0,
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0x51 => Self::ADDR_FILT_LWR0,
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0x52 => Self::ADDR_FILT_UPR1,
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0x53 => Self::ADDR_FILT_LWR1,
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0x70 => Self::ADDR_MSK_LWR0,
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0x71 => Self::ADDR_MSK_UPR0,
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0x72 => Self::ADDR_MSK_LWR1,
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0x73 => Self::ADDR_MSK_UPR1,
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0x90 => Self::RX_FSIZE,
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0x91 => Self::RX,
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e => panic!("Unknown value {}", e),
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}
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}
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}
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// Register definitions
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bitfield! {
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/// Status0 Register bits
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pub struct Status0(u32);
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impl Debug;
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u32;
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/// Control Data Protection Error
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pub cdpe, _ : 12;
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/// Transmit Frame Check Squence Error
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pub txfcse, _: 11;
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/// Transmit Time Stamp Capture Available C
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pub ttscac, _ : 10;
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/// Transmit Time Stamp Capture Available B
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pub ttscab, _ : 9;
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/// Transmit Time Stamp Capture Available A
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pub ttscaa, _ : 8;
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/// PHY Interrupt for Port 1
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pub phyint, _ : 7;
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/// Reset Complete
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pub resetc, _ : 6;
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/// Header error
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pub hdre, _ : 5;
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/// Loss of Frame Error
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pub lofe, _ : 4;
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/// Receiver Buffer Overflow Error
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pub rxboe, _ : 3;
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/// Host Tx FIFO Under Run Error
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pub txbue, _ : 2;
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/// Host Tx FIFO Overflow
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pub txboe, _ : 1;
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/// Transmit Protocol Error
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pub txpe, _ : 0;
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}
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bitfield! {
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/// Status1 Register bits
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pub struct Status1(u32);
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impl Debug;
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u32;
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/// ECC Error on Reading the Frame Size from a Tx FIFO
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pub tx_ecc_err, set_tx_ecc_err: 12;
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/// ECC Error on Reading the Frame Size from an Rx FIFO
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pub rx_ecc_err, set_rx_ecc_err : 11;
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/// Detected an Error on an SPI Transaction
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pub spi_err, set_spi_err: 10;
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/// Rx MAC Interframe Gap Error
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pub p1_rx_ifg_err, set_p1_rx_ifg_err : 8;
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/// Port1 Rx Ready High Priority
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pub p1_rx_rdy_hi, set_p1_rx_rdy_hi : 5;
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/// Port 1 Rx FIFO Contains Data
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pub p1_rx_rdy, set_p1_rx_rdy : 4;
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/// Tx Ready
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pub tx_rdy, set_tx_rdy : 3;
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/// Link Status Changed
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pub link_change, set_link_change : 1;
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/// Port 1 Link Status
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pub p1_link_status, _ : 0;
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}
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bitfield! {
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/// Config0 Register bits
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pub struct Config0(u32);
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impl Debug;
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u32;
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/// Configuration Synchronization
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pub sync, set_sync : 15;
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/// Transmit Frame Check Sequence Validation Enable
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pub txfcsve, set_txfcsve : 14;
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/// !CS Align Receive Frame Enable
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pub csarfe, set_csarfe : 13;
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/// Zero Align Receive Frame Enable
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pub zarfe, set_zarfe : 12;
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/// Transmit Credit Threshold
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pub tcxthresh, set_tcxthresh : 11, 10;
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/// Transmit Cut Through Enable
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pub txcte, set_txcte : 9;
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/// Receive Cut Through Enable
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pub rxcte, set_rxcte : 8;
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/// Frame Time Stamp Enable
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pub ftse, set_ftse : 7;
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/// Receive Frame Time Stamp Select
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pub ftss, set_ftss : 6;
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/// Enable Control Data Read Write Protection
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pub prote, set_prote : 5;
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/// Enable TX Data Chunk Sequence and Retry
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pub seqe, set_seqe : 4;
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/// Chunk Payload Selector (N).
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pub cps, set_cps : 2, 0;
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}
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bitfield! {
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/// Config2 Register bits
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pub struct Config2(u32);
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impl Debug;
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u32;
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/// Assert TX_RDY When the Tx FIFO is Empty
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pub tx_rdy_on_empty, set_tx_rdy_on_empty : 8;
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/// Determines If the SFD is Detected in the PHY or MAC
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pub sdf_detect_src, set_sdf_detect_src : 7;
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/// Statistics Clear on Reading
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pub stats_clr_on_rd, set_stats_clr_on_rd : 6;
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/// Enable SPI CRC
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pub crc_append, set_crc_append : 5;
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/// Admit Frames with IFG Errors on Port 1 (P1)
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pub p1_rcv_ifg_err_frm, set_p1_rcv_ifg_err_frm : 4;
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/// Forward Frames Not Matching Any MAC Address to the Host
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pub p1_fwd_unk2host, set_p1_fwd_unk2host : 2;
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/// SPI to MDIO Bridge MDC Clock Speed
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pub mspeed, set_mspeed : 0;
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}
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bitfield! {
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/// IMASK0 Register bits
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pub struct IMask0(u32);
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impl Debug;
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u32;
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/// Control Data Protection Error Mask
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pub cppem, set_cppem : 12;
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/// Transmit Frame Check Sequence Error Mask
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pub txfcsem, set_txfcsem : 11;
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/// Transmit Time Stamp Capture Available C Mask
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pub ttscacm, set_ttscacm : 10;
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/// Transmit Time Stamp Capture Available B Mask
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pub ttscabm, set_ttscabm : 9;
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/// Transmit Time Stamp Capture Available A Mask
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pub ttscaam, set_ttscaam : 8;
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/// Physical Layer Interrupt Mask
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pub phyintm, set_phyintm : 7;
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/// RESET Complete Mask
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pub resetcm, set_resetcm : 6;
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/// Header Error Mask
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pub hdrem, set_hdrem : 5;
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/// Loss of Frame Error Mask
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pub lofem, set_lofem : 4;
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/// Receive Buffer Overflow Error Mask
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pub rxboem, set_rxboem : 3;
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/// Transmit Buffer Underflow Error Mask
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pub txbuem, set_txbuem : 2;
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/// Transmit Buffer Overflow Error Mask
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pub txboem, set_txboem : 1;
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/// Transmit Protocol Error Mask
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pub txpem, set_txpem : 0;
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}
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bitfield! {
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/// IMASK1 Register bits
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pub struct IMask1(u32);
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impl Debug;
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u32;
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/// Mask Bit for TXF_ECC_ERR
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pub tx_ecc_err_mask, set_tx_ecc_err_mask : 12;
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/// Mask Bit for RXF_ECC_ERR
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pub rx_ecc_err_mask, set_rx_ecc_err_mask : 11;
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/// Mask Bit for SPI_ERR
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/// This field is only used with the generic SPI protocol
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pub spi_err_mask, set_spi_err_mask : 10;
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/// Mask Bit for RX_IFG_ERR
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pub p1_rx_ifg_err_mask, set_p1_rx_ifg_err_mask : 8;
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/// Mask Bit for P1_RX_RDY
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/// This field is only used with the generic SPI protocol
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pub p1_rx_rdy_mask, set_p1_rx_rdy_mask : 4;
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/// Mask Bit for TX_FRM_DONE
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/// This field is only used with the generic SPI protocol
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pub tx_rdy_mask, set_tx_rdy_mask : 3;
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/// Mask Bit for LINK_CHANGE
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pub link_change_mask, set_link_change_mask : 1;
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}
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/// LED Functions
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#[repr(u8)]
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pub enum LedFunc {
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LinkupTxRxActicity = 0,
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LinkupTxActicity,
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LinkupRxActicity,
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LinkupOnly,
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TxRxActivity,
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TxActivity,
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RxActivity,
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LinkupRxEr,
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LinkupRxTxEr,
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RxEr,
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RxTxEr,
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TxSop,
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RxSop,
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On,
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Off,
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Blink,
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TxLevel2P4,
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TxLevel1P0,
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Master,
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Slave,
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IncompatiableLinkCfg,
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AnLinkGood,
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AnComplete,
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TsTimer,
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LocRcvrStatus,
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RemRcvrStatus,
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Clk25Ref,
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TxTCLK,
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Clk120MHz,
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}
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impl From<LedFunc> for u8 {
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fn from(val: LedFunc) -> Self {
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val as u8
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}
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}
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impl From<u8> for LedFunc {
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fn from(value: u8) -> Self {
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match value {
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0 => LedFunc::LinkupTxRxActicity,
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1 => LedFunc::LinkupTxActicity,
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2 => LedFunc::LinkupRxActicity,
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3 => LedFunc::LinkupOnly,
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4 => LedFunc::TxRxActivity,
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5 => LedFunc::TxActivity,
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6 => LedFunc::RxActivity,
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7 => LedFunc::LinkupRxEr,
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8 => LedFunc::LinkupRxTxEr,
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9 => LedFunc::RxEr,
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10 => LedFunc::RxTxEr,
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11 => LedFunc::TxSop,
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12 => LedFunc::RxSop,
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13 => LedFunc::On,
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14 => LedFunc::Off,
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15 => LedFunc::Blink,
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16 => LedFunc::TxLevel2P4,
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17 => LedFunc::TxLevel1P0,
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18 => LedFunc::Master,
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19 => LedFunc::Slave,
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20 => LedFunc::IncompatiableLinkCfg,
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21 => LedFunc::AnLinkGood,
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22 => LedFunc::AnComplete,
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23 => LedFunc::TsTimer,
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24 => LedFunc::LocRcvrStatus,
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25 => LedFunc::RemRcvrStatus,
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26 => LedFunc::Clk25Ref,
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27 => LedFunc::TxTCLK,
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28 => LedFunc::Clk120MHz,
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e => panic!("Invalid value {}", e),
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}
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}
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}
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/// LED Control Register
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#[derive(Copy, Clone, PartialEq, Eq, Hash)]
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pub struct LedCntrl(pub u16);
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bitfield_bitrange! {struct LedCntrl(u16)}
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impl LedCntrl {
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bitfield_fields! {
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u8;
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/// LED 0 Pin Function
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pub from into LedFunc, led0_function, set_led0_function: 4, 0;
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/// LED 0 Mode Selection
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pub led0_mode, set_led0_mode: 5;
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/// Qualify Certain LED 0 Options with Link Status.
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pub led0_link_st_qualify, set_led0_link_st_qualify: 6;
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/// LED 0 Enable
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pub led0_en, set_led0_en: 7;
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/// LED 1 Pin Function
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pub from into LedFunc, led1_function, set_led1_function: 12, 8;
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/// /// LED 1 Mode Selection
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pub led1_mode, set_led1_mode: 13;
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/// Qualify Certain LED 1 Options with Link Status.
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pub led1_link_st_qualify, set_led1_link_st_qualify: 14;
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/// LED 1 Enable
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pub led1_en, set_led1_en: 15;
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}
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pub fn new() -> Self {
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LedCntrl(0)
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}
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}
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// LED Polarity
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#[repr(u8)]
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pub enum LedPol {
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AutoSense = 0,
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ActiveHigh,
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ActiveLow,
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}
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impl From<LedPol> for u8 {
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fn from(val: LedPol) -> Self {
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val as u8
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}
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}
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impl From<u8> for LedPol {
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fn from(value: u8) -> Self {
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match value {
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0 => LedPol::AutoSense,
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1 => LedPol::ActiveHigh,
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2 => LedPol::ActiveLow,
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e => panic!("Invalid value {}", e),
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}
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}
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}
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/// LED Control Register
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#[derive(Copy, Clone, PartialEq, Eq, Hash)]
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pub struct LedPolarity(pub u16);
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bitfield_bitrange! {struct LedPolarity(u16)}
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impl LedPolarity {
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bitfield_fields! {
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u8;
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/// LED 1 Polarity
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pub from into LedPol, led1_polarity, set_led1_polarity: 3, 2;
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/// LED 0 Polarity
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pub from into LedPol, led0_polarity, set_led0_polarity: 1, 0;
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}
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}
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/// SPI Header
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#[derive(Copy, Clone, PartialEq, Eq, Hash)]
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pub struct SpiHeader(pub u16);
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bitfield_bitrange! {struct SpiHeader(u16)}
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impl SpiHeader {
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bitfield_fields! {
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u16;
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/// Mask Bit for TXF_ECC_ERR
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pub control, set_control : 15;
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pub full_duplex, set_full_duplex : 14;
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/// Read or Write to register
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pub write, set_write : 13;
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/// Registers ID/addr
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pub from into SpiRegisters, addr, set_addr: 11, 0;
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}
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}
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