87 lines
2.3 KiB
Rust
87 lines
2.3 KiB
Rust
//! Make sure to connect GPIO pins 3 (`PIN_3`) and 4 (`PIN_4`) together
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//! to run this test.
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//!
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#![no_std]
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#![no_main]
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#![feature(type_alias_impl_trait)]
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#[path = "../common.rs"]
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mod common;
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use defmt::{assert_eq, *};
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use embassy_executor::Spawner;
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use embassy_rp::spi::{Config, Spi};
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use {defmt_rtt as _, panic_probe as _};
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#[embassy_executor::main]
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async fn main(_spawner: Spawner) {
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let p = embassy_rp::init(Default::default());
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info!("Hello World!");
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let clk = p.PIN_2;
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let mosi = p.PIN_3;
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let miso = p.PIN_4;
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let mut spi = Spi::new(p.SPI0, clk, mosi, miso, p.DMA_CH0, p.DMA_CH1, Config::default());
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// equal rx & tx buffers
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{
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let tx_buf = [1_u8, 2, 3, 4, 5, 6];
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let mut rx_buf = [0_u8; 6];
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spi.transfer(&mut rx_buf, &tx_buf).await.unwrap();
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assert_eq!(rx_buf, tx_buf);
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}
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// tx > rx buffer
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{
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let tx_buf = [7_u8, 8, 9, 10, 11, 12];
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let mut rx_buf = [0_u8; 3];
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spi.transfer(&mut rx_buf, &tx_buf).await.unwrap();
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assert_eq!(rx_buf, tx_buf[..3]);
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defmt::info!("tx > rx buffer - OK");
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}
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// we make sure to that clearing FIFO works after the uneven buffers
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// equal rx & tx buffers
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{
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let tx_buf = [13_u8, 14, 15, 16, 17, 18];
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let mut rx_buf = [0_u8; 6];
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spi.transfer(&mut rx_buf, &tx_buf).await.unwrap();
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assert_eq!(rx_buf, tx_buf);
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defmt::info!("buffer rx length == tx length - OK");
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}
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// rx > tx buffer
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{
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let tx_buf = [19_u8, 20, 21];
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let mut rx_buf = [0_u8; 6];
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// we should have written dummy data to tx buffer to sync clock.
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spi.transfer(&mut rx_buf, &tx_buf).await.unwrap();
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assert_eq!(
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rx_buf[..3],
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tx_buf,
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"only the first 3 TX bytes should have been received in the RX buffer"
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);
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assert_eq!(rx_buf[3..], [0, 0, 0], "the rest of the RX bytes should be empty");
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defmt::info!("buffer rx length > tx length - OK");
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}
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// equal rx & tx buffers
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{
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let tx_buf = [22_u8, 23, 24, 25, 26, 27];
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let mut rx_buf = [0_u8; 6];
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spi.transfer(&mut rx_buf, &tx_buf).await.unwrap();
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assert_eq!(rx_buf, tx_buf);
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defmt::info!("buffer rx length = tx length - OK");
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}
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info!("Test OK");
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cortex_m::asm::bkpt();
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}
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