612 lines
18 KiB
Rust
612 lines
18 KiB
Rust
//! Serial Peripheral Interface
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use core::marker::PhantomData;
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use embassy_embedded_hal::SetConfig;
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use embassy_futures::join::join;
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use embassy_hal_internal::{into_ref, PeripheralRef};
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pub use embedded_hal_02::spi::{Phase, Polarity};
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use crate::dma::{AnyChannel, Channel};
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use crate::gpio::sealed::Pin as _;
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use crate::gpio::{AnyPin, Pin as GpioPin};
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use crate::{pac, peripherals, Peripheral};
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#[derive(Debug, Clone, Copy, PartialEq, Eq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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#[non_exhaustive]
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pub enum Error {
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// No errors for now
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}
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#[non_exhaustive]
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#[derive(Clone)]
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pub struct Config {
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pub frequency: u32,
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pub phase: Phase,
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pub polarity: Polarity,
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}
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impl Default for Config {
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fn default() -> Self {
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Self {
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frequency: 1_000_000,
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phase: Phase::CaptureOnFirstTransition,
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polarity: Polarity::IdleLow,
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}
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}
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}
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pub struct Spi<'d, T: Instance, M: Mode> {
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inner: PeripheralRef<'d, T>,
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tx_dma: Option<PeripheralRef<'d, AnyChannel>>,
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rx_dma: Option<PeripheralRef<'d, AnyChannel>>,
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phantom: PhantomData<(&'d mut T, M)>,
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}
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fn div_roundup(a: u32, b: u32) -> u32 {
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(a + b - 1) / b
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}
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fn calc_prescs(freq: u32) -> (u8, u8) {
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let clk_peri = crate::clocks::clk_peri_freq();
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// final SPI frequency: spi_freq = clk_peri / presc / postdiv
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// presc must be in 2..=254, and must be even
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// postdiv must be in 1..=256
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// divide extra by 2, so we get rid of the "presc must be even" requirement
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let ratio = div_roundup(clk_peri, freq * 2);
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if ratio > 127 * 256 {
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panic!("Requested too low SPI frequency");
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}
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let presc = div_roundup(ratio, 256);
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let postdiv = if presc == 1 { ratio } else { div_roundup(ratio, presc) };
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((presc * 2) as u8, (postdiv - 1) as u8)
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}
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impl<'d, T: Instance, M: Mode> Spi<'d, T, M> {
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fn new_inner(
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inner: impl Peripheral<P = T> + 'd,
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clk: Option<PeripheralRef<'d, AnyPin>>,
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mosi: Option<PeripheralRef<'d, AnyPin>>,
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miso: Option<PeripheralRef<'d, AnyPin>>,
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cs: Option<PeripheralRef<'d, AnyPin>>,
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tx_dma: Option<PeripheralRef<'d, AnyChannel>>,
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rx_dma: Option<PeripheralRef<'d, AnyChannel>>,
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config: Config,
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) -> Self {
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into_ref!(inner);
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let p = inner.regs();
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let (presc, postdiv) = calc_prescs(config.frequency);
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p.cpsr().write(|w| w.set_cpsdvsr(presc));
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p.cr0().write(|w| {
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w.set_dss(0b0111); // 8bit
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w.set_spo(config.polarity == Polarity::IdleHigh);
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w.set_sph(config.phase == Phase::CaptureOnSecondTransition);
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w.set_scr(postdiv);
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});
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// Always enable DREQ signals -- harmless if DMA is not listening
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p.dmacr().write(|reg| {
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reg.set_rxdmae(true);
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reg.set_txdmae(true);
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});
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// finally, enable.
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p.cr1().write(|w| w.set_sse(true));
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if let Some(pin) = &clk {
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pin.io().ctrl().write(|w| w.set_funcsel(1));
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}
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if let Some(pin) = &mosi {
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pin.io().ctrl().write(|w| w.set_funcsel(1));
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}
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if let Some(pin) = &miso {
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pin.io().ctrl().write(|w| w.set_funcsel(1));
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}
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if let Some(pin) = &cs {
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pin.io().ctrl().write(|w| w.set_funcsel(1));
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}
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Self {
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inner,
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tx_dma,
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rx_dma,
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phantom: PhantomData,
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}
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}
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pub fn blocking_write(&mut self, data: &[u8]) -> Result<(), Error> {
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let p = self.inner.regs();
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for &b in data {
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while !p.sr().read().tnf() {}
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p.dr().write(|w| w.set_data(b as _));
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while !p.sr().read().rne() {}
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let _ = p.dr().read();
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}
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self.flush()?;
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Ok(())
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}
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pub fn blocking_transfer_in_place(&mut self, data: &mut [u8]) -> Result<(), Error> {
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let p = self.inner.regs();
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for b in data {
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while !p.sr().read().tnf() {}
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p.dr().write(|w| w.set_data(*b as _));
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while !p.sr().read().rne() {}
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*b = p.dr().read().data() as u8;
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}
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self.flush()?;
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Ok(())
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}
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pub fn blocking_read(&mut self, data: &mut [u8]) -> Result<(), Error> {
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let p = self.inner.regs();
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for b in data {
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while !p.sr().read().tnf() {}
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p.dr().write(|w| w.set_data(0));
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while !p.sr().read().rne() {}
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*b = p.dr().read().data() as u8;
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}
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self.flush()?;
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Ok(())
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}
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pub fn blocking_transfer(&mut self, read: &mut [u8], write: &[u8]) -> Result<(), Error> {
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let p = self.inner.regs();
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let len = read.len().max(write.len());
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for i in 0..len {
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let wb = write.get(i).copied().unwrap_or(0);
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while !p.sr().read().tnf() {}
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p.dr().write(|w| w.set_data(wb as _));
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while !p.sr().read().rne() {}
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let rb = p.dr().read().data() as u8;
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if let Some(r) = read.get_mut(i) {
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*r = rb;
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}
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}
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self.flush()?;
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Ok(())
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}
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pub fn flush(&mut self) -> Result<(), Error> {
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let p = self.inner.regs();
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while p.sr().read().bsy() {}
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Ok(())
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}
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pub fn set_frequency(&mut self, freq: u32) {
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let (presc, postdiv) = calc_prescs(freq);
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let p = self.inner.regs();
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// disable
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p.cr1().write(|w| w.set_sse(false));
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// change stuff
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p.cpsr().write(|w| w.set_cpsdvsr(presc));
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p.cr0().modify(|w| {
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w.set_scr(postdiv);
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});
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// enable
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p.cr1().write(|w| w.set_sse(true));
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}
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}
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impl<'d, T: Instance> Spi<'d, T, Blocking> {
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pub fn new_blocking(
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inner: impl Peripheral<P = T> + 'd,
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clk: impl Peripheral<P = impl ClkPin<T> + 'd> + 'd,
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mosi: impl Peripheral<P = impl MosiPin<T> + 'd> + 'd,
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miso: impl Peripheral<P = impl MisoPin<T> + 'd> + 'd,
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config: Config,
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) -> Self {
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into_ref!(clk, mosi, miso);
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Self::new_inner(
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inner,
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Some(clk.map_into()),
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Some(mosi.map_into()),
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Some(miso.map_into()),
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None,
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None,
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None,
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config,
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)
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}
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pub fn new_blocking_txonly(
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inner: impl Peripheral<P = T> + 'd,
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clk: impl Peripheral<P = impl ClkPin<T> + 'd> + 'd,
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mosi: impl Peripheral<P = impl MosiPin<T> + 'd> + 'd,
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config: Config,
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) -> Self {
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into_ref!(clk, mosi);
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Self::new_inner(
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inner,
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Some(clk.map_into()),
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Some(mosi.map_into()),
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None,
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None,
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None,
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None,
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config,
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)
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}
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pub fn new_blocking_rxonly(
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inner: impl Peripheral<P = T> + 'd,
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clk: impl Peripheral<P = impl ClkPin<T> + 'd> + 'd,
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miso: impl Peripheral<P = impl MisoPin<T> + 'd> + 'd,
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config: Config,
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) -> Self {
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into_ref!(clk, miso);
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Self::new_inner(
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inner,
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Some(clk.map_into()),
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None,
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Some(miso.map_into()),
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None,
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None,
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None,
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config,
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)
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}
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}
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impl<'d, T: Instance> Spi<'d, T, Async> {
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pub fn new(
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inner: impl Peripheral<P = T> + 'd,
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clk: impl Peripheral<P = impl ClkPin<T> + 'd> + 'd,
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mosi: impl Peripheral<P = impl MosiPin<T> + 'd> + 'd,
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miso: impl Peripheral<P = impl MisoPin<T> + 'd> + 'd,
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tx_dma: impl Peripheral<P = impl Channel> + 'd,
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rx_dma: impl Peripheral<P = impl Channel> + 'd,
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config: Config,
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) -> Self {
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into_ref!(tx_dma, rx_dma, clk, mosi, miso);
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Self::new_inner(
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inner,
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Some(clk.map_into()),
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Some(mosi.map_into()),
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Some(miso.map_into()),
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None,
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Some(tx_dma.map_into()),
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Some(rx_dma.map_into()),
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config,
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)
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}
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pub fn new_txonly(
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inner: impl Peripheral<P = T> + 'd,
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clk: impl Peripheral<P = impl ClkPin<T> + 'd> + 'd,
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mosi: impl Peripheral<P = impl MosiPin<T> + 'd> + 'd,
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tx_dma: impl Peripheral<P = impl Channel> + 'd,
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config: Config,
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) -> Self {
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into_ref!(tx_dma, clk, mosi);
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Self::new_inner(
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inner,
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Some(clk.map_into()),
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Some(mosi.map_into()),
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None,
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None,
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Some(tx_dma.map_into()),
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None,
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config,
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)
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}
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pub fn new_rxonly(
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inner: impl Peripheral<P = T> + 'd,
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clk: impl Peripheral<P = impl ClkPin<T> + 'd> + 'd,
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miso: impl Peripheral<P = impl MisoPin<T> + 'd> + 'd,
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rx_dma: impl Peripheral<P = impl Channel> + 'd,
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config: Config,
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) -> Self {
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into_ref!(rx_dma, clk, miso);
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Self::new_inner(
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inner,
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Some(clk.map_into()),
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None,
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Some(miso.map_into()),
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None,
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None,
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Some(rx_dma.map_into()),
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config,
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)
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}
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pub async fn write(&mut self, buffer: &[u8]) -> Result<(), Error> {
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let tx_ch = self.tx_dma.as_mut().unwrap();
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let tx_transfer = unsafe {
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// If we don't assign future to a variable, the data register pointer
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// is held across an await and makes the future non-Send.
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crate::dma::write(tx_ch, buffer, self.inner.regs().dr().as_ptr() as *mut _, T::TX_DREQ)
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};
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tx_transfer.await;
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let p = self.inner.regs();
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while p.sr().read().bsy() {}
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// clear RX FIFO contents to prevent stale reads
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while p.sr().read().rne() {
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let _: u16 = p.dr().read().data();
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}
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// clear RX overrun interrupt
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p.icr().write(|w| w.set_roric(true));
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Ok(())
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}
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pub async fn read(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
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// Start RX first. Transfer starts when TX starts, if RX
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// is not started yet we might lose bytes.
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let rx_ch = self.rx_dma.as_mut().unwrap();
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let rx_transfer = unsafe {
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// If we don't assign future to a variable, the data register pointer
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// is held across an await and makes the future non-Send.
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crate::dma::read(rx_ch, self.inner.regs().dr().as_ptr() as *const _, buffer, T::RX_DREQ)
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};
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let tx_ch = self.tx_dma.as_mut().unwrap();
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let tx_transfer = unsafe {
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// If we don't assign future to a variable, the data register pointer
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// is held across an await and makes the future non-Send.
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crate::dma::write_repeated(
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tx_ch,
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self.inner.regs().dr().as_ptr() as *mut u8,
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buffer.len(),
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T::TX_DREQ,
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)
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};
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join(tx_transfer, rx_transfer).await;
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Ok(())
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}
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pub async fn transfer(&mut self, rx_buffer: &mut [u8], tx_buffer: &[u8]) -> Result<(), Error> {
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self.transfer_inner(rx_buffer, tx_buffer).await
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}
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pub async fn transfer_in_place(&mut self, words: &mut [u8]) -> Result<(), Error> {
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self.transfer_inner(words, words).await
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}
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async fn transfer_inner(&mut self, rx_ptr: *mut [u8], tx_ptr: *const [u8]) -> Result<(), Error> {
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let (_, tx_len) = crate::dma::slice_ptr_parts(tx_ptr);
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let (_, rx_len) = crate::dma::slice_ptr_parts_mut(rx_ptr);
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// Start RX first. Transfer starts when TX starts, if RX
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// is not started yet we might lose bytes.
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let rx_ch = self.rx_dma.as_mut().unwrap();
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let rx_transfer = unsafe {
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// If we don't assign future to a variable, the data register pointer
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// is held across an await and makes the future non-Send.
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crate::dma::read(rx_ch, self.inner.regs().dr().as_ptr() as *const _, rx_ptr, T::RX_DREQ)
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};
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let mut tx_ch = self.tx_dma.as_mut().unwrap();
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// If we don't assign future to a variable, the data register pointer
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// is held across an await and makes the future non-Send.
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let tx_transfer = async {
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let p = self.inner.regs();
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unsafe {
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crate::dma::write(&mut tx_ch, tx_ptr, p.dr().as_ptr() as *mut _, T::TX_DREQ).await;
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if rx_len > tx_len {
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let write_bytes_len = rx_len - tx_len;
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// write dummy data
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// this will disable incrementation of the buffers
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crate::dma::write_repeated(tx_ch, p.dr().as_ptr() as *mut u8, write_bytes_len, T::TX_DREQ).await
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}
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}
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};
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join(tx_transfer, rx_transfer).await;
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// if tx > rx we should clear any overflow of the FIFO SPI buffer
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if tx_len > rx_len {
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let p = self.inner.regs();
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while p.sr().read().bsy() {}
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// clear RX FIFO contents to prevent stale reads
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while p.sr().read().rne() {
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let _: u16 = p.dr().read().data();
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}
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// clear RX overrun interrupt
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p.icr().write(|w| w.set_roric(true));
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}
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Ok(())
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}
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}
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mod sealed {
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use super::*;
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pub trait Mode {}
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pub trait Instance {
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const TX_DREQ: u8;
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const RX_DREQ: u8;
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fn regs(&self) -> pac::spi::Spi;
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}
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}
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pub trait Mode: sealed::Mode {}
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pub trait Instance: sealed::Instance {}
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macro_rules! impl_instance {
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($type:ident, $irq:ident, $tx_dreq:expr, $rx_dreq:expr) => {
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impl sealed::Instance for peripherals::$type {
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const TX_DREQ: u8 = $tx_dreq;
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const RX_DREQ: u8 = $rx_dreq;
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fn regs(&self) -> pac::spi::Spi {
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pac::$type
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}
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}
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impl Instance for peripherals::$type {}
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};
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}
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impl_instance!(SPI0, Spi0, 16, 17);
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impl_instance!(SPI1, Spi1, 18, 19);
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pub trait ClkPin<T: Instance>: GpioPin {}
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pub trait CsPin<T: Instance>: GpioPin {}
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pub trait MosiPin<T: Instance>: GpioPin {}
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pub trait MisoPin<T: Instance>: GpioPin {}
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macro_rules! impl_pin {
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($pin:ident, $instance:ident, $function:ident) => {
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impl $function<peripherals::$instance> for peripherals::$pin {}
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};
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}
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impl_pin!(PIN_0, SPI0, MisoPin);
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impl_pin!(PIN_1, SPI0, CsPin);
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impl_pin!(PIN_2, SPI0, ClkPin);
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impl_pin!(PIN_3, SPI0, MosiPin);
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impl_pin!(PIN_4, SPI0, MisoPin);
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impl_pin!(PIN_5, SPI0, CsPin);
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impl_pin!(PIN_6, SPI0, ClkPin);
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impl_pin!(PIN_7, SPI0, MosiPin);
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impl_pin!(PIN_8, SPI1, MisoPin);
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impl_pin!(PIN_9, SPI1, CsPin);
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impl_pin!(PIN_10, SPI1, ClkPin);
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impl_pin!(PIN_11, SPI1, MosiPin);
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impl_pin!(PIN_12, SPI1, MisoPin);
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impl_pin!(PIN_13, SPI1, CsPin);
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impl_pin!(PIN_14, SPI1, ClkPin);
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impl_pin!(PIN_15, SPI1, MosiPin);
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impl_pin!(PIN_16, SPI0, MisoPin);
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impl_pin!(PIN_17, SPI0, CsPin);
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impl_pin!(PIN_18, SPI0, ClkPin);
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impl_pin!(PIN_19, SPI0, MosiPin);
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impl_pin!(PIN_20, SPI0, MisoPin);
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impl_pin!(PIN_21, SPI0, CsPin);
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impl_pin!(PIN_22, SPI0, ClkPin);
|
|
impl_pin!(PIN_23, SPI0, MosiPin);
|
|
impl_pin!(PIN_24, SPI1, MisoPin);
|
|
impl_pin!(PIN_25, SPI1, CsPin);
|
|
impl_pin!(PIN_26, SPI1, ClkPin);
|
|
impl_pin!(PIN_27, SPI1, MosiPin);
|
|
impl_pin!(PIN_28, SPI1, MisoPin);
|
|
impl_pin!(PIN_29, SPI1, CsPin);
|
|
|
|
macro_rules! impl_mode {
|
|
($name:ident) => {
|
|
impl sealed::Mode for $name {}
|
|
impl Mode for $name {}
|
|
};
|
|
}
|
|
|
|
pub struct Blocking;
|
|
pub struct Async;
|
|
|
|
impl_mode!(Blocking);
|
|
impl_mode!(Async);
|
|
|
|
// ====================
|
|
|
|
mod eh02 {
|
|
use super::*;
|
|
|
|
impl<'d, T: Instance, M: Mode> embedded_hal_02::blocking::spi::Transfer<u8> for Spi<'d, T, M> {
|
|
type Error = Error;
|
|
fn transfer<'w>(&mut self, words: &'w mut [u8]) -> Result<&'w [u8], Self::Error> {
|
|
self.blocking_transfer_in_place(words)?;
|
|
Ok(words)
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Instance, M: Mode> embedded_hal_02::blocking::spi::Write<u8> for Spi<'d, T, M> {
|
|
type Error = Error;
|
|
|
|
fn write(&mut self, words: &[u8]) -> Result<(), Self::Error> {
|
|
self.blocking_write(words)
|
|
}
|
|
}
|
|
}
|
|
|
|
#[cfg(feature = "unstable-traits")]
|
|
mod eh1 {
|
|
use super::*;
|
|
|
|
impl embedded_hal_1::spi::Error for Error {
|
|
fn kind(&self) -> embedded_hal_1::spi::ErrorKind {
|
|
match *self {}
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Instance, M: Mode> embedded_hal_1::spi::ErrorType for Spi<'d, T, M> {
|
|
type Error = Error;
|
|
}
|
|
|
|
impl<'d, T: Instance, M: Mode> embedded_hal_1::spi::SpiBus<u8> for Spi<'d, T, M> {
|
|
fn flush(&mut self) -> Result<(), Self::Error> {
|
|
Ok(())
|
|
}
|
|
|
|
fn read(&mut self, words: &mut [u8]) -> Result<(), Self::Error> {
|
|
self.blocking_transfer(words, &[])
|
|
}
|
|
|
|
fn write(&mut self, words: &[u8]) -> Result<(), Self::Error> {
|
|
self.blocking_write(words)
|
|
}
|
|
|
|
fn transfer(&mut self, read: &mut [u8], write: &[u8]) -> Result<(), Self::Error> {
|
|
self.blocking_transfer(read, write)
|
|
}
|
|
|
|
fn transfer_in_place(&mut self, words: &mut [u8]) -> Result<(), Self::Error> {
|
|
self.blocking_transfer_in_place(words)
|
|
}
|
|
}
|
|
}
|
|
|
|
#[cfg(all(feature = "unstable-traits", feature = "nightly"))]
|
|
mod eha {
|
|
use super::*;
|
|
|
|
impl<'d, T: Instance> embedded_hal_async::spi::SpiBus<u8> for Spi<'d, T, Async> {
|
|
async fn flush(&mut self) -> Result<(), Self::Error> {
|
|
Ok(())
|
|
}
|
|
|
|
async fn write(&mut self, words: &[u8]) -> Result<(), Self::Error> {
|
|
self.write(words).await
|
|
}
|
|
|
|
async fn read(&mut self, words: &mut [u8]) -> Result<(), Self::Error> {
|
|
self.read(words).await
|
|
}
|
|
|
|
async fn transfer(&mut self, read: &mut [u8], write: &[u8]) -> Result<(), Self::Error> {
|
|
self.transfer(read, write).await
|
|
}
|
|
|
|
async fn transfer_in_place(&mut self, words: &mut [u8]) -> Result<(), Self::Error> {
|
|
self.transfer_in_place(words).await
|
|
}
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Instance, M: Mode> SetConfig for Spi<'d, T, M> {
|
|
type Config = Config;
|
|
fn set_config(&mut self, config: &Self::Config) {
|
|
let p = self.inner.regs();
|
|
let (presc, postdiv) = calc_prescs(config.frequency);
|
|
p.cpsr().write(|w| w.set_cpsdvsr(presc));
|
|
p.cr0().write(|w| {
|
|
w.set_dss(0b0111); // 8bit
|
|
w.set_spo(config.polarity == Polarity::IdleHigh);
|
|
w.set_sph(config.phase == Phase::CaptureOnSecondTransition);
|
|
w.set_scr(postdiv);
|
|
});
|
|
}
|
|
}
|