589 lines
15 KiB
Rust
589 lines
15 KiB
Rust
#![macro_use]
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use core::convert::Infallible;
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use core::marker::PhantomData;
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use embassy::util::Unborrow;
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use embassy_hal_common::{unborrow, unsafe_impl_unborrow};
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use embedded_hal::digital::v2::{toggleable, InputPin, OutputPin, StatefulOutputPin};
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use crate::pac;
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use crate::pac::gpio::{self, vals};
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use crate::peripherals;
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/// Pull setting for an input.
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#[derive(Debug, Eq, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum Pull {
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None,
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Up,
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Down,
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}
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#[cfg(gpio_v2)]
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impl From<Pull> for vals::Pupdr {
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fn from(pull: Pull) -> Self {
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use Pull::*;
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match pull {
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None => vals::Pupdr::FLOATING,
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Up => vals::Pupdr::PULLUP,
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Down => vals::Pupdr::PULLDOWN,
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}
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}
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}
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/// Speed settings
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#[derive(Debug)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum Speed {
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Low,
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Medium,
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#[cfg(not(any(syscfg_f0, gpio_v1)))]
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High,
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VeryHigh,
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}
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#[cfg(gpio_v1)]
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impl From<Speed> for vals::Mode {
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fn from(speed: Speed) -> Self {
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use Speed::*;
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match speed {
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Low => vals::Mode::OUTPUT2,
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Medium => vals::Mode::OUTPUT,
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VeryHigh => vals::Mode::OUTPUT50,
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}
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}
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}
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#[cfg(gpio_v2)]
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impl From<Speed> for vals::Ospeedr {
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fn from(speed: Speed) -> Self {
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use Speed::*;
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match speed {
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Low => vals::Ospeedr::LOWSPEED,
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Medium => vals::Ospeedr::MEDIUMSPEED,
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#[cfg(not(syscfg_f0))]
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High => vals::Ospeedr::HIGHSPEED,
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VeryHigh => vals::Ospeedr::VERYHIGHSPEED,
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}
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}
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}
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/// GPIO input driver.
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pub struct Input<'d, T: Pin> {
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pub(crate) pin: T,
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phantom: PhantomData<&'d mut T>,
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}
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impl<'d, T: Pin> Input<'d, T> {
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pub fn new(pin: impl Unborrow<Target = T> + 'd, pull: Pull) -> Self {
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unborrow!(pin);
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cortex_m::interrupt::free(|_| unsafe {
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let r = pin.block();
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let n = pin.pin() as usize;
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#[cfg(gpio_v1)]
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{
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let crlh = if n < 8 { 0 } else { 1 };
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match pull {
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Pull::Up => r.bsrr().write(|w| w.set_bs(n, true)),
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Pull::Down => r.bsrr().write(|w| w.set_br(n, true)),
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Pull::None => {}
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}
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if pull == Pull::None {
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r.cr(crlh)
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.modify(|w| w.set_cnf(n % 8, vals::Cnf::OPENDRAIN));
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} else {
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r.cr(crlh)
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.modify(|w| w.set_cnf(n % 8, vals::Cnf::ALTPUSHPULL));
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}
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r.cr(crlh).modify(|w| w.set_mode(n % 8, vals::Mode::INPUT));
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}
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#[cfg(gpio_v2)]
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{
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r.pupdr().modify(|w| w.set_pupdr(n, pull.into()));
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r.otyper().modify(|w| w.set_ot(n, vals::Ot::PUSHPULL));
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r.moder().modify(|w| w.set_moder(n, vals::Moder::INPUT));
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}
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});
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Self {
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pin,
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phantom: PhantomData,
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}
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}
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}
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impl<'d, T: Pin> Drop for Input<'d, T> {
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fn drop(&mut self) {
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cortex_m::interrupt::free(|_| unsafe {
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let r = self.pin.block();
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let n = self.pin.pin() as usize;
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#[cfg(gpio_v1)]
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{
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let crlh = if n < 8 { 0 } else { 1 };
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r.cr(crlh)
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.modify(|w| w.set_cnf(n % 8, vals::Cnf::OPENDRAIN));
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}
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#[cfg(gpio_v2)]
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r.pupdr().modify(|w| w.set_pupdr(n, vals::Pupdr::FLOATING));
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});
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}
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}
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impl<'d, T: Pin> InputPin for Input<'d, T> {
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type Error = Infallible;
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fn is_high(&self) -> Result<bool, Self::Error> {
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self.is_low().map(|v| !v)
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}
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fn is_low(&self) -> Result<bool, Self::Error> {
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let state = unsafe { self.pin.block().idr().read().idr(self.pin.pin() as _) };
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Ok(state == vals::Idr::LOW)
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}
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}
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/// Digital input or output level.
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#[derive(Debug, Eq, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum Level {
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Low,
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High,
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}
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/// GPIO output driver.
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pub struct Output<'d, T: Pin> {
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pub(crate) pin: T,
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phantom: PhantomData<&'d mut T>,
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}
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impl<'d, T: Pin> Output<'d, T> {
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pub fn new(pin: impl Unborrow<Target = T> + 'd, initial_output: Level, speed: Speed) -> Self {
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unborrow!(pin);
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match initial_output {
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Level::High => pin.set_high(),
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Level::Low => pin.set_low(),
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}
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cortex_m::interrupt::free(|_| unsafe {
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let r = pin.block();
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let n = pin.pin() as usize;
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#[cfg(gpio_v1)]
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{
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let crlh = if n < 8 { 0 } else { 1 };
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r.cr(crlh).modify(|w| w.set_cnf(n % 8, vals::Cnf::PUSHPULL));
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r.cr(crlh).modify(|w| w.set_mode(n % 8, speed.into()));
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}
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#[cfg(gpio_v2)]
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{
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r.pupdr().modify(|w| w.set_pupdr(n, vals::Pupdr::FLOATING));
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r.otyper().modify(|w| w.set_ot(n, vals::Ot::PUSHPULL));
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pin.set_speed(speed);
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r.moder().modify(|w| w.set_moder(n, vals::Moder::OUTPUT));
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}
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});
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Self {
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pin,
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phantom: PhantomData,
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}
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}
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}
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impl<'d, T: Pin> Drop for Output<'d, T> {
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fn drop(&mut self) {
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cortex_m::interrupt::free(|_| unsafe {
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let r = self.pin.block();
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let n = self.pin.pin() as usize;
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#[cfg(gpio_v1)]
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{
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let crlh = if n < 8 { 0 } else { 1 };
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r.cr(crlh)
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.modify(|w| w.set_cnf(n % 8, vals::Cnf::OPENDRAIN));
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r.cr(crlh).modify(|w| w.set_mode(n % 8, vals::Mode::INPUT));
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}
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#[cfg(gpio_v2)]
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{
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r.pupdr().modify(|w| w.set_pupdr(n, vals::Pupdr::FLOATING));
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r.moder().modify(|w| w.set_moder(n, vals::Moder::INPUT));
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}
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});
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}
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}
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impl<'d, T: Pin> OutputPin for Output<'d, T> {
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type Error = Infallible;
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/// Set the output as high.
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fn set_high(&mut self) -> Result<(), Self::Error> {
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self.pin.set_high();
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Ok(())
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}
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/// Set the output as low.
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fn set_low(&mut self) -> Result<(), Self::Error> {
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self.pin.set_low();
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Ok(())
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}
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}
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impl<'d, T: Pin> StatefulOutputPin for Output<'d, T> {
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/// Is the output pin set as high?
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fn is_set_high(&self) -> Result<bool, Self::Error> {
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self.is_set_low().map(|v| !v)
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}
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/// Is the output pin set as low?
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fn is_set_low(&self) -> Result<bool, Self::Error> {
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let state = unsafe { self.pin.block().odr().read().odr(self.pin.pin() as _) };
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Ok(state == vals::Odr::LOW)
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}
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}
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impl<'d, T: Pin> toggleable::Default for Output<'d, T> {}
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/// GPIO output open-drain driver.
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pub struct OutputOpenDrain<'d, T: Pin> {
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pub(crate) pin: T,
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phantom: PhantomData<&'d mut T>,
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}
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impl<'d, T: Pin> OutputOpenDrain<'d, T> {
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pub fn new(
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pin: impl Unborrow<Target = T> + 'd,
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initial_output: Level,
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speed: Speed,
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pull: Pull,
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) -> Self {
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unborrow!(pin);
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match initial_output {
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Level::High => pin.set_high(),
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Level::Low => pin.set_low(),
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}
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cortex_m::interrupt::free(|_| unsafe {
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let r = pin.block();
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let n = pin.pin() as usize;
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#[cfg(gpio_v1)]
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{
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let crlh = if n < 8 { 0 } else { 1 };
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match pull {
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Pull::Up => r.bsrr().write(|w| w.set_bs(n, true)),
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Pull::Down => r.bsrr().write(|w| w.set_br(n, true)),
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Pull::None => {}
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}
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r.cr(crlh).modify(|w| w.set_mode(n % 8, speed.into()));
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r.cr(crlh)
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.modify(|w| w.set_cnf(n % 8, vals::Cnf::OPENDRAIN));
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}
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#[cfg(gpio_v2)]
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{
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r.pupdr().modify(|w| w.set_pupdr(n, pull.into()));
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r.otyper().modify(|w| w.set_ot(n, vals::Ot::OPENDRAIN));
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pin.set_speed(speed);
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r.moder().modify(|w| w.set_moder(n, vals::Moder::OUTPUT));
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}
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});
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Self {
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pin,
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phantom: PhantomData,
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}
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}
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}
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impl<'d, T: Pin> Drop for OutputOpenDrain<'d, T> {
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fn drop(&mut self) {
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cortex_m::interrupt::free(|_| unsafe {
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let r = self.pin.block();
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let n = self.pin.pin() as usize;
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#[cfg(gpio_v1)]
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{
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let crlh = if n < 8 { 0 } else { 1 };
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r.cr(crlh)
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.modify(|w| w.set_cnf(n % 8, vals::Cnf::OPENDRAIN));
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r.cr(crlh).modify(|w| w.set_mode(n % 8, vals::Mode::INPUT));
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}
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#[cfg(gpio_v2)]
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{
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r.pupdr().modify(|w| w.set_pupdr(n, vals::Pupdr::FLOATING));
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r.moder().modify(|w| w.set_moder(n, vals::Moder::INPUT));
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}
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});
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}
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}
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impl<'d, T: Pin> OutputPin for OutputOpenDrain<'d, T> {
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type Error = Infallible;
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/// Set the output as high.
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fn set_high(&mut self) -> Result<(), Self::Error> {
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self.pin.set_high();
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Ok(())
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}
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/// Set the output as low.
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fn set_low(&mut self) -> Result<(), Self::Error> {
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self.pin.set_low();
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Ok(())
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}
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}
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impl<'d, T: Pin> InputPin for OutputOpenDrain<'d, T> {
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type Error = Infallible;
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fn is_high(&self) -> Result<bool, Self::Error> {
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self.is_low().map(|v| !v)
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}
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fn is_low(&self) -> Result<bool, Self::Error> {
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// NOTE(safety) Atomic read
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let state = unsafe { self.pin.block().idr().read().idr(self.pin.pin() as usize) };
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Ok(state == vals::Idr::LOW)
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}
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}
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pub(crate) mod sealed {
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use super::*;
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/// Output type settings
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#[derive(Debug)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum OutputType {
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PushPull,
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OpenDrain,
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}
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pub trait Pin {
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fn pin_port(&self) -> u8;
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#[inline]
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fn _pin(&self) -> u8 {
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self.pin_port() % 16
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}
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#[inline]
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fn _port(&self) -> u8 {
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self.pin_port() / 16
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}
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#[inline]
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fn block(&self) -> gpio::Gpio {
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pac::GPIO(self._port() as _)
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}
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/// Set the output as high.
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#[inline]
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fn set_high(&self) {
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unsafe {
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let n = self._pin() as _;
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self.block().bsrr().write(|w| w.set_bs(n, true));
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}
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}
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/// Set the output as low.
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#[inline]
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fn set_low(&self) {
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unsafe {
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let n = self._pin() as _;
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self.block().bsrr().write(|w| w.set_br(n, true));
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}
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}
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#[cfg(gpio_v1)]
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unsafe fn set_as_af(&self, _af_num: u8, _af_type: OutputType) {
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panic!("F1 alternate GPIO functions not supported yet!");
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}
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#[cfg(gpio_v2)]
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unsafe fn set_as_af(&self, af_num: u8, af_type: OutputType) {
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let pin = self._pin() as usize;
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let block = self.block();
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block
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.afr(pin / 8)
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.modify(|w| w.set_afr(pin % 8, vals::Afr(af_num)));
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match af_type {
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OutputType::PushPull => {
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block.otyper().modify(|w| w.set_ot(pin, vals::Ot::PUSHPULL))
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}
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OutputType::OpenDrain => block
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.otyper()
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.modify(|w| w.set_ot(pin, vals::Ot::OPENDRAIN)),
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}
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block
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.pupdr()
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.modify(|w| w.set_pupdr(pin, vals::Pupdr::FLOATING));
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block
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.moder()
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.modify(|w| w.set_moder(pin, vals::Moder::ALTERNATE));
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}
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unsafe fn set_as_analog(&self) {
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let pin = self._pin() as usize;
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let block = self.block();
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#[cfg(gpio_v1)]
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{
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let crlh = if pin < 8 { 0 } else { 1 };
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block
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.cr(crlh)
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.modify(|w| w.set_cnf(pin % 8, vals::Cnf::PUSHPULL));
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block
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.cr(crlh)
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.modify(|w| w.set_mode(pin % 8, vals::Mode::INPUT));
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}
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#[cfg(gpio_v2)]
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block
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.moder()
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.modify(|w| w.set_moder(pin, vals::Moder::ANALOG));
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}
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#[cfg(gpio_v2)]
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unsafe fn set_speed(&self, speed: Speed) {
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let pin = self._pin() as usize;
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self.block()
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.ospeedr()
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.modify(|w| w.set_ospeedr(pin, speed.into()));
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}
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}
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pub trait OptionalPin {}
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}
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pub trait Pin: sealed::Pin + Sized {
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type ExtiChannel: crate::exti::Channel;
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/// Number of the pin within the port (0..31)
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#[inline]
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fn pin(&self) -> u8 {
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self._pin()
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}
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/// Port of the pin
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#[inline]
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fn port(&self) -> u8 {
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self._port()
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}
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/// Convert from concrete pin type PX_XX to type erased `AnyPin`.
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#[inline]
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fn degrade(self) -> AnyPin {
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AnyPin {
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pin_port: self.pin_port(),
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}
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}
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}
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// Type-erased GPIO pin
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pub struct AnyPin {
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pin_port: u8,
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}
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impl AnyPin {
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#[inline]
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pub unsafe fn steal(pin_port: u8) -> Self {
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Self { pin_port }
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}
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#[inline]
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fn _port(&self) -> u8 {
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self.pin_port / 16
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}
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#[inline]
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pub fn block(&self) -> gpio::Gpio {
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pac::GPIO(self._port() as _)
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}
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}
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unsafe_impl_unborrow!(AnyPin);
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impl Pin for AnyPin {
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type ExtiChannel = crate::exti::AnyChannel;
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}
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impl sealed::Pin for AnyPin {
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#[inline]
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fn pin_port(&self) -> u8 {
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self.pin_port
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}
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}
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// ====================
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pub trait OptionalPin: sealed::OptionalPin + Sized {
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type Pin: Pin;
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fn pin(&self) -> Option<&Self::Pin>;
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fn pin_mut(&mut self) -> Option<&mut Self::Pin>;
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/// Convert from concrete pin type PX_XX to type erased `Option<AnyPin>`.
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#[inline]
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fn degrade_optional(mut self) -> Option<AnyPin> {
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self.pin_mut()
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.map(|pin| unsafe { core::ptr::read(pin) }.degrade())
|
|
}
|
|
}
|
|
|
|
impl<T: Pin> sealed::OptionalPin for T {}
|
|
impl<T: Pin> OptionalPin for T {
|
|
type Pin = T;
|
|
|
|
#[inline]
|
|
fn pin(&self) -> Option<&T> {
|
|
Some(self)
|
|
}
|
|
|
|
#[inline]
|
|
fn pin_mut(&mut self) -> Option<&mut T> {
|
|
Some(self)
|
|
}
|
|
}
|
|
|
|
#[derive(Clone, Copy, Debug)]
|
|
pub struct NoPin;
|
|
unsafe_impl_unborrow!(NoPin);
|
|
impl sealed::OptionalPin for NoPin {}
|
|
impl OptionalPin for NoPin {
|
|
type Pin = AnyPin;
|
|
|
|
#[inline]
|
|
fn pin(&self) -> Option<&AnyPin> {
|
|
None
|
|
}
|
|
|
|
#[inline]
|
|
fn pin_mut(&mut self) -> Option<&mut AnyPin> {
|
|
None
|
|
}
|
|
}
|
|
|
|
// ====================
|
|
|
|
crate::pac::pins!(
|
|
($pin_name:ident, $port_name:ident, $port_num:expr, $pin_num:expr, $exti_ch:ident) => {
|
|
impl Pin for peripherals::$pin_name {
|
|
type ExtiChannel = peripherals::$exti_ch;
|
|
}
|
|
impl sealed::Pin for peripherals::$pin_name {
|
|
#[inline]
|
|
fn pin_port(&self) -> u8 {
|
|
$port_num * 16 + $pin_num
|
|
}
|
|
}
|
|
};
|
|
);
|
|
|
|
pub(crate) unsafe fn init() {
|
|
crate::pac::gpio_rcc! {
|
|
($en_reg:ident) => {
|
|
crate::pac::RCC.$en_reg().modify(|reg| {
|
|
crate::pac::gpio_rcc! {
|
|
($name:ident, $clock:ident, $en_reg, $rst_reg:ident, $en_fn:ident, $rst_fn:ident) => {
|
|
reg.$en_fn(true);
|
|
};
|
|
}
|
|
});
|
|
};
|
|
}
|
|
}
|