428 lines
13 KiB
Rust
428 lines
13 KiB
Rust
use chiptool::generate::CommonModule;
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use chiptool::{generate, ir, transform};
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use proc_macro2::TokenStream;
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use regex::Regex;
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use std::collections::{BTreeMap, HashMap, HashSet};
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use std::fmt::{Debug, Write as _};
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use std::fs;
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use std::fs::File;
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use std::io::Write;
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use std::path::Path;
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use std::path::PathBuf;
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use std::str::FromStr;
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mod data;
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use data::*;
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#[derive(Debug, Eq, PartialEq, Clone)]
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struct Metadata<'a> {
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name: &'a str,
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family: &'a str,
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line: &'a str,
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memory: &'a [MemoryRegion],
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peripherals: &'a [Peripheral],
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interrupts: &'a [Interrupt],
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dma_channels: &'a [DmaChannel],
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}
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pub struct Options {
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pub chips: Vec<String>,
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pub out_dir: PathBuf,
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pub data_dir: PathBuf,
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}
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pub struct Gen {
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opts: Options,
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all_peripheral_versions: HashSet<(String, String)>,
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metadata_dedup: HashMap<String, String>,
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}
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impl Gen {
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pub fn new(opts: Options) -> Self {
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Self {
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opts,
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all_peripheral_versions: HashSet::new(),
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metadata_dedup: HashMap::new(),
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}
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}
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fn gen_chip(&mut self, chip_core_name: &str, chip: &Chip, core: &Core, core_index: usize) {
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let mut ir = ir::IR::new();
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let mut dev = ir::Device {
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interrupts: Vec::new(),
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peripherals: Vec::new(),
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};
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let mut peripheral_versions: BTreeMap<String, String> = BTreeMap::new();
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let gpio_base = core
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.peripherals
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.iter()
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.find(|p| p.name == "GPIOA")
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.unwrap()
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.address as u32;
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let gpio_stride = 0x400;
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for p in &core.peripherals {
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let mut ir_peri = ir::Peripheral {
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name: p.name.clone(),
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array: None,
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base_address: p.address,
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block: None,
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description: None,
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interrupts: HashMap::new(),
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};
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if let Some(bi) = &p.registers {
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if let Some(old_version) =
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peripheral_versions.insert(bi.kind.clone(), bi.version.clone())
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{
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if old_version != bi.version {
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panic!(
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"Peripheral {} has multiple versions: {} and {}",
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bi.kind, old_version, bi.version
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);
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}
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}
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ir_peri.block = Some(format!("{}::{}", bi.kind, bi.block));
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if bi.kind == "gpio" {
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assert_eq!(0, (p.address as u32 - gpio_base) % gpio_stride);
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}
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}
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dev.peripherals.push(ir_peri);
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}
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for irq in &core.interrupts {
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dev.interrupts.push(ir::Interrupt {
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name: irq.name.clone(),
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description: None,
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value: irq.number,
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});
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}
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ir.devices.insert("".to_string(), dev);
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let mut extra = format!(
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"pub fn GPIO(n: usize) -> gpio::Gpio {{
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gpio::Gpio(({} + {}*n) as _)
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}}",
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gpio_base, gpio_stride,
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);
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for (module, version) in &peripheral_versions {
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self.all_peripheral_versions
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.insert((module.clone(), version.clone()));
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write!(
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&mut extra,
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"#[path=\"../../peripherals/{}_{}.rs\"] pub mod {};\n",
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module, version, module
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)
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.unwrap();
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}
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write!(
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&mut extra,
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"pub const CORE_INDEX: usize = {};\n",
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core_index
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)
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.unwrap();
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let flash = chip.memory.iter().find(|r| r.name == "BANK_1").unwrap();
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write!(
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&mut extra,
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"pub const FLASH_BASE: usize = {};\n",
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flash.address,
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)
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.unwrap();
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write!(
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&mut extra,
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"pub const FLASH_SIZE: usize = {};\n",
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flash.size,
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)
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.unwrap();
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if let Some(settings) = &flash.settings {
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write!(
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&mut extra,
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"pub const ERASE_SIZE: usize = {};\n",
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settings.erase_size,
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)
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.unwrap();
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write!(
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&mut extra,
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"pub const WRITE_SIZE: usize = {};\n",
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settings.write_size,
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)
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.unwrap();
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write!(
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&mut extra,
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"pub const ERASE_VALUE: u8 = {};\n",
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settings.erase_value,
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)
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.unwrap();
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}
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// Cleanups!
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transform::sort::Sort {}.run(&mut ir).unwrap();
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transform::Sanitize {}.run(&mut ir).unwrap();
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// ==============================
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// Setup chip dir
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let chip_dir = self
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.opts
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.out_dir
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.join("src/chips")
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.join(chip_core_name.to_ascii_lowercase());
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fs::create_dir_all(&chip_dir).unwrap();
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// ==============================
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// generate pac.rs
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let data = generate::render(&ir, &gen_opts()).unwrap().to_string();
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let data = data.replace("] ", "]\n");
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// Remove inner attributes like #![no_std]
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let data = Regex::new("# *! *\\[.*\\]").unwrap().replace_all(&data, "");
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let mut file = File::create(chip_dir.join("pac.rs")).unwrap();
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file.write_all(data.as_bytes()).unwrap();
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file.write_all(extra.as_bytes()).unwrap();
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let mut device_x = String::new();
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for irq in &core.interrupts {
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write!(&mut device_x, "PROVIDE({} = DefaultHandler);\n", irq.name).unwrap();
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}
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// ==============================
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// generate metadata.rs
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// (peripherals, interrupts, dma_channels) are often equal across multiple chips.
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// To reduce bloat, deduplicate them.
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let mut data = String::new();
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write!(
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&mut data,
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"
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const PERIPHERALS: &'static [Peripheral] = {};
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const INTERRUPTS: &'static [Interrupt] = {};
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const DMA_CHANNELS: &'static [DmaChannel] = {};
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",
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stringify(&core.peripherals),
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stringify(&core.interrupts),
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stringify(&core.dma_channels),
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)
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.unwrap();
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let out_dir = self.opts.out_dir.clone();
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let n = self.metadata_dedup.len();
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let deduped_file = self.metadata_dedup.entry(data.clone()).or_insert_with(|| {
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let file = format!("metadata_{:04}.rs", n);
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let path = out_dir.join("src/chips").join(&file);
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fs::write(path, data).unwrap();
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file
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});
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let data = format!(
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"include!(\"../{}\");
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pub const METADATA: Metadata = Metadata {{
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name: {:?},
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family: {:?},
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line: {:?},
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memory: {},
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peripherals: PERIPHERALS,
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interrupts: INTERRUPTS,
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dma_channels: DMA_CHANNELS,
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}};",
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deduped_file,
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&chip.name,
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&chip.family,
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&chip.line,
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stringify(&chip.memory),
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);
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let mut file = File::create(chip_dir.join("metadata.rs")).unwrap();
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file.write_all(data.as_bytes()).unwrap();
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// ==============================
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// generate device.x
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File::create(chip_dir.join("device.x"))
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.unwrap()
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.write_all(device_x.as_bytes())
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.unwrap();
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// ==============================
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// generate default memory.x
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gen_memory_x(&chip_dir, &chip);
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}
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fn load_chip(&mut self, name: &str) -> Chip {
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let chip_path = self
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.opts
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.data_dir
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.join("chips")
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.join(&format!("{}.json", name));
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let chip = fs::read(chip_path).expect(&format!("Could not load chip {}", name));
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serde_yaml::from_slice(&chip).unwrap()
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}
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pub fn gen(&mut self) {
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fs::create_dir_all(self.opts.out_dir.join("src/peripherals")).unwrap();
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fs::create_dir_all(self.opts.out_dir.join("src/chips")).unwrap();
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let mut chip_core_names: Vec<String> = Vec::new();
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for chip_name in &self.opts.chips.clone() {
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println!("Generating {}...", chip_name);
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let mut chip = self.load_chip(chip_name);
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// Cleanup
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for core in &mut chip.cores {
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for irq in &mut core.interrupts {
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irq.name = irq.name.to_ascii_uppercase();
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}
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for p in &mut core.peripherals {
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for irq in &mut p.interrupts {
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irq.interrupt = irq.interrupt.to_ascii_uppercase();
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}
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}
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}
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// Generate
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for (core_index, core) in chip.cores.iter().enumerate() {
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let chip_core_name = match chip.cores.len() {
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1 => chip_name.clone(),
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_ => format!("{}-{}", chip_name, core.name),
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};
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chip_core_names.push(chip_core_name.clone());
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self.gen_chip(&chip_core_name, &chip, core, core_index)
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}
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}
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for (module, version) in &self.all_peripheral_versions {
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println!("loading {} {}", module, version);
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let regs_path = Path::new(&self.opts.data_dir)
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.join("registers")
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.join(&format!("{}_{}.yaml", module, version));
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let mut ir: ir::IR = serde_yaml::from_reader(File::open(regs_path).unwrap()).unwrap();
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transform::expand_extends::ExpandExtends {}
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.run(&mut ir)
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.unwrap();
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transform::map_names(&mut ir, |k, s| match k {
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transform::NameKind::Block => *s = format!("{}", s),
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transform::NameKind::Fieldset => *s = format!("regs::{}", s),
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transform::NameKind::Enum => *s = format!("vals::{}", s),
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_ => {}
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});
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transform::sort::Sort {}.run(&mut ir).unwrap();
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transform::Sanitize {}.run(&mut ir).unwrap();
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let items = generate::render(&ir, &gen_opts()).unwrap();
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let mut file = File::create(
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self.opts
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.out_dir
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.join("src/peripherals")
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.join(format!("{}_{}.rs", module, version)),
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)
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.unwrap();
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let data = items.to_string().replace("] ", "]\n");
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// Remove inner attributes like #![no_std]
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let re = Regex::new("# *! *\\[.*\\]").unwrap();
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let data = re.replace_all(&data, "");
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file.write_all(data.as_bytes()).unwrap();
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}
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// Generate Cargo.toml
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const BUILDDEP_BEGIN: &[u8] = b"# BEGIN BUILD DEPENDENCIES";
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const BUILDDEP_END: &[u8] = b"# END BUILD DEPENDENCIES";
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let mut contents = include_bytes!("../../stm32-metapac/Cargo.toml").to_vec();
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let begin = bytes_find(&contents, BUILDDEP_BEGIN).unwrap();
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let end = bytes_find(&contents, BUILDDEP_END).unwrap() + BUILDDEP_END.len();
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contents.drain(begin..end);
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fs::write(self.opts.out_dir.join("Cargo.toml"), contents).unwrap();
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// copy misc files
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fs::write(
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self.opts.out_dir.join("build.rs"),
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include_bytes!("../../stm32-metapac/build_pregenerated.rs"),
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)
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.unwrap();
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fs::write(
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self.opts.out_dir.join("src/lib.rs"),
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include_bytes!("../../stm32-metapac/src/lib.rs"),
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)
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.unwrap();
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fs::write(
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self.opts.out_dir.join("src/common.rs"),
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chiptool::generate::COMMON_MODULE,
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)
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.unwrap();
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fs::write(
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self.opts.out_dir.join("src/metadata.rs"),
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include_bytes!("../../stm32-metapac/src/metadata.rs"),
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)
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.unwrap();
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}
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}
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fn bytes_find(haystack: &[u8], needle: &[u8]) -> Option<usize> {
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haystack
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.windows(needle.len())
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.position(|window| window == needle)
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}
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fn stringify<T: Debug>(metadata: T) -> String {
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let mut metadata = format!("{:?}", metadata);
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if metadata.starts_with('[') {
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metadata = format!("&{}", metadata);
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}
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metadata = metadata.replace(": [", ": &[");
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metadata = metadata.replace("kind: Ram", "kind: MemoryRegionKind::Ram");
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metadata = metadata.replace("kind: Flash", "kind: MemoryRegionKind::Flash");
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metadata
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}
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fn gen_opts() -> generate::Options {
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generate::Options {
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common_module: CommonModule::External(TokenStream::from_str("crate::common").unwrap()),
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}
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}
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fn gen_memory_x(out_dir: &PathBuf, chip: &Chip) {
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let mut memory_x = String::new();
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let flash = chip.memory.iter().find(|r| r.name == "BANK_1").unwrap();
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let ram = chip.memory.iter().find(|r| r.name == "SRAM").unwrap();
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write!(memory_x, "MEMORY\n{{\n").unwrap();
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write!(
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memory_x,
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" FLASH : ORIGIN = 0x{:x}, LENGTH = {}\n",
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flash.address, flash.size,
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)
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.unwrap();
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write!(
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memory_x,
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" RAM : ORIGIN = 0x{:x}, LENGTH = {}\n",
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ram.address, ram.size,
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)
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.unwrap();
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write!(memory_x, "}}").unwrap();
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fs::create_dir_all(out_dir.join("memory_x")).unwrap();
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let mut file = File::create(out_dir.join("memory_x").join("memory.x")).unwrap();
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file.write_all(memory_x.as_bytes()).unwrap();
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}
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