138 lines
4.0 KiB
Rust
138 lines
4.0 KiB
Rust
use embassy_hal_internal::into_ref;
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use embedded_hal_02::blocking::delay::DelayUs;
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use crate::adc::{Adc, AdcPin, Instance, SampleTime};
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use crate::rcc::get_freqs;
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use crate::time::Hertz;
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use crate::Peripheral;
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pub const VDDA_CALIB_MV: u32 = 3300;
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pub const ADC_MAX: u32 = (1 << 12) - 1;
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// No calibration data for F103, voltage should be 1.2v
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pub const VREF_INT: u32 = 1200;
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pub struct Vref;
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impl<T: Instance> AdcPin<T> for Vref {}
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impl<T: Instance> super::sealed::AdcPin<T> for Vref {
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fn channel(&self) -> u8 {
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17
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}
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}
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pub struct Temperature;
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impl<T: Instance> AdcPin<T> for Temperature {}
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impl<T: Instance> super::sealed::AdcPin<T> for Temperature {
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fn channel(&self) -> u8 {
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16
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}
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}
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impl<'d, T: Instance> Adc<'d, T> {
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pub fn new(adc: impl Peripheral<P = T> + 'd, delay: &mut impl DelayUs<u32>) -> Self {
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into_ref!(adc);
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T::enable();
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T::reset();
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T::regs().cr2().modify(|reg| reg.set_adon(true));
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// 11.4: Before starting a calibration, the ADC must have been in power-on state (ADON bit = ‘1’)
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// for at least two ADC clock cycles
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delay.delay_us((1_000_000 * 2) / Self::freq().0 + 1);
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// Reset calibration
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T::regs().cr2().modify(|reg| reg.set_rstcal(true));
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while T::regs().cr2().read().rstcal() {
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// spin
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}
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// Calibrate
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T::regs().cr2().modify(|reg| reg.set_cal(true));
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while T::regs().cr2().read().cal() {
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// spin
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}
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// One cycle after calibration
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delay.delay_us((1_000_000) / Self::freq().0 + 1);
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Self {
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adc,
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sample_time: Default::default(),
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}
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}
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fn freq() -> Hertz {
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unsafe { get_freqs() }.adc
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}
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pub fn sample_time_for_us(&self, us: u32) -> SampleTime {
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match us * Self::freq().0 / 1_000_000 {
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0..=1 => SampleTime::Cycles1_5,
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2..=7 => SampleTime::Cycles7_5,
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8..=13 => SampleTime::Cycles13_5,
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14..=28 => SampleTime::Cycles28_5,
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29..=41 => SampleTime::Cycles41_5,
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42..=55 => SampleTime::Cycles55_5,
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56..=71 => SampleTime::Cycles71_5,
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_ => SampleTime::Cycles239_5,
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}
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}
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pub fn enable_vref(&self, _delay: &mut impl DelayUs<u32>) -> Vref {
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T::regs().cr2().modify(|reg| {
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reg.set_tsvrefe(true);
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});
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Vref {}
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}
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pub fn enable_temperature(&self) -> Temperature {
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T::regs().cr2().modify(|reg| {
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reg.set_tsvrefe(true);
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});
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Temperature {}
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}
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pub fn set_sample_time(&mut self, sample_time: SampleTime) {
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self.sample_time = sample_time;
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}
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/// Perform a single conversion.
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fn convert(&mut self) -> u16 {
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T::regs().cr2().modify(|reg| {
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reg.set_adon(true);
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reg.set_swstart(true);
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});
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while T::regs().cr2().read().swstart() {}
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while !T::regs().sr().read().eoc() {}
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T::regs().dr().read().0 as u16
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}
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pub fn read(&mut self, pin: &mut impl AdcPin<T>) -> u16 {
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Self::set_channel_sample_time(pin.channel(), self.sample_time);
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T::regs().cr1().modify(|reg| {
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reg.set_scan(false);
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reg.set_discen(false);
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});
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T::regs().sqr1().modify(|reg| reg.set_l(0));
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T::regs().cr2().modify(|reg| {
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reg.set_cont(false);
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reg.set_exttrig(true);
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reg.set_swstart(false);
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reg.set_extsel(crate::pac::adc::vals::Extsel::SWSTART);
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});
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// Configure the channel to sample
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T::regs().sqr3().write(|reg| reg.set_sq(0, pin.channel()));
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self.convert()
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}
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fn set_channel_sample_time(ch: u8, sample_time: SampleTime) {
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let sample_time = sample_time.into();
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if ch <= 9 {
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T::regs().smpr2().modify(|reg| reg.set_smp(ch as _, sample_time));
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} else {
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T::regs().smpr1().modify(|reg| reg.set_smp((ch - 10) as _, sample_time));
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}
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}
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}
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