53 lines
1.7 KiB
Rust
53 lines
1.7 KiB
Rust
#![no_std]
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#![no_main]
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#![feature(type_alias_impl_trait)]
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use core::convert::TryFrom;
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use defmt::*;
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use embassy_executor::executor::Spawner;
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use embassy_executor::time::{Duration, Timer};
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use embassy_stm32::rcc::{
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APBPrescaler, ClockSrc, HSEConfig, HSESrc, PLL48Div, PLLConfig, PLLMainDiv, PLLMul, PLLPreDiv, PLLSrc,
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};
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use embassy_stm32::time::Hertz;
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use embassy_stm32::{Config, Peripherals};
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use {defmt_rtt as _, panic_probe as _};
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// Example config for maximum performance on a NUCLEO-F207ZG board
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fn config() -> Config {
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let mut config = Config::default();
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// By default, HSE on the board comes from a 8 MHz clock signal (not a crystal)
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config.rcc.hse = Some(HSEConfig {
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frequency: Hertz(8_000_000),
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source: HSESrc::Bypass,
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});
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// PLL uses HSE as the clock source
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config.rcc.pll_mux = PLLSrc::HSE;
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config.rcc.pll = PLLConfig {
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// 8 MHz clock source / 8 = 1 MHz PLL input
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pre_div: unwrap!(PLLPreDiv::try_from(8)),
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// 1 MHz PLL input * 240 = 240 MHz PLL VCO
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mul: unwrap!(PLLMul::try_from(240)),
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// 240 MHz PLL VCO / 2 = 120 MHz main PLL output
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main_div: PLLMainDiv::Div2,
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// 240 MHz PLL VCO / 5 = 48 MHz PLL48 output
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pll48_div: unwrap!(PLL48Div::try_from(5)),
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};
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// System clock comes from PLL (= the 120 MHz main PLL output)
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config.rcc.mux = ClockSrc::PLL;
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// 120 MHz / 4 = 30 MHz APB1 frequency
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config.rcc.apb1_pre = APBPrescaler::Div4;
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// 120 MHz / 2 = 60 MHz APB2 frequency
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config.rcc.apb2_pre = APBPrescaler::Div2;
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config
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}
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#[embassy_executor::main(config = "config()")]
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async fn main(_spawner: Spawner, _p: Peripherals) {
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loop {
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Timer::after(Duration::from_millis(1000)).await;
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info!("1s elapsed");
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}
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}
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