379 lines
11 KiB
Rust
379 lines
11 KiB
Rust
//! Pulse Width Modulation (PWM)
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use embassy_hal_internal::{into_ref, Peripheral, PeripheralRef};
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use fixed::traits::ToFixed;
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use fixed::FixedU16;
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use pac::pwm::regs::{ChDiv, Intr};
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use pac::pwm::vals::Divmode;
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use crate::gpio::sealed::Pin as _;
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use crate::gpio::{AnyPin, Pin as GpioPin};
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use crate::{pac, peripherals, RegExt};
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/// The configuration of a PWM slice.
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/// Note the period in clock cycles of a slice can be computed as:
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/// `(top + 1) * (phase_correct ? 1 : 2) * divider`
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#[non_exhaustive]
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#[derive(Clone)]
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pub struct Config {
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/// Inverts the PWM output signal on channel A.
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pub invert_a: bool,
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/// Inverts the PWM output signal on channel B.
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pub invert_b: bool,
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/// Enables phase-correct mode for PWM operation.
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/// In phase-correct mode, the PWM signal is generated in such a way that
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/// the pulse is always centered regardless of the duty cycle.
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/// The output frequency is halved when phase-correct mode is enabled.
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pub phase_correct: bool,
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/// Enables the PWM slice, allowing it to generate an output.
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pub enable: bool,
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/// A fractional clock divider, represented as a fixed-point number with
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/// 8 integer bits and 4 fractional bits. It allows precise control over
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/// the PWM output frequency by gating the PWM counter increment.
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/// A higher value will result in a slower output frequency.
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pub divider: fixed::FixedU16<fixed::types::extra::U4>,
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/// The output on channel A goes high when `compare_a` is higher than the
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/// counter. A compare of 0 will produce an always low output, while a
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/// compare of `top + 1` will produce an always high output.
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pub compare_a: u16,
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/// The output on channel B goes high when `compare_b` is higher than the
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/// counter. A compare of 0 will produce an always low output, while a
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/// compare of `top + 1` will produce an always high output.
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pub compare_b: u16,
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/// The point at which the counter wraps, representing the maximum possible
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/// period. The counter will either wrap to 0 or reverse depending on the
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/// setting of `phase_correct`.
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pub top: u16,
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}
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impl Default for Config {
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fn default() -> Self {
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Self {
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invert_a: false,
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invert_b: false,
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phase_correct: false,
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enable: true, // differs from reset value
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divider: 1.to_fixed(),
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compare_a: 0,
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compare_b: 0,
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top: 0xffff,
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}
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}
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}
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/// PWM input mode.
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pub enum InputMode {
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/// Level mode.
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Level,
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/// Rising edge mode.
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RisingEdge,
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/// Falling edge mode.
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FallingEdge,
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}
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impl From<InputMode> for Divmode {
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fn from(value: InputMode) -> Self {
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match value {
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InputMode::Level => Divmode::LEVEL,
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InputMode::RisingEdge => Divmode::RISE,
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InputMode::FallingEdge => Divmode::FALL,
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}
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}
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}
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/// PWM driver.
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pub struct Pwm<'d, T: Channel> {
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inner: PeripheralRef<'d, T>,
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pin_a: Option<PeripheralRef<'d, AnyPin>>,
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pin_b: Option<PeripheralRef<'d, AnyPin>>,
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}
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impl<'d, T: Channel> Pwm<'d, T> {
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fn new_inner(
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inner: impl Peripheral<P = T> + 'd,
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a: Option<PeripheralRef<'d, AnyPin>>,
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b: Option<PeripheralRef<'d, AnyPin>>,
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config: Config,
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divmode: Divmode,
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) -> Self {
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into_ref!(inner);
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let p = inner.regs();
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p.csr().modify(|w| {
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w.set_divmode(divmode);
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w.set_en(false);
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});
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p.ctr().write(|w| w.0 = 0);
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Self::configure(p, &config);
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if let Some(pin) = &a {
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pin.gpio().ctrl().write(|w| w.set_funcsel(4));
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}
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if let Some(pin) = &b {
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pin.gpio().ctrl().write(|w| w.set_funcsel(4));
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}
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Self {
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inner,
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pin_a: a.into(),
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pin_b: b.into(),
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}
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}
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/// Create PWM driver without any configured pins.
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#[inline]
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pub fn new_free(inner: impl Peripheral<P = T> + 'd, config: Config) -> Self {
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Self::new_inner(inner, None, None, config, Divmode::DIV)
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}
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/// Create PWM driver with a single 'a' as output.
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#[inline]
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pub fn new_output_a(
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inner: impl Peripheral<P = T> + 'd,
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a: impl Peripheral<P = impl PwmPinA<T>> + 'd,
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config: Config,
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) -> Self {
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into_ref!(a);
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Self::new_inner(inner, Some(a.map_into()), None, config, Divmode::DIV)
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}
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/// Create PWM driver with a single 'b' pin as output.
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#[inline]
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pub fn new_output_b(
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inner: impl Peripheral<P = T> + 'd,
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b: impl Peripheral<P = impl PwmPinB<T>> + 'd,
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config: Config,
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) -> Self {
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into_ref!(b);
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Self::new_inner(inner, None, Some(b.map_into()), config, Divmode::DIV)
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}
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/// Create PWM driver with a 'a' and 'b' pins as output.
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#[inline]
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pub fn new_output_ab(
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inner: impl Peripheral<P = T> + 'd,
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a: impl Peripheral<P = impl PwmPinA<T>> + 'd,
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b: impl Peripheral<P = impl PwmPinB<T>> + 'd,
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config: Config,
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) -> Self {
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into_ref!(a, b);
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Self::new_inner(inner, Some(a.map_into()), Some(b.map_into()), config, Divmode::DIV)
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}
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/// Create PWM driver with a single 'b' as input pin.
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#[inline]
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pub fn new_input(
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inner: impl Peripheral<P = T> + 'd,
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b: impl Peripheral<P = impl PwmPinB<T>> + 'd,
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mode: InputMode,
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config: Config,
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) -> Self {
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into_ref!(b);
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Self::new_inner(inner, None, Some(b.map_into()), config, mode.into())
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}
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/// Create PWM driver with a 'a' and 'b' pins in the desired input mode.
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#[inline]
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pub fn new_output_input(
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inner: impl Peripheral<P = T> + 'd,
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a: impl Peripheral<P = impl PwmPinA<T>> + 'd,
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b: impl Peripheral<P = impl PwmPinB<T>> + 'd,
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mode: InputMode,
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config: Config,
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) -> Self {
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into_ref!(a, b);
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Self::new_inner(inner, Some(a.map_into()), Some(b.map_into()), config, mode.into())
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}
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/// Set the PWM config.
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pub fn set_config(&mut self, config: &Config) {
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Self::configure(self.inner.regs(), config);
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}
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fn configure(p: pac::pwm::Channel, config: &Config) {
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if config.divider > FixedU16::<fixed::types::extra::U4>::from_bits(0xFF_F) {
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panic!("Requested divider is too large");
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}
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p.div().write_value(ChDiv(config.divider.to_bits() as u32));
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p.cc().write(|w| {
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w.set_a(config.compare_a);
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w.set_b(config.compare_b);
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});
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p.top().write(|w| w.set_top(config.top));
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p.csr().modify(|w| {
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w.set_a_inv(config.invert_a);
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w.set_b_inv(config.invert_b);
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w.set_ph_correct(config.phase_correct);
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w.set_en(config.enable);
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});
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}
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/// Advances a slice’s output phase by one count while it is running
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/// by inserting a pulse into the clock enable. The counter
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/// will not count faster than once per cycle.
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#[inline]
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pub fn phase_advance(&mut self) {
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let p = self.inner.regs();
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p.csr().write_set(|w| w.set_ph_adv(true));
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while p.csr().read().ph_adv() {}
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}
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/// Retards a slice’s output phase by one count while it is running
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/// by deleting a pulse from the clock enable. The counter will not
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/// count backward when clock enable is permenantly low.
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#[inline]
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pub fn phase_retard(&mut self) {
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let p = self.inner.regs();
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p.csr().write_set(|w| w.set_ph_ret(true));
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while p.csr().read().ph_ret() {}
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}
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/// Read PWM counter.
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#[inline]
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pub fn counter(&self) -> u16 {
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self.inner.regs().ctr().read().ctr()
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}
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/// Write PWM counter.
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#[inline]
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pub fn set_counter(&self, ctr: u16) {
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self.inner.regs().ctr().write(|w| w.set_ctr(ctr))
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}
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/// Wait for channel interrupt.
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#[inline]
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pub fn wait_for_wrap(&mut self) {
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while !self.wrapped() {}
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self.clear_wrapped();
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}
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/// Check if interrupt for channel is set.
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#[inline]
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pub fn wrapped(&mut self) -> bool {
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pac::PWM.intr().read().0 & self.bit() != 0
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}
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#[inline]
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/// Clear interrupt flag.
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pub fn clear_wrapped(&mut self) {
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pac::PWM.intr().write_value(Intr(self.bit() as _));
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}
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#[inline]
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fn bit(&self) -> u32 {
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1 << self.inner.number() as usize
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}
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}
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/// Batch representation of PWM channels.
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pub struct PwmBatch(u32);
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impl PwmBatch {
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#[inline]
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/// Enable a PWM channel in this batch.
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pub fn enable(&mut self, pwm: &Pwm<'_, impl Channel>) {
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self.0 |= pwm.bit();
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}
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#[inline]
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/// Enable channels in this batch in a PWM.
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pub fn set_enabled(enabled: bool, batch: impl FnOnce(&mut PwmBatch)) {
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let mut en = PwmBatch(0);
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batch(&mut en);
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if enabled {
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pac::PWM.en().write_set(|w| w.0 = en.0);
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} else {
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pac::PWM.en().write_clear(|w| w.0 = en.0);
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}
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}
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}
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impl<'d, T: Channel> Drop for Pwm<'d, T> {
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fn drop(&mut self) {
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self.inner.regs().csr().write_clear(|w| w.set_en(false));
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if let Some(pin) = &self.pin_a {
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pin.gpio().ctrl().write(|w| w.set_funcsel(31));
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}
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if let Some(pin) = &self.pin_b {
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pin.gpio().ctrl().write(|w| w.set_funcsel(31));
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}
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}
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}
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mod sealed {
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pub trait Channel {}
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}
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/// PWM Channel.
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pub trait Channel: Peripheral<P = Self> + sealed::Channel + Sized + 'static {
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/// Channel number.
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fn number(&self) -> u8;
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/// Channel register block.
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fn regs(&self) -> pac::pwm::Channel {
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pac::PWM.ch(self.number() as _)
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}
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}
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macro_rules! channel {
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($name:ident, $num:expr) => {
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impl sealed::Channel for peripherals::$name {}
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impl Channel for peripherals::$name {
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fn number(&self) -> u8 {
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$num
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}
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}
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};
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}
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channel!(PWM_CH0, 0);
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channel!(PWM_CH1, 1);
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channel!(PWM_CH2, 2);
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channel!(PWM_CH3, 3);
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channel!(PWM_CH4, 4);
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channel!(PWM_CH5, 5);
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channel!(PWM_CH6, 6);
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channel!(PWM_CH7, 7);
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/// PWM Pin A.
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pub trait PwmPinA<T: Channel>: GpioPin {}
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/// PWM Pin B.
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pub trait PwmPinB<T: Channel>: GpioPin {}
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macro_rules! impl_pin {
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($pin:ident, $channel:ident, $kind:ident) => {
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impl $kind<peripherals::$channel> for peripherals::$pin {}
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};
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}
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impl_pin!(PIN_0, PWM_CH0, PwmPinA);
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impl_pin!(PIN_1, PWM_CH0, PwmPinB);
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impl_pin!(PIN_2, PWM_CH1, PwmPinA);
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impl_pin!(PIN_3, PWM_CH1, PwmPinB);
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impl_pin!(PIN_4, PWM_CH2, PwmPinA);
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impl_pin!(PIN_5, PWM_CH2, PwmPinB);
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impl_pin!(PIN_6, PWM_CH3, PwmPinA);
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impl_pin!(PIN_7, PWM_CH3, PwmPinB);
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impl_pin!(PIN_8, PWM_CH4, PwmPinA);
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impl_pin!(PIN_9, PWM_CH4, PwmPinB);
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impl_pin!(PIN_10, PWM_CH5, PwmPinA);
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impl_pin!(PIN_11, PWM_CH5, PwmPinB);
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impl_pin!(PIN_12, PWM_CH6, PwmPinA);
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impl_pin!(PIN_13, PWM_CH6, PwmPinB);
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impl_pin!(PIN_14, PWM_CH7, PwmPinA);
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impl_pin!(PIN_15, PWM_CH7, PwmPinB);
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impl_pin!(PIN_16, PWM_CH0, PwmPinA);
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impl_pin!(PIN_17, PWM_CH0, PwmPinB);
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impl_pin!(PIN_18, PWM_CH1, PwmPinA);
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impl_pin!(PIN_19, PWM_CH1, PwmPinB);
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impl_pin!(PIN_20, PWM_CH2, PwmPinA);
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impl_pin!(PIN_21, PWM_CH2, PwmPinB);
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impl_pin!(PIN_22, PWM_CH3, PwmPinA);
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impl_pin!(PIN_23, PWM_CH3, PwmPinB);
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impl_pin!(PIN_24, PWM_CH4, PwmPinA);
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impl_pin!(PIN_25, PWM_CH4, PwmPinB);
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impl_pin!(PIN_26, PWM_CH5, PwmPinA);
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impl_pin!(PIN_27, PWM_CH5, PwmPinB);
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impl_pin!(PIN_28, PWM_CH6, PwmPinA);
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impl_pin!(PIN_29, PWM_CH6, PwmPinB);
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