807 lines
27 KiB
Rust
807 lines
27 KiB
Rust
use chiptool::generate::CommonModule;
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use chiptool::ir::IR;
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use regex::Regex;
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use serde::Deserialize;
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use std::collections::{BTreeMap, HashMap, HashSet};
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use std::env;
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use std::fmt::Write as _;
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use std::fs;
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use std::fs::File;
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use std::io::Write;
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use std::path::Path;
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use std::path::PathBuf;
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use chiptool::util::ToSanitizedSnakeCase;
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use chiptool::{generate, ir, transform};
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#[derive(Debug, Eq, PartialEq, Clone, Deserialize)]
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pub struct Chip {
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pub name: String,
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pub family: String,
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pub line: String,
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pub cores: Vec<Core>,
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pub flash: Memory,
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pub ram: Memory,
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pub packages: Vec<Package>,
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}
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#[derive(Debug, Eq, PartialEq, Clone, Deserialize)]
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pub struct Memory {
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pub bytes: u32,
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pub regions: HashMap<String, MemoryRegion>,
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}
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#[derive(Debug, Eq, PartialEq, Clone, Deserialize)]
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pub struct MemoryRegion {
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pub base: u32,
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pub bytes: Option<u32>,
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}
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#[derive(Debug, Eq, PartialEq, Clone, Deserialize)]
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pub struct Core {
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pub name: String,
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pub peripherals: BTreeMap<String, Peripheral>,
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pub interrupts: BTreeMap<String, u32>,
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pub dma_channels: BTreeMap<String, DmaChannel>,
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}
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#[derive(Debug, Eq, PartialEq, Clone, Deserialize)]
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pub struct Package {
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pub name: String,
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pub package: String,
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}
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#[derive(Debug, Eq, PartialEq, Clone, Deserialize)]
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pub struct Peripheral {
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pub address: u64,
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#[serde(default)]
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pub kind: Option<String>,
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#[serde(default)]
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pub block: Option<String>,
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#[serde(default)]
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pub clock: Option<String>,
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#[serde(default)]
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pub pins: Vec<Pin>,
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#[serde(default)]
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pub dma_channels: BTreeMap<String, Vec<PeripheralDmaChannel>>,
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#[serde(default)]
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pub interrupts: BTreeMap<String, String>,
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}
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#[derive(Debug, Eq, PartialEq, Clone, Deserialize)]
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pub struct Pin {
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pub pin: String,
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pub signal: String,
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pub af: Option<String>,
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}
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#[derive(Debug, Eq, PartialEq, Clone, Deserialize)]
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pub struct DmaChannel {
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pub dma: String,
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pub channel: u32,
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pub dmamux: Option<String>,
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pub dmamux_channel: Option<u32>,
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}
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#[derive(Debug, Eq, PartialEq, Clone, Deserialize, Hash)]
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pub struct PeripheralDmaChannel {
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pub channel: Option<String>,
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pub dmamux: Option<String>,
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pub request: Option<u32>,
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}
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struct BlockInfo {
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/// usart_v1/USART -> usart
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module: String,
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/// usart_v1/USART -> v1
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version: String,
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/// usart_v1/USART -> USART
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block: String,
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}
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impl BlockInfo {
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fn parse(s: &str) -> Self {
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let mut s = s.split("/");
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let module = s.next().unwrap();
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let block = s.next().unwrap();
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assert!(s.next().is_none());
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let mut s = module.split("_");
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let module = s.next().unwrap();
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let version = s.next().unwrap();
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assert!(s.next().is_none());
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Self {
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module: module.to_string(),
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version: version.to_string(),
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block: block.to_string(),
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}
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}
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}
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fn find_reg<'c>(rcc: &'c ir::IR, reg_regex: &str, field_name: &str) -> Option<(&'c str, &'c str)> {
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let reg_regex = Regex::new(reg_regex).unwrap();
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for (name, fieldset) in &rcc.fieldsets {
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// Workaround for some families that prefix register aliases with C1_, which does
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// not help matching for clock name.
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if !name.starts_with("C1") && !name.starts_with("C2") && reg_regex.is_match(name) {
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for field in &fieldset.fields {
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if field_name == field.name {
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return Some((name.as_str(), field.name.as_str()));
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}
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}
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}
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}
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None
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}
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fn make_peripheral_counts(out: &mut String, data: &BTreeMap<String, u8>) {
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write!(
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out,
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"#[macro_export]
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macro_rules! peripheral_count {{
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"
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)
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.unwrap();
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for (name, count) in data {
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write!(out, "({}) => ({});\n", name, count,).unwrap();
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}
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write!(out, " }}\n").unwrap();
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}
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fn make_dma_channel_counts(out: &mut String, data: &BTreeMap<String, u8>) {
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write!(
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out,
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"#[macro_export]
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macro_rules! dma_channels_count {{
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"
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)
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.unwrap();
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for (name, count) in data {
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write!(out, "({}) => ({});\n", name, count,).unwrap();
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}
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write!(out, " }}\n").unwrap();
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}
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fn make_table(out: &mut String, name: &str, data: &Vec<Vec<String>>) {
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write!(
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out,
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"#[macro_export]
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macro_rules! {} {{
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($($pat:tt => $code:tt;)*) => {{
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macro_rules! __{}_inner {{
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$(($pat) => $code;)*
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($_:tt) => {{}}
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}}
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",
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name, name
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)
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.unwrap();
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for row in data {
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write!(out, " __{}_inner!(({}));\n", name, row.join(",")).unwrap();
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}
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write!(
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out,
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" }};
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}}"
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)
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.unwrap();
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}
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pub struct Options {
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pub chips: Vec<String>,
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pub out_dir: PathBuf,
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pub data_dir: PathBuf,
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}
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pub fn gen(options: Options) {
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let generate_opts = generate::Options {
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common_module: CommonModule::Builtin,
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};
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let out_dir = options.out_dir;
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let data_dir = options.data_dir;
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fs::create_dir_all(out_dir.join("src/peripherals")).unwrap();
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fs::create_dir_all(out_dir.join("src/chips")).unwrap();
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println!("cwd: {:?}", env::current_dir());
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let mut all_peripheral_versions: HashSet<(String, String)> = HashSet::new();
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let mut chip_cores: BTreeMap<String, Option<String>> = BTreeMap::new();
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for chip_name in &options.chips {
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let mut s = chip_name.split('_');
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let mut chip_name: String = s.next().unwrap().to_string();
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let core_name: Option<&str> = if let Some(c) = s.next() {
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if !c.starts_with("CM") {
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println!("Core not detected, adding as variant");
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chip_name.push('-');
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chip_name.push_str(c);
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None
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} else {
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println!("Detected core {}", c);
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Some(c)
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}
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} else {
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None
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};
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chip_cores.insert(
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chip_name.to_string(),
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core_name.map(|s| s.to_ascii_lowercase().to_string()),
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);
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let chip_path = data_dir.join("chips").join(&format!("{}.yaml", chip_name));
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println!("chip_path: {:?}", chip_path);
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let chip = fs::read(chip_path).unwrap();
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let chip: Chip = serde_yaml::from_slice(&chip).unwrap();
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println!("looking for core {:?}", core_name);
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let core: Option<(&Core, usize)> = if let Some(core_name) = core_name {
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let core_name = core_name.to_ascii_lowercase();
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let mut c = None;
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let mut idx = 0;
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for (i, core) in chip.cores.iter().enumerate() {
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if core.name == core_name {
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c = Some(core);
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idx = i;
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break;
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}
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}
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c.map(|c| (c, idx))
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} else {
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Some((&chip.cores[0], 0))
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};
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let (core, core_index) = core.unwrap();
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let core_name = &core.name;
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let mut ir = ir::IR::new();
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let mut dev = ir::Device {
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interrupts: Vec::new(),
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peripherals: Vec::new(),
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};
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// Load DBGMCU register for chip
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let mut dbgmcu: Option<ir::IR> = core.peripherals.iter().find_map(|(name, p)| {
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if name == "DBGMCU" {
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p.block.as_ref().map(|block| {
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let bi = BlockInfo::parse(block);
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let dbgmcu_reg_path = data_dir
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.join("registers")
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.join(&format!("{}_{}.yaml", bi.module, bi.version));
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serde_yaml::from_reader(File::open(dbgmcu_reg_path).unwrap()).unwrap()
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})
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} else {
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None
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}
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});
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// Load RCC register for chip
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let (_, rcc) = core
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.peripherals
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.iter()
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.find(|(name, _)| name == &"RCC")
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.expect("RCC peripheral missing");
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let rcc_block = rcc.block.as_ref().expect("RCC peripheral has no block");
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let bi = BlockInfo::parse(&rcc_block);
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let rcc_reg_path = data_dir
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.join("registers")
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.join(&format!("{}_{}.yaml", bi.module, bi.version));
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let rcc: IR = serde_yaml::from_reader(File::open(rcc_reg_path).unwrap()).unwrap();
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let mut peripheral_versions: BTreeMap<String, String> = BTreeMap::new();
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let mut pin_table: Vec<Vec<String>> = Vec::new();
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let mut interrupt_table: Vec<Vec<String>> = Vec::new();
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let mut peripherals_table: Vec<Vec<String>> = Vec::new();
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let mut peripheral_pins_table: Vec<Vec<String>> = Vec::new();
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let mut peripheral_rcc_table: Vec<Vec<String>> = Vec::new();
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let mut dma_channels_table: Vec<Vec<String>> = Vec::new();
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let mut peripheral_dma_channels_table: Vec<Vec<String>> = Vec::new();
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let mut peripheral_counts: BTreeMap<String, u8> = BTreeMap::new();
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let mut dma_channel_counts: BTreeMap<String, u8> = BTreeMap::new();
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let mut dbgmcu_table: Vec<Vec<String>> = Vec::new();
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let mut gpio_rcc_table: Vec<Vec<String>> = Vec::new();
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let mut gpio_regs: HashSet<String> = HashSet::new();
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let gpio_base = core.peripherals.get(&"GPIOA".to_string()).unwrap().address as u32;
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let gpio_stride = 0x400;
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let number_suffix_re = Regex::new("^(.*?)[0-9]*$").unwrap();
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if let Some(ref mut reg) = dbgmcu {
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if let Some(ref cr) = reg.fieldsets.get("CR") {
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for field in cr.fields.iter().filter(|e| e.name.contains("DBG")) {
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let mut fn_name = String::new();
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fn_name.push_str("set_");
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fn_name.push_str(&field.name.to_sanitized_snake_case());
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dbgmcu_table.push(vec!["cr".into(), fn_name]);
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}
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}
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}
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for (name, p) in &core.peripherals {
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let captures = number_suffix_re.captures(&name).unwrap();
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let root_peri_name = captures.get(1).unwrap().as_str().to_string();
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peripheral_counts.insert(
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root_peri_name.clone(),
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peripheral_counts.get(&root_peri_name).map_or(1, |v| v + 1),
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);
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let mut ir_peri = ir::Peripheral {
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name: name.clone(),
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array: None,
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base_address: p.address,
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block: None,
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description: None,
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interrupts: HashMap::new(),
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};
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if let Some(block) = &p.block {
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let bi = BlockInfo::parse(block);
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peripheral_counts.insert(
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bi.module.clone(),
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peripheral_counts.get(&bi.module).map_or(1, |v| v + 1),
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);
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for pin in &p.pins {
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let mut row = Vec::new();
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row.push(name.clone());
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row.push(bi.module.clone());
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row.push(bi.block.clone());
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row.push(pin.pin.clone());
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row.push(pin.signal.clone());
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if let Some(ref af) = pin.af {
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row.push(af.clone());
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}
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peripheral_pins_table.push(row);
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}
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for (signal, irq_name) in &p.interrupts {
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let mut row = Vec::new();
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row.push(name.clone());
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row.push(bi.module.clone());
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row.push(bi.block.clone());
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row.push(signal.clone());
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row.push(irq_name.to_ascii_uppercase());
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interrupt_table.push(row)
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}
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for (request, dma_channels) in &p.dma_channels {
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for channel in dma_channels.iter() {
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let mut row = Vec::new();
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row.push(name.clone());
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row.push(bi.module.clone());
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row.push(bi.block.clone());
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row.push(request.clone());
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row.push(if let Some(channel) = &channel.channel {
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format!("{{channel: {}}}", channel)
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} else if let Some(dmamux) = &channel.dmamux {
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format!("{{dmamux: {}}}", dmamux)
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} else {
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unreachable!();
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});
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row.push(if let Some(request) = channel.request {
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request.to_string()
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} else {
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"()".to_string()
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});
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if peripheral_dma_channels_table
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.iter()
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.find(|a| a[..a.len() - 1] == row[..row.len() - 1])
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.is_none()
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{
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peripheral_dma_channels_table.push(row);
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}
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}
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}
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let mut peripheral_row = Vec::new();
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peripheral_row.push(bi.module.clone());
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peripheral_row.push(name.clone());
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peripherals_table.push(peripheral_row);
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if let Some(old_version) =
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peripheral_versions.insert(bi.module.clone(), bi.version.clone())
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{
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if old_version != bi.version {
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panic!(
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"Peripheral {} has multiple versions: {} and {}",
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bi.module, old_version, bi.version
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);
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}
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}
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ir_peri.block = Some(format!("{}::{}", bi.module, bi.block));
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match bi.module.as_str() {
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"gpio" => {
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let port_letter = name.chars().skip(4).next().unwrap();
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assert_eq!(0, (p.address as u32 - gpio_base) % gpio_stride);
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let port_num = (p.address as u32 - gpio_base) / gpio_stride;
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for pin_num in 0..16 {
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let pin_name = format!("P{}{}", port_letter, pin_num);
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pin_table.push(vec![
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pin_name.clone(),
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name.clone(),
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port_num.to_string(),
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pin_num.to_string(),
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format!("EXTI{}", pin_num),
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]);
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}
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}
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_ => {}
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}
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// Workaround for clock registers being split on some chip families. Assume fields are
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// named after peripheral and look for first field matching and use that register.
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let mut en = find_reg(&rcc, "^.+ENR\\d*$", &format!("{}EN", name));
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let mut rst = find_reg(&rcc, "^.+RSTR\\d*$", &format!("{}RST", name));
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if en.is_none() && name.ends_with("1") {
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en = find_reg(
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&rcc,
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"^.+ENR\\d*$",
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&format!("{}EN", &name[..name.len() - 1]),
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);
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rst = find_reg(
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&rcc,
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"^.+RSTR\\d*$",
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&format!("{}RST", &name[..name.len() - 1]),
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);
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}
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match (en, rst) {
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(Some((enable_reg, enable_field)), reset_reg_field) => {
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let clock = match &p.clock {
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Some(clock) => clock.as_str(),
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None => {
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// No clock was specified, derive the clock name from the enable register name.
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// N.B. STM32G0 has only one APB bus but split ENR registers
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// (e.g. APBENR1).
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Regex::new("([A-Z]+\\d*)ENR\\d*")
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.unwrap()
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.captures(enable_reg)
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.unwrap()
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.get(1)
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.unwrap()
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.as_str()
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}
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};
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let clock = if name.starts_with("TIM") {
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format!("{}_tim", clock.to_ascii_lowercase())
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} else {
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clock.to_ascii_lowercase()
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};
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let mut row = Vec::with_capacity(6);
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row.push(name.clone());
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row.push(clock);
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row.push(enable_reg.to_ascii_lowercase());
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if let Some((reset_reg, reset_field)) = reset_reg_field {
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row.push(reset_reg.to_ascii_lowercase());
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row.push(format!("set_{}", enable_field.to_ascii_lowercase()));
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row.push(format!("set_{}", reset_field.to_ascii_lowercase()));
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} else {
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row.push(format!("set_{}", enable_field.to_ascii_lowercase()));
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}
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if !name.starts_with("GPIO") {
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peripheral_rcc_table.push(row);
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} else {
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gpio_rcc_table.push(row);
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gpio_regs.insert(enable_reg.to_ascii_lowercase());
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}
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}
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(None, Some(_)) => {
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println!("Unable to find enable register for {}", name)
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}
|
|
(None, None) => {
|
|
println!("Unable to find enable and reset register for {}", name)
|
|
}
|
|
}
|
|
}
|
|
|
|
dev.peripherals.push(ir_peri);
|
|
}
|
|
|
|
for reg in gpio_regs {
|
|
gpio_rcc_table.push(vec![reg]);
|
|
}
|
|
|
|
// We should always find GPIO RCC regs. If not, it means something
|
|
// is broken and GPIO won't work because it's not enabled.
|
|
assert!(!gpio_rcc_table.is_empty());
|
|
|
|
for (id, channel_info) in &core.dma_channels {
|
|
let mut row = Vec::new();
|
|
let dma_peri = core.peripherals.get(&channel_info.dma).unwrap();
|
|
let bi = BlockInfo::parse(dma_peri.block.as_ref().unwrap());
|
|
|
|
row.push(id.clone());
|
|
row.push(channel_info.dma.clone());
|
|
row.push(bi.module.clone());
|
|
row.push(channel_info.channel.to_string());
|
|
if let Some(dmamux) = &channel_info.dmamux {
|
|
let dmamux_channel = channel_info.dmamux_channel.unwrap();
|
|
row.push(format!(
|
|
"{{dmamux: {}, dmamux_channel: {}}}",
|
|
dmamux, dmamux_channel
|
|
));
|
|
} else {
|
|
row.push("{}".to_string());
|
|
}
|
|
|
|
dma_channels_table.push(row);
|
|
|
|
let dma_peri_name = channel_info.dma.clone();
|
|
dma_channel_counts.insert(
|
|
dma_peri_name.clone(),
|
|
dma_channel_counts.get(&dma_peri_name).map_or(1, |v| v + 1),
|
|
);
|
|
}
|
|
|
|
for (name, &num) in &core.interrupts {
|
|
dev.interrupts.push(ir::Interrupt {
|
|
name: name.clone(),
|
|
description: None,
|
|
value: num,
|
|
});
|
|
|
|
let name = name.to_ascii_uppercase();
|
|
|
|
interrupt_table.push(vec![name.clone()]);
|
|
|
|
if name.contains("EXTI") {
|
|
interrupt_table.push(vec!["EXTI".to_string(), name.clone()]);
|
|
}
|
|
}
|
|
|
|
ir.devices.insert("".to_string(), dev);
|
|
|
|
let mut extra = format!(
|
|
"pub fn GPIO(n: usize) -> gpio::Gpio {{
|
|
gpio::Gpio(({} + {}*n) as _)
|
|
}}",
|
|
gpio_base, gpio_stride,
|
|
);
|
|
|
|
let peripheral_version_table = peripheral_versions
|
|
.iter()
|
|
.map(|(kind, version)| vec![kind.clone(), version.clone()])
|
|
.collect();
|
|
|
|
make_table(&mut extra, "pins", &pin_table);
|
|
make_table(&mut extra, "interrupts", &interrupt_table);
|
|
make_table(&mut extra, "peripherals", &peripherals_table);
|
|
make_table(&mut extra, "peripheral_versions", &peripheral_version_table);
|
|
make_table(&mut extra, "peripheral_pins", &peripheral_pins_table);
|
|
make_table(
|
|
&mut extra,
|
|
"peripheral_dma_channels",
|
|
&peripheral_dma_channels_table,
|
|
);
|
|
make_table(&mut extra, "peripheral_rcc", &peripheral_rcc_table);
|
|
make_table(&mut extra, "gpio_rcc", &gpio_rcc_table);
|
|
make_table(&mut extra, "dma_channels", &dma_channels_table);
|
|
make_table(&mut extra, "dbgmcu", &dbgmcu_table);
|
|
make_peripheral_counts(&mut extra, &peripheral_counts);
|
|
make_dma_channel_counts(&mut extra, &dma_channel_counts);
|
|
|
|
for (module, version) in peripheral_versions {
|
|
all_peripheral_versions.insert((module.clone(), version.clone()));
|
|
write!(
|
|
&mut extra,
|
|
"#[path=\"../../peripherals/{}_{}.rs\"] pub mod {};\n",
|
|
module, version, module
|
|
)
|
|
.unwrap();
|
|
}
|
|
write!(
|
|
&mut extra,
|
|
"pub const CORE_INDEX: usize = {};\n",
|
|
core_index
|
|
)
|
|
.unwrap();
|
|
|
|
// Cleanups!
|
|
transform::sort::Sort {}.run(&mut ir).unwrap();
|
|
transform::Sanitize {}.run(&mut ir).unwrap();
|
|
|
|
let chip_dir = if chip.cores.len() > 1 {
|
|
out_dir.join("src/chips").join(format!(
|
|
"{}_{}",
|
|
chip_name.to_ascii_lowercase(),
|
|
core_name.to_ascii_lowercase()
|
|
))
|
|
} else {
|
|
out_dir
|
|
.join("src/chips")
|
|
.join(chip_name.to_ascii_lowercase())
|
|
};
|
|
fs::create_dir_all(&chip_dir).unwrap();
|
|
|
|
let items = generate::render(&ir, &generate_opts).unwrap();
|
|
let mut file = File::create(chip_dir.join("pac.rs")).unwrap();
|
|
let data = items.to_string().replace("] ", "]\n");
|
|
|
|
// Remove inner attributes like #![no_std]
|
|
let re = Regex::new("# *! *\\[.*\\]").unwrap();
|
|
let data = re.replace_all(&data, "");
|
|
file.write_all(data.as_bytes()).unwrap();
|
|
file.write_all(extra.as_bytes()).unwrap();
|
|
|
|
let mut device_x = String::new();
|
|
|
|
for (name, _) in &core.interrupts {
|
|
write!(
|
|
&mut device_x,
|
|
"PROVIDE({} = DefaultHandler);\n",
|
|
name.to_ascii_uppercase()
|
|
)
|
|
.unwrap();
|
|
}
|
|
|
|
File::create(chip_dir.join("device.x"))
|
|
.unwrap()
|
|
.write_all(device_x.as_bytes())
|
|
.unwrap();
|
|
|
|
// generate default memory.x
|
|
gen_memory_x(&chip_dir, &chip);
|
|
}
|
|
|
|
for (module, version) in all_peripheral_versions {
|
|
println!("loading {} {}", module, version);
|
|
|
|
let regs_path = Path::new(&data_dir)
|
|
.join("registers")
|
|
.join(&format!("{}_{}.yaml", module, version));
|
|
|
|
let mut ir: ir::IR = serde_yaml::from_reader(File::open(regs_path).unwrap()).unwrap();
|
|
|
|
transform::expand_extends::ExpandExtends {}
|
|
.run(&mut ir)
|
|
.unwrap();
|
|
|
|
transform::map_names(&mut ir, |k, s| match k {
|
|
transform::NameKind::Block => *s = format!("{}", s),
|
|
transform::NameKind::Fieldset => *s = format!("regs::{}", s),
|
|
transform::NameKind::Enum => *s = format!("vals::{}", s),
|
|
_ => {}
|
|
});
|
|
|
|
transform::sort::Sort {}.run(&mut ir).unwrap();
|
|
transform::Sanitize {}.run(&mut ir).unwrap();
|
|
|
|
let items = generate::render(&ir, &generate_opts).unwrap();
|
|
let mut file = File::create(
|
|
out_dir
|
|
.join("src/peripherals")
|
|
.join(format!("{}_{}.rs", module, version)),
|
|
)
|
|
.unwrap();
|
|
let data = items.to_string().replace("] ", "]\n");
|
|
|
|
// Remove inner attributes like #![no_std]
|
|
let re = Regex::new("# *! *\\[.*\\]").unwrap();
|
|
let data = re.replace_all(&data, "");
|
|
file.write_all(data.as_bytes()).unwrap();
|
|
}
|
|
|
|
// Generate src/lib_inner.rs
|
|
const PATHS_MARKER: &[u8] = b"// GEN PATHS HERE";
|
|
let librs = include_bytes!("assets/lib_inner.rs");
|
|
let i = bytes_find(librs, PATHS_MARKER).unwrap();
|
|
let mut paths = String::new();
|
|
|
|
for (chip, cores) in chip_cores.iter() {
|
|
let x = chip.to_ascii_lowercase();
|
|
if let Some(c) = cores {
|
|
write!(
|
|
&mut paths,
|
|
"#[cfg_attr(feature=\"{}_{}\", path = \"chips/{}_{}/pac.rs\")]",
|
|
x, c, x, c
|
|
)
|
|
.unwrap();
|
|
} else {
|
|
write!(
|
|
&mut paths,
|
|
"#[cfg_attr(feature=\"{}\", path = \"chips/{}/pac.rs\")]",
|
|
x, x
|
|
)
|
|
.unwrap();
|
|
}
|
|
}
|
|
let mut contents: Vec<u8> = Vec::new();
|
|
contents.extend(&librs[..i]);
|
|
contents.extend(paths.as_bytes());
|
|
contents.extend(&librs[i + PATHS_MARKER.len()..]);
|
|
fs::write(out_dir.join("src").join("lib_inner.rs"), &contents).unwrap();
|
|
|
|
// Generate src/lib.rs
|
|
const CUT_MARKER: &[u8] = b"// GEN CUT HERE";
|
|
let librs = include_bytes!("../../stm32-metapac/src/lib.rs");
|
|
let i = bytes_find(librs, CUT_MARKER).unwrap();
|
|
let mut contents: Vec<u8> = Vec::new();
|
|
contents.extend(&librs[..i]);
|
|
contents.extend(b"include!(\"lib_inner.rs\");\n");
|
|
fs::write(out_dir.join("src").join("lib.rs"), contents).unwrap();
|
|
|
|
// Generate src/common.rs
|
|
fs::write(
|
|
out_dir.join("src").join("common.rs"),
|
|
generate::COMMON_MODULE,
|
|
)
|
|
.unwrap();
|
|
|
|
// Generate Cargo.toml
|
|
const BUILDDEP_BEGIN: &[u8] = b"# BEGIN BUILD DEPENDENCIES";
|
|
const BUILDDEP_END: &[u8] = b"# END BUILD DEPENDENCIES";
|
|
|
|
let mut contents = include_bytes!("../../stm32-metapac/Cargo.toml").to_vec();
|
|
let begin = bytes_find(&contents, BUILDDEP_BEGIN).unwrap();
|
|
let end = bytes_find(&contents, BUILDDEP_END).unwrap() + BUILDDEP_END.len();
|
|
contents.drain(begin..end);
|
|
fs::write(out_dir.join("Cargo.toml"), contents).unwrap();
|
|
|
|
// Generate build.rs
|
|
fs::write(out_dir.join("build.rs"), include_bytes!("assets/build.rs")).unwrap();
|
|
}
|
|
|
|
fn bytes_find(haystack: &[u8], needle: &[u8]) -> Option<usize> {
|
|
haystack
|
|
.windows(needle.len())
|
|
.position(|window| window == needle)
|
|
}
|
|
|
|
fn gen_memory_x(out_dir: &PathBuf, chip: &Chip) {
|
|
let mut memory_x = String::new();
|
|
|
|
let flash_bytes = chip
|
|
.flash
|
|
.regions
|
|
.get("BANK_1")
|
|
.unwrap()
|
|
.bytes
|
|
.unwrap_or(chip.flash.bytes);
|
|
let flash_origin = chip.flash.regions.get("BANK_1").unwrap().base;
|
|
|
|
let ram_bytes = chip
|
|
.ram
|
|
.regions
|
|
.get("SRAM")
|
|
.unwrap()
|
|
.bytes
|
|
.unwrap_or(chip.ram.bytes);
|
|
let ram_origin = chip.ram.regions.get("SRAM").unwrap().base;
|
|
|
|
write!(memory_x, "MEMORY\n{{\n").unwrap();
|
|
write!(
|
|
memory_x,
|
|
" FLASH : ORIGIN = 0x{:x}, LENGTH = {}\n",
|
|
flash_origin, flash_bytes
|
|
)
|
|
.unwrap();
|
|
write!(
|
|
memory_x,
|
|
" RAM : ORIGIN = 0x{:x}, LENGTH = {}\n",
|
|
ram_origin, ram_bytes
|
|
)
|
|
.unwrap();
|
|
write!(memory_x, "}}").unwrap();
|
|
|
|
fs::create_dir_all(out_dir.join("memory_x")).unwrap();
|
|
let mut file = File::create(out_dir.join("memory_x").join("memory.x")).unwrap();
|
|
file.write_all(memory_x.as_bytes()).unwrap();
|
|
}
|