2080d8bb6d
Co-Authored-By: anton smeenk <asmeenk@planet.nl>
345 lines
9.3 KiB
Rust
345 lines
9.3 KiB
Rust
#![macro_use]
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use core::future::Future;
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use core::pin::Pin;
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use core::sync::atomic::{fence, Ordering};
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use core::task::{Context, Poll};
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use embassy_cortex_m::interrupt::Priority;
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use embassy_hal_common::{into_ref, Peripheral, PeripheralRef};
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use embassy_sync::waitqueue::AtomicWaker;
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use super::word::{Word, WordSize};
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use super::Dir;
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use crate::_generated::BDMA_CHANNEL_COUNT;
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use crate::interrupt::{Interrupt, InterruptExt};
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use crate::pac;
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use crate::pac::bdma::vals;
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#[derive(Debug, Copy, Clone, PartialEq, Eq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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#[non_exhaustive]
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pub struct TransferOptions {}
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impl Default for TransferOptions {
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fn default() -> Self {
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Self {}
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}
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}
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impl From<WordSize> for vals::Size {
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fn from(raw: WordSize) -> Self {
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match raw {
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WordSize::OneByte => Self::BITS8,
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WordSize::TwoBytes => Self::BITS16,
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WordSize::FourBytes => Self::BITS32,
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}
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}
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}
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impl From<Dir> for vals::Dir {
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fn from(raw: Dir) -> Self {
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match raw {
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Dir::MemoryToPeripheral => Self::FROMMEMORY,
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Dir::PeripheralToMemory => Self::FROMPERIPHERAL,
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}
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}
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}
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struct State {
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ch_wakers: [AtomicWaker; BDMA_CHANNEL_COUNT],
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}
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impl State {
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const fn new() -> Self {
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const AW: AtomicWaker = AtomicWaker::new();
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Self {
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ch_wakers: [AW; BDMA_CHANNEL_COUNT],
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}
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}
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}
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static STATE: State = State::new();
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/// safety: must be called only once
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pub(crate) unsafe fn init(irq_priority: Priority) {
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foreach_interrupt! {
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($peri:ident, bdma, $block:ident, $signal_name:ident, $irq:ident) => {
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let irq = crate::interrupt::$irq::steal();
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irq.set_priority(irq_priority);
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irq.enable();
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};
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}
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crate::_generated::init_bdma();
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}
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foreach_dma_channel! {
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($channel_peri:ident, BDMA1, bdma, $channel_num:expr, $index:expr, $dmamux:tt) => {
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// BDMA1 in H7 doesn't use DMAMUX, which breaks
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};
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($channel_peri:ident, $dma_peri:ident, bdma, $channel_num:expr, $index:expr, $dmamux:tt) => {
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impl sealed::Channel for crate::peripherals::$channel_peri {
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fn regs(&self) -> pac::bdma::Dma {
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pac::$dma_peri
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}
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fn num(&self) -> usize {
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$channel_num
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}
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fn index(&self) -> usize {
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$index
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}
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fn on_irq() {
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unsafe { on_irq_inner(pac::$dma_peri, $channel_num, $index) }
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}
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}
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impl Channel for crate::peripherals::$channel_peri {}
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};
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}
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/// Safety: Must be called with a matching set of parameters for a valid dma channel
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pub(crate) unsafe fn on_irq_inner(dma: pac::bdma::Dma, channel_num: usize, index: usize) {
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let isr = dma.isr().read();
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let cr = dma.ch(channel_num).cr();
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if isr.teif(channel_num) {
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panic!("DMA: error on BDMA@{:08x} channel {}", dma.0 as u32, channel_num);
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}
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if isr.tcif(channel_num) && cr.read().tcie() {
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cr.write(|_| ()); // Disable channel interrupts with the default value.
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STATE.ch_wakers[index].wake();
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}
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}
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#[cfg(any(bdma_v2, dmamux))]
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pub type Request = u8;
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#[cfg(not(any(bdma_v2, dmamux)))]
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pub type Request = ();
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#[cfg(dmamux)]
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pub trait Channel: sealed::Channel + Peripheral<P = Self> + 'static + super::dmamux::MuxChannel {}
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#[cfg(not(dmamux))]
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pub trait Channel: sealed::Channel + Peripheral<P = Self> + 'static {}
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pub(crate) mod sealed {
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use super::*;
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pub trait Channel {
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fn regs(&self) -> pac::bdma::Dma;
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fn num(&self) -> usize;
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fn index(&self) -> usize;
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fn on_irq();
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}
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}
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#[must_use = "futures do nothing unless you `.await` or poll them"]
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pub struct Transfer<'a, C: Channel> {
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channel: PeripheralRef<'a, C>,
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}
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impl<'a, C: Channel> Transfer<'a, C> {
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pub unsafe fn new_read<W: Word>(
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channel: impl Peripheral<P = C> + 'a,
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request: Request,
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peri_addr: *mut W,
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buf: &'a mut [W],
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options: TransferOptions,
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) -> Self {
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Self::new_read_raw(channel, request, peri_addr, buf, options)
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}
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pub unsafe fn new_read_raw<W: Word>(
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channel: impl Peripheral<P = C> + 'a,
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request: Request,
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peri_addr: *mut W,
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buf: *mut [W],
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options: TransferOptions,
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) -> Self {
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into_ref!(channel);
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let (ptr, len) = super::slice_ptr_parts_mut(buf);
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assert!(len > 0 && len <= 0xFFFF);
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Self::new_inner(
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channel,
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request,
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Dir::PeripheralToMemory,
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peri_addr as *const u32,
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ptr as *mut u32,
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len,
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true,
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W::size(),
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options,
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)
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}
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pub unsafe fn new_write<W: Word>(
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channel: impl Peripheral<P = C> + 'a,
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request: Request,
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buf: &'a [W],
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peri_addr: *mut W,
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options: TransferOptions,
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) -> Self {
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Self::new_write_raw(channel, request, buf, peri_addr, options)
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}
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pub unsafe fn new_write_raw<W: Word>(
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channel: impl Peripheral<P = C> + 'a,
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request: Request,
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buf: *const [W],
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peri_addr: *mut W,
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options: TransferOptions,
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) -> Self {
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into_ref!(channel);
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let (ptr, len) = super::slice_ptr_parts(buf);
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assert!(len > 0 && len <= 0xFFFF);
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Self::new_inner(
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channel,
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request,
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Dir::MemoryToPeripheral,
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peri_addr as *const u32,
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ptr as *mut u32,
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len,
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true,
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W::size(),
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options,
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)
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}
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pub unsafe fn new_write_repeated<W: Word>(
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channel: impl Peripheral<P = C> + 'a,
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request: Request,
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repeated: &'a W,
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count: usize,
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peri_addr: *mut W,
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options: TransferOptions,
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) -> Self {
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into_ref!(channel);
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Self::new_inner(
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channel,
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request,
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Dir::MemoryToPeripheral,
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peri_addr as *const u32,
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repeated as *const W as *mut u32,
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count,
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false,
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W::size(),
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options,
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)
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}
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unsafe fn new_inner(
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channel: PeripheralRef<'a, C>,
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_request: Request,
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dir: Dir,
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peri_addr: *const u32,
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mem_addr: *mut u32,
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mem_len: usize,
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incr_mem: bool,
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data_size: WordSize,
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_options: TransferOptions,
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) -> Self {
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let ch = channel.regs().ch(channel.num());
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// "Preceding reads and writes cannot be moved past subsequent writes."
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fence(Ordering::SeqCst);
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#[cfg(bdma_v2)]
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critical_section::with(|_| channel.regs().cselr().modify(|w| w.set_cs(channel.num(), _request)));
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let mut this = Self { channel };
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this.clear_irqs();
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#[cfg(dmamux)]
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super::dmamux::configure_dmamux(&mut *this.channel, _request);
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ch.par().write_value(peri_addr as u32);
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ch.mar().write_value(mem_addr as u32);
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ch.ndtr().write(|w| w.set_ndt(mem_len as u16));
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ch.cr().write(|w| {
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w.set_psize(data_size.into());
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w.set_msize(data_size.into());
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if incr_mem {
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w.set_minc(vals::Inc::ENABLED);
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} else {
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w.set_minc(vals::Inc::DISABLED);
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}
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w.set_dir(dir.into());
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w.set_teie(true);
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w.set_tcie(true);
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w.set_en(true);
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});
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this
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}
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fn clear_irqs(&mut self) {
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unsafe {
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self.channel.regs().ifcr().write(|w| {
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w.set_tcif(self.channel.num(), true);
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w.set_teif(self.channel.num(), true);
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})
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}
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}
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pub fn request_stop(&mut self) {
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let ch = self.channel.regs().ch(self.channel.num());
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// Disable the channel. Keep the IEs enabled so the irqs still fire.
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unsafe {
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ch.cr().write(|w| {
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w.set_teie(true);
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w.set_tcie(true);
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})
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}
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}
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pub fn is_running(&mut self) -> bool {
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let ch = self.channel.regs().ch(self.channel.num());
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unsafe { ch.cr().read() }.en()
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}
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/// Gets the total remaining transfers for the channel
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/// Note: this will be zero for transfers that completed without cancellation.
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pub fn get_remaining_transfers(&self) -> u16 {
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let ch = self.channel.regs().ch(self.channel.num());
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unsafe { ch.ndtr().read() }.ndt()
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}
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pub fn blocking_wait(mut self) {
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while self.is_running() {}
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// "Subsequent reads and writes cannot be moved ahead of preceding reads."
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fence(Ordering::SeqCst);
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core::mem::forget(self);
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}
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}
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impl<'a, C: Channel> Drop for Transfer<'a, C> {
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fn drop(&mut self) {
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self.request_stop();
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while self.is_running() {}
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// "Subsequent reads and writes cannot be moved ahead of preceding reads."
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fence(Ordering::SeqCst);
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}
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}
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impl<'a, C: Channel> Unpin for Transfer<'a, C> {}
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impl<'a, C: Channel> Future for Transfer<'a, C> {
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type Output = ();
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fn poll(mut self: Pin<&mut Self>, cx: &mut Context<'_>) -> Poll<Self::Output> {
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STATE.ch_wakers[self.channel.index()].register(cx.waker());
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if self.is_running() {
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Poll::Pending
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} else {
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Poll::Ready(())
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}
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}
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}
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