218 lines
8.1 KiB
Rust
218 lines
8.1 KiB
Rust
use stm32_metapac::rtc::vals::{Calp, Calw16, Calw8, Fmt, Init, Key, Osel, Pol, TampalrmPu, TampalrmType};
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use super::{Instance, RtcCalibrationCyclePeriod, RtcConfig};
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use crate::pac::rtc::Rtc;
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impl<'d, T: Instance> super::Rtc<'d, T> {
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/// Applies the RTC config
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/// It this changes the RTC clock source the time will be reset
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pub(super) fn apply_config(&mut self, rtc_config: RtcConfig) {
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// Unlock the backup domain
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unsafe {
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#[cfg(feature = "stm32g0c1ve")]
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{
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crate::pac::PWR.cr1().modify(|w| w.set_dbp(true));
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while !crate::pac::PWR.cr1().read().dbp() {}
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}
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#[cfg(not(feature = "stm32g0c1ve"))]
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{
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crate::pac::PWR
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.cr1()
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.modify(|w| w.set_dbp(stm32_metapac::pwr::vals::Dbp::ENABLED));
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while crate::pac::PWR.cr1().read().dbp() != stm32_metapac::pwr::vals::Dbp::DISABLED {}
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}
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let reg = crate::pac::RCC.bdcr().read();
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assert!(!reg.lsecsson(), "RTC is not compatible with LSE CSS, yet.");
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let config_rtcsel = rtc_config.clock_config as u8;
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#[cfg(not(any(
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feature = "stm32wl54jc-cm0p",
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feature = "stm32wle5ub",
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feature = "stm32g0c1ve",
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feature = "stm32wl55jc-cm4",
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feature = "stm32wl55uc-cm4"
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)))]
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let config_rtcsel = stm32_metapac::rtc::vals::Rtcsel(config_rtcsel);
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#[cfg(feature = "stm32g0c1ve")]
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let config_rtcsel = stm32_metapac::rcc::vals::Rtcsel(config_rtcsel);
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if !reg.rtcen() || reg.rtcsel() != config_rtcsel {
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crate::pac::RCC.bdcr().modify(|w| w.set_bdrst(true));
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crate::pac::RCC.bdcr().modify(|w| {
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// Reset
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w.set_bdrst(false);
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// Select RTC source
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w.set_rtcsel(config_rtcsel);
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w.set_rtcen(true);
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// Restore bcdr
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w.set_lscosel(reg.lscosel());
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w.set_lscoen(reg.lscoen());
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w.set_lseon(reg.lseon());
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w.set_lsedrv(reg.lsedrv());
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w.set_lsebyp(reg.lsebyp());
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});
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}
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}
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self.write(true, |rtc| {
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unsafe {
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rtc.cr().modify(|w| {
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w.set_fmt(Fmt::TWENTYFOURHOUR);
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w.set_osel(Osel::DISABLED);
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w.set_pol(Pol::HIGH);
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});
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rtc.prer().modify(|w| {
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w.set_prediv_s(rtc_config.sync_prescaler);
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w.set_prediv_a(rtc_config.async_prescaler);
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});
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// TODO: configuration for output pins
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rtc.cr().modify(|w| {
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w.set_out2en(false);
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w.set_tampalrm_type(TampalrmType::PUSHPULL);
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w.set_tampalrm_pu(TampalrmPu::NOPULLUP);
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});
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}
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});
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self.rtc_config = rtc_config;
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}
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const RTC_CALR_MIN_PPM: f32 = -487.1;
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const RTC_CALR_MAX_PPM: f32 = 488.5;
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const RTC_CALR_RESOLUTION_PPM: f32 = 0.9537;
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/// Calibrate the clock drift.
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///
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/// `clock_drift` can be adjusted from -487.1 ppm to 488.5 ppm and is clamped to this range.
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///
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/// ### Note
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///
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/// To perform a calibration when `async_prescaler` is less then 3, `sync_prescaler`
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/// has to be reduced accordingly (see RM0351 Rev 9, sec 38.3.12).
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pub fn calibrate(&mut self, mut clock_drift: f32, period: RtcCalibrationCyclePeriod) {
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if clock_drift < Self::RTC_CALR_MIN_PPM {
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clock_drift = Self::RTC_CALR_MIN_PPM;
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} else if clock_drift > Self::RTC_CALR_MAX_PPM {
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clock_drift = Self::RTC_CALR_MAX_PPM;
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}
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clock_drift = clock_drift / Self::RTC_CALR_RESOLUTION_PPM;
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self.write(false, |rtc| {
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unsafe {
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rtc.calr().write(|w| {
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match period {
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RtcCalibrationCyclePeriod::Seconds8 => {
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w.set_calw8(Calw8::EIGHTSECONDS);
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}
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RtcCalibrationCyclePeriod::Seconds16 => {
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w.set_calw16(Calw16::SIXTEENSECONDS);
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}
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RtcCalibrationCyclePeriod::Seconds32 => {
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// Set neither `calw8` nor `calw16` to use 32 seconds
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}
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}
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// Extra pulses during calibration cycle period: CALP * 512 - CALM
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//
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// CALP sets whether pulses are added or omitted.
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//
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// CALM contains how many pulses (out of 512) are masked in a
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// given calibration cycle period.
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if clock_drift > 0.0 {
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// Maximum (about 512.2) rounds to 512.
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clock_drift += 0.5;
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// When the offset is positive (0 to 512), the opposite of
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// the offset (512 - offset) is masked, i.e. for the
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// maximum offset (512), 0 pulses are masked.
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w.set_calp(Calp::INCREASEFREQ);
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w.set_calm(512 - clock_drift as u16);
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} else {
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// Minimum (about -510.7) rounds to -511.
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clock_drift -= 0.5;
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// When the offset is negative or zero (-511 to 0),
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// the absolute offset is masked, i.e. for the minimum
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// offset (-511), 511 pulses are masked.
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w.set_calp(Calp::NOCHANGE);
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w.set_calm((clock_drift * -1.0) as u16);
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}
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});
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}
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})
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}
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pub(super) fn write<F, R>(&mut self, init_mode: bool, f: F) -> R
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where
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F: FnOnce(&crate::pac::rtc::Rtc) -> R,
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{
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let r = T::regs();
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// Disable write protection.
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// This is safe, as we're only writin the correct and expected values.
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unsafe {
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r.wpr().write(|w| w.set_key(Key::DEACTIVATE1));
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r.wpr().write(|w| w.set_key(Key::DEACTIVATE2));
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if init_mode && !r.icsr().read().initf() {
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r.icsr().modify(|w| w.set_init(Init::INITMODE));
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// wait till init state entered
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// ~2 RTCCLK cycles
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while !r.icsr().read().initf() {}
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}
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}
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let result = f(&r);
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unsafe {
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if init_mode {
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r.icsr().modify(|w| w.set_init(Init::FREERUNNINGMODE)); // Exits init mode
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}
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// Re-enable write protection.
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// This is safe, as the field accepts the full range of 8-bit values.
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r.wpr().write(|w| w.set_key(Key::ACTIVATE));
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}
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result
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}
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}
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pub(super) unsafe fn enable_peripheral_clk() {
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// Nothing to do
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}
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pub const BACKUP_REGISTER_COUNT: usize = 32;
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/// Read content of the backup register.
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///
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/// The registers retain their values during wakes from standby mode or system resets. They also
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/// retain their value when Vdd is switched off as long as V_BAT is powered.
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pub fn read_backup_register(_rtc: &Rtc, register: usize) -> Option<u32> {
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if register < BACKUP_REGISTER_COUNT {
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//Some(rtc.bkpr()[register].read().bits())
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None // RTC3 backup registers come from the TAMP peripe=heral, not RTC. Not() even in the L412 PAC
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} else {
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None
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}
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}
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/// Set content of the backup register.
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///
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/// The registers retain their values during wakes from standby mode or system resets. They also
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/// retain their value when Vdd is switched off as long as V_BAT is powered.
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pub fn write_backup_register(_rtc: &Rtc, register: usize, _value: u32) {
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if register < BACKUP_REGISTER_COUNT {
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// RTC3 backup registers come from the TAMP peripe=heral, not RTC. Not() even in the L412 PAC
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//unsafe { self.rtc.bkpr()[register].write(|w| w.bits(value)) }
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}
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}
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