381 lines
8.9 KiB
Rust
381 lines
8.9 KiB
Rust
#[allow(unused_imports)]
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#[rustfmt::skip]
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pub mod pac {
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// The nRF9160 has a secure and non-secure (NS) mode.
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// To avoid cfg spam, we remove _ns or _s suffixes here.
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pub use nrf9160_pac::{
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interrupt,
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Interrupt,
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cc_host_rgf_s as cc_host_rgf,
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clock_ns as clock,
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cryptocell_s as cryptocell,
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ctrl_ap_peri_s as ctrl_ap_peri,
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dppic_ns as dppic,
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egu0_ns as egu0,
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ficr_s as ficr,
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fpu_ns as fpu,
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gpiote0_s as gpiote,
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i2s_ns as i2s,
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ipc_ns as ipc,
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kmu_ns as kmu,
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nvmc_ns as nvmc,
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p0_ns as p0,
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pdm_ns as pdm,
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power_ns as power,
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pwm0_ns as pwm0,
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regulators_ns as regulators,
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rtc0_ns as rtc0,
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saadc_ns as saadc,
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spim0_ns as spim0,
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spis0_ns as spis0,
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spu_s as spu,
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tad_s as tad,
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timer0_ns as timer0,
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twim0_ns as twim0,
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twis0_ns as twis0,
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uarte0_ns as uarte0,
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uicr_s as uicr,
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vmc_ns as vmc,
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wdt_ns as wdt,
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};
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#[cfg(feature = "nrf9160-ns")]
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pub use nrf9160_pac::{
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CLOCK_NS as CLOCK,
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DPPIC_NS as DPPIC,
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EGU0_NS as EGU0,
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EGU1_NS as EGU1,
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EGU2_NS as EGU2,
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EGU3_NS as EGU3,
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EGU4_NS as EGU4,
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EGU5_NS as EGU5,
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FPU_NS as FPU,
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GPIOTE1_NS as GPIOTE1,
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I2S_NS as I2S,
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IPC_NS as IPC,
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KMU_NS as KMU,
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NVMC_NS as NVMC,
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P0_NS as P0,
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PDM_NS as PDM,
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POWER_NS as POWER,
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PWM0_NS as PWM0,
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PWM1_NS as PWM1,
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PWM2_NS as PWM2,
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PWM3_NS as PWM3,
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REGULATORS_NS as REGULATORS,
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RTC0_NS as RTC0,
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RTC1_NS as RTC1,
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SAADC_NS as SAADC,
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SPIM0_NS as SPIM0,
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SPIM1_NS as SPIM1,
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SPIM2_NS as SPIM2,
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SPIM3_NS as SPIM3,
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SPIS0_NS as SPIS0,
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SPIS1_NS as SPIS1,
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SPIS2_NS as SPIS2,
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SPIS3_NS as SPIS3,
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TIMER0_NS as TIMER0,
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TIMER1_NS as TIMER1,
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TIMER2_NS as TIMER2,
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TWIM0_NS as TWIM0,
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TWIM1_NS as TWIM1,
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TWIM2_NS as TWIM2,
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TWIM3_NS as TWIM3,
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TWIS0_NS as TWIS0,
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TWIS1_NS as TWIS1,
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TWIS2_NS as TWIS2,
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TWIS3_NS as TWIS3,
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UARTE0_NS as UARTE0,
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UARTE1_NS as UARTE1,
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UARTE2_NS as UARTE2,
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UARTE3_NS as UARTE3,
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VMC_NS as VMC,
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WDT_NS as WDT,
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};
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#[cfg(feature = "nrf9160-s")]
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pub use nrf9160_pac::{
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CC_HOST_RGF_S as CC_HOST_RGF,
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CLOCK_S as CLOCK,
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CRYPTOCELL_S as CRYPTOCELL,
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CTRL_AP_PERI_S as CTRL_AP_PERI,
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DPPIC_S as DPPIC,
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EGU0_S as EGU0,
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EGU1_S as EGU1,
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EGU2_S as EGU2,
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EGU3_S as EGU3,
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EGU4_S as EGU4,
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EGU5_S as EGU5,
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FICR_S as FICR,
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FPU_S as FPU,
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GPIOTE0_S as GPIOTE0,
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I2S_S as I2S,
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IPC_S as IPC,
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KMU_S as KMU,
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NVMC_S as NVMC,
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P0_S as P0,
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PDM_S as PDM,
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POWER_S as POWER,
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PWM0_S as PWM0,
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PWM1_S as PWM1,
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PWM2_S as PWM2,
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PWM3_S as PWM3,
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REGULATORS_S as REGULATORS,
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RTC0_S as RTC0,
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RTC1_S as RTC1,
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SAADC_S as SAADC,
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SPIM0_S as SPIM0,
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SPIM1_S as SPIM1,
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SPIM2_S as SPIM2,
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SPIM3_S as SPIM3,
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SPIS0_S as SPIS0,
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SPIS1_S as SPIS1,
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SPIS2_S as SPIS2,
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SPIS3_S as SPIS3,
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SPU_S as SPU,
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TAD_S as TAD,
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TIMER0_S as TIMER0,
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TIMER1_S as TIMER1,
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TIMER2_S as TIMER2,
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TWIM0_S as TWIM0,
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TWIM1_S as TWIM1,
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TWIM2_S as TWIM2,
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TWIM3_S as TWIM3,
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TWIS0_S as TWIS0,
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TWIS1_S as TWIS1,
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TWIS2_S as TWIS2,
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TWIS3_S as TWIS3,
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UARTE0_S as UARTE0,
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UARTE1_S as UARTE1,
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UARTE2_S as UARTE2,
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UARTE3_S as UARTE3,
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UICR_S as UICR,
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VMC_S as VMC,
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WDT_S as WDT,
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};
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}
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/// The maximum buffer size that the EasyDMA can send/recv in one operation.
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pub const EASY_DMA_SIZE: usize = (1 << 13) - 1;
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pub const FORCE_COPY_BUFFER_SIZE: usize = 1024;
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embassy_hal_common::peripherals! {
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// RTC
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RTC0,
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RTC1,
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// WDT
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WDT,
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// UARTE, TWI & SPI
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UARTETWISPI0,
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UARTETWISPI1,
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UARTETWISPI2,
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UARTETWISPI3,
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// SAADC
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SAADC,
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// PWM
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PWM0,
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PWM1,
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PWM2,
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PWM3,
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// TIMER
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TIMER0,
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TIMER1,
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TIMER2,
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// GPIOTE
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GPIOTE_CH0,
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GPIOTE_CH1,
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GPIOTE_CH2,
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GPIOTE_CH3,
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GPIOTE_CH4,
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GPIOTE_CH5,
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GPIOTE_CH6,
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GPIOTE_CH7,
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// PPI
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PPI_CH0,
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PPI_CH1,
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PPI_CH2,
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PPI_CH3,
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PPI_CH4,
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PPI_CH5,
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PPI_CH6,
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PPI_CH7,
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PPI_CH8,
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PPI_CH9,
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PPI_CH10,
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PPI_CH11,
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PPI_CH12,
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PPI_CH13,
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PPI_CH14,
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PPI_CH15,
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PPI_GROUP0,
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PPI_GROUP1,
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PPI_GROUP2,
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PPI_GROUP3,
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PPI_GROUP4,
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PPI_GROUP5,
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// GPIO port 0
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P0_00,
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P0_01,
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P0_02,
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P0_03,
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P0_04,
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P0_05,
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P0_06,
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P0_07,
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P0_08,
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P0_09,
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P0_10,
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P0_11,
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P0_12,
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P0_13,
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P0_14,
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P0_15,
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P0_16,
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P0_17,
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P0_18,
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P0_19,
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P0_20,
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P0_21,
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P0_22,
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P0_23,
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P0_24,
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P0_25,
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P0_26,
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P0_27,
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P0_28,
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P0_29,
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P0_30,
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P0_31,
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}
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impl_uarte!(UARTETWISPI0, UARTE0, UARTE0_SPIM0_SPIS0_TWIM0_TWIS0);
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impl_uarte!(UARTETWISPI1, UARTE1, UARTE1_SPIM1_SPIS1_TWIM1_TWIS1);
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impl_uarte!(UARTETWISPI2, UARTE2, UARTE2_SPIM2_SPIS2_TWIM2_TWIS2);
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impl_uarte!(UARTETWISPI3, UARTE3, UARTE3_SPIM3_SPIS3_TWIM3_TWIS3);
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impl_spim!(UARTETWISPI0, SPIM0, UARTE0_SPIM0_SPIS0_TWIM0_TWIS0);
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impl_spim!(UARTETWISPI1, SPIM1, UARTE1_SPIM1_SPIS1_TWIM1_TWIS1);
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impl_spim!(UARTETWISPI2, SPIM2, UARTE2_SPIM2_SPIS2_TWIM2_TWIS2);
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impl_spim!(UARTETWISPI3, SPIM3, UARTE3_SPIM3_SPIS3_TWIM3_TWIS3);
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impl_twim!(UARTETWISPI0, TWIM0, UARTE0_SPIM0_SPIS0_TWIM0_TWIS0);
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impl_twim!(UARTETWISPI1, TWIM1, UARTE1_SPIM1_SPIS1_TWIM1_TWIS1);
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impl_twim!(UARTETWISPI2, TWIM2, UARTE2_SPIM2_SPIS2_TWIM2_TWIS2);
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impl_twim!(UARTETWISPI3, TWIM3, UARTE3_SPIM3_SPIS3_TWIM3_TWIS3);
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impl_pwm!(PWM0, PWM0, PWM0);
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impl_pwm!(PWM1, PWM1, PWM1);
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impl_pwm!(PWM2, PWM2, PWM2);
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impl_pwm!(PWM3, PWM3, PWM3);
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impl_timer!(TIMER0, TIMER0, TIMER0);
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impl_timer!(TIMER1, TIMER1, TIMER1);
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impl_timer!(TIMER2, TIMER2, TIMER2);
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impl_pin!(P0_00, 0, 0);
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impl_pin!(P0_01, 0, 1);
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impl_pin!(P0_02, 0, 2);
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impl_pin!(P0_03, 0, 3);
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impl_pin!(P0_04, 0, 4);
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impl_pin!(P0_05, 0, 5);
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impl_pin!(P0_06, 0, 6);
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impl_pin!(P0_07, 0, 7);
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impl_pin!(P0_08, 0, 8);
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impl_pin!(P0_09, 0, 9);
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impl_pin!(P0_10, 0, 10);
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impl_pin!(P0_11, 0, 11);
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impl_pin!(P0_12, 0, 12);
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impl_pin!(P0_13, 0, 13);
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impl_pin!(P0_14, 0, 14);
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impl_pin!(P0_15, 0, 15);
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impl_pin!(P0_16, 0, 16);
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impl_pin!(P0_17, 0, 17);
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impl_pin!(P0_18, 0, 18);
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impl_pin!(P0_19, 0, 19);
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impl_pin!(P0_20, 0, 20);
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impl_pin!(P0_21, 0, 21);
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impl_pin!(P0_22, 0, 22);
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impl_pin!(P0_23, 0, 23);
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impl_pin!(P0_24, 0, 24);
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impl_pin!(P0_25, 0, 25);
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impl_pin!(P0_26, 0, 26);
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impl_pin!(P0_27, 0, 27);
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impl_pin!(P0_28, 0, 28);
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impl_pin!(P0_29, 0, 29);
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impl_pin!(P0_30, 0, 30);
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impl_pin!(P0_31, 0, 31);
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impl_ppi_channel!(PPI_CH0, 0 => configurable);
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impl_ppi_channel!(PPI_CH1, 1 => configurable);
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impl_ppi_channel!(PPI_CH2, 2 => configurable);
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impl_ppi_channel!(PPI_CH3, 3 => configurable);
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impl_ppi_channel!(PPI_CH4, 4 => configurable);
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impl_ppi_channel!(PPI_CH5, 5 => configurable);
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impl_ppi_channel!(PPI_CH6, 6 => configurable);
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impl_ppi_channel!(PPI_CH7, 7 => configurable);
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impl_ppi_channel!(PPI_CH8, 8 => configurable);
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impl_ppi_channel!(PPI_CH9, 9 => configurable);
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impl_ppi_channel!(PPI_CH10, 10 => configurable);
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impl_ppi_channel!(PPI_CH11, 11 => configurable);
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impl_ppi_channel!(PPI_CH12, 12 => configurable);
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impl_ppi_channel!(PPI_CH13, 13 => configurable);
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impl_ppi_channel!(PPI_CH14, 14 => configurable);
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impl_ppi_channel!(PPI_CH15, 15 => configurable);
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impl_saadc_input!(P0_13, ANALOGINPUT0);
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impl_saadc_input!(P0_14, ANALOGINPUT1);
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impl_saadc_input!(P0_15, ANALOGINPUT2);
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impl_saadc_input!(P0_16, ANALOGINPUT3);
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impl_saadc_input!(P0_17, ANALOGINPUT4);
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impl_saadc_input!(P0_18, ANALOGINPUT5);
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impl_saadc_input!(P0_19, ANALOGINPUT6);
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impl_saadc_input!(P0_20, ANALOGINPUT7);
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pub mod irqs {
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use crate::pac::Interrupt as InterruptEnum;
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use embassy_macros::interrupt_declare as declare;
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declare!(SPU);
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declare!(CLOCK_POWER);
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declare!(UARTE0_SPIM0_SPIS0_TWIM0_TWIS0);
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declare!(UARTE1_SPIM1_SPIS1_TWIM1_TWIS1);
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declare!(UARTE2_SPIM2_SPIS2_TWIM2_TWIS2);
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declare!(UARTE3_SPIM3_SPIS3_TWIM3_TWIS3);
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declare!(GPIOTE0);
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declare!(SAADC);
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declare!(TIMER0);
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declare!(TIMER1);
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declare!(TIMER2);
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declare!(RTC0);
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declare!(RTC1);
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declare!(WDT);
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declare!(EGU0);
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declare!(EGU1);
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declare!(EGU2);
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declare!(EGU3);
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declare!(EGU4);
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declare!(EGU5);
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declare!(PWM0);
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declare!(PWM1);
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declare!(PWM2);
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declare!(PDM);
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declare!(PWM3);
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declare!(I2S);
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declare!(IPC);
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declare!(FPU);
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declare!(GPIOTE1);
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declare!(KMU);
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declare!(CRYPTOCELL);
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}
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