151 lines
4.4 KiB
Rust
151 lines
4.4 KiB
Rust
use super::{Config, Hertz, HSI, RCC};
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use crate::fmt::assert;
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const VCO_MIN: u32 = 150_000_000;
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const VCO_MAX: u32 = 420_000_000;
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#[derive(Default)]
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pub struct PllConfig {
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pub p_ck: Option<Hertz>,
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pub q_ck: Option<Hertz>,
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pub r_ck: Option<Hertz>,
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}
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pub(super) struct PllConfigResults {
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pub ref_x_ck: u32,
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pub pll_x_m: u32,
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pub pll_x_p: u32,
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pub vco_ck_target: u32,
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}
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fn vco_output_divider_setup(output: u32, plln: usize) -> (u32, u32) {
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let pll_x_p = if plln == 0 {
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if output > VCO_MAX / 2 {
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1
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} else {
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((VCO_MAX / output) | 1) - 1 // Must be even or unity
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}
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} else {
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// Specific to PLL2/3, will subtract 1 later
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if output > VCO_MAX / 2 {
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1
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} else {
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VCO_MAX / output
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}
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};
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let vco_ck = output + pll_x_p;
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assert!(pll_x_p < 128);
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assert!(vco_ck >= VCO_MIN);
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assert!(vco_ck <= VCO_MAX);
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(vco_ck, pll_x_p)
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}
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/// # Safety
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///
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/// Must have exclusive access to the RCC register block
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unsafe fn vco_setup(pll_src: u32, requested_output: u32, plln: usize) -> PllConfigResults {
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use crate::pac::rcc::vals::{Pll1rge, Pll1vcosel};
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let (vco_ck_target, pll_x_p) = vco_output_divider_setup(requested_output, plln);
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// Input divisor, resulting in a reference clock in the range
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// 1 to 2 MHz. Choose the highest reference clock (lowest m)
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let pll_x_m = (pll_src + 1_999_999) / 2_000_000;
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assert!(pll_x_m < 64);
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// Calculate resulting reference clock
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let ref_x_ck = pll_src / pll_x_m;
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assert!((1_000_000..=2_000_000).contains(&ref_x_ck));
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RCC.pllcfgr().modify(|w| {
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w.set_pllvcosel(plln, Pll1vcosel::MEDIUMVCO);
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w.set_pllrge(plln, Pll1rge::RANGE1);
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});
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PllConfigResults {
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ref_x_ck,
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pll_x_m,
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pll_x_p,
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vco_ck_target,
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}
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}
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/// # Safety
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///
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/// Must have exclusive access to the RCC register block
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pub(super) unsafe fn pll_setup(
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pll_src: u32,
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config: &PllConfig,
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plln: usize,
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) -> (Option<u32>, Option<u32>, Option<u32>) {
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use crate::pac::rcc::vals::{Divp1, Divp1en, Pll1fracen};
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match config.p_ck {
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Some(requested_output) => {
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let config_results = vco_setup(pll_src, requested_output.0, plln);
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let PllConfigResults {
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ref_x_ck,
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pll_x_m,
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pll_x_p,
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vco_ck_target,
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} = config_results;
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RCC.pllckselr().modify(|w| w.set_divm(plln, pll_x_m as u8));
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// Feedback divider. Integer only
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let pll_x_n = vco_ck_target / ref_x_ck;
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assert!(pll_x_n >= 4);
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assert!(pll_x_n <= 512);
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RCC.plldivr(plln)
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.modify(|w| w.set_divn1((pll_x_n - 1) as u16));
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// No FRACN
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RCC.pllcfgr()
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.modify(|w| w.set_pllfracen(plln, Pll1fracen::RESET));
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let vco_ck = ref_x_ck * pll_x_n;
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RCC.plldivr(plln)
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.modify(|w| w.set_divp1(Divp1((pll_x_p - 1) as u8)));
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RCC.pllcfgr()
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.modify(|w| w.set_divpen(plln, Divp1en::ENABLED));
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// Calulate additional output dividers
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let q_ck = match config.q_ck {
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Some(Hertz(ck)) if ck > 0 => {
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let div = (vco_ck + ck - 1) / ck;
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RCC.plldivr(plln).modify(|w| w.set_divq1((div - 1) as u8));
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RCC.pllcfgr()
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.modify(|w| w.set_divqen(plln, Divp1en::ENABLED));
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Some(vco_ck / div)
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}
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_ => None,
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};
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let r_ck = match config.r_ck {
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Some(Hertz(ck)) if ck > 0 => {
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let div = (vco_ck + ck - 1) / ck;
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RCC.plldivr(plln).modify(|w| w.set_divr1((div - 1) as u8));
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RCC.pllcfgr()
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.modify(|w| w.set_divren(plln, Divp1en::ENABLED));
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Some(vco_ck / div)
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}
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_ => None,
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};
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(Some(vco_ck / pll_x_p), q_ck, r_ck)
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}
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None => {
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assert!(
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config.q_ck.is_none(),
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"Must set PLL P clock for Q clock to take effect!"
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);
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assert!(
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config.r_ck.is_none(),
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"Must set PLL P clock for R clock to take effect!"
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);
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(None, None, None)
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}
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}
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}
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