143 lines
3.5 KiB
Rust
143 lines
3.5 KiB
Rust
use crate::mdio::MdioBus;
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#[allow(dead_code, non_camel_case_types, clippy::upper_case_acronyms)]
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#[repr(u8)]
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/// Clause 22 Registers
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pub enum RegsC22 {
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/// MII Control Register
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CONTROL = 0x00,
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/// MII Status Register
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STATUS = 0x01,
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/// PHY Identifier 1 Register
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PHY_ID1 = 0x02,
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/// PHY Identifier 2 Register.
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PHY_ID2 = 0x03,
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}
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/// Clause 45 Registers
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#[allow(non_snake_case, dead_code)]
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pub mod RegsC45 {
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/// Device Address: 0x01
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#[allow(non_camel_case_types, clippy::upper_case_acronyms)]
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#[repr(u16)]
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pub enum DA1 {
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/// PMA/PMD Control 1 Register
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PMA_PMD_CNTRL1 = 0x0000,
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/// PMA/PMD Status 1 Register
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PMA_PMD_STAT1 = 0x0001,
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/// MSE Value Register
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MSE_VAL = 0x830B,
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}
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impl DA1 {
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#[must_use]
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pub fn into(self) -> (u8, u16) {
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(0x01, self as u16)
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}
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}
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/// Device Address: 0x03
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#[allow(non_camel_case_types, clippy::upper_case_acronyms)]
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#[repr(u16)]
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pub enum DA3 {
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/// PCS Control 1 Register
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PCS_CNTRL1 = 0x0000,
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/// PCS Status 1 Register
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PCS_STAT1 = 0x0001,
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/// PCS Status 2 Register
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PCS_STAT2 = 0x0008,
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}
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impl DA3 {
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#[must_use]
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pub fn into(self) -> (u8, u16) {
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(0x03, self as u16)
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}
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}
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/// Device Address: 0x07
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#[allow(non_camel_case_types, clippy::upper_case_acronyms)]
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#[repr(u16)]
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pub enum DA7 {
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/// Extra Autonegotiation Status Register
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AN_STATUS_EXTRA = 0x8001,
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}
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impl DA7 {
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#[must_use]
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pub fn into(self) -> (u8, u16) {
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(0x07, self as u16)
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}
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}
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/// Device Address: 0x1E
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#[allow(non_camel_case_types, clippy::upper_case_acronyms)]
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#[repr(u16)]
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pub enum DA1E {
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/// System Interrupt Status Register
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CRSM_IRQ_STATUS = 0x0010,
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/// System Interrupt Mask Register
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CRSM_IRQ_MASK = 0x0020,
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/// Pin Mux Configuration 1 Register
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DIGIO_PINMUX = 0x8c56,
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/// LED Control Register.
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LED_CNTRL = 0x8C82,
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/// LED Polarity Register
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LED_POLARITY = 0x8C83,
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}
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impl DA1E {
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#[must_use]
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pub fn into(self) -> (u8, u16) {
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(0x1e, self as u16)
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}
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}
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/// Device Address: 0x1F
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#[allow(non_camel_case_types, clippy::upper_case_acronyms)]
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#[repr(u16)]
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pub enum DA1F {
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/// PHY Subsystem Interrupt Status Register
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PHY_SYBSYS_IRQ_STATUS = 0x0011,
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/// PHY Subsystem Interrupt Mask Register
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PHY_SYBSYS_IRQ_MASK = 0x0021,
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}
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impl DA1F {
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#[must_use]
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pub fn into(self) -> (u8, u16) {
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(0x1f, self as u16)
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}
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}
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}
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pub struct Phy10BaseT1x(u8);
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impl Default for Phy10BaseT1x {
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fn default() -> Self {
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Self(0x01)
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}
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}
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impl Phy10BaseT1x {
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/// Get the both parts of the PHYID.
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pub async fn get_id<MDIOBUS, MDE>(&self, mdiobus: &mut MDIOBUS) -> Result<u32, MDE>
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where
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MDIOBUS: MdioBus<Error = MDE>,
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MDE: core::fmt::Debug,
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{
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let mut phyid = u32::from(mdiobus.read_cl22(self.0, RegsC22::PHY_ID1 as u8).await?) << 16;
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phyid |= u32::from(mdiobus.read_cl22(self.0, RegsC22::PHY_ID2 as u8).await?);
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Ok(phyid)
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}
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/// Get the Mean Squared Error Value.
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pub async fn get_sqi<MDIOBUS, MDE>(&self, mdiobus: &mut MDIOBUS) -> Result<u16, MDE>
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where
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MDIOBUS: MdioBus<Error = MDE>,
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MDE: core::fmt::Debug,
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{
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mdiobus.read_cl45(self.0, RegsC45::DA1::MSE_VAL.into()).await
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}
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}
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