322 lines
10 KiB
Rust
322 lines
10 KiB
Rust
mod descriptors;
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use core::sync::atomic::{fence, Ordering};
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use embassy_cortex_m::interrupt::Interrupt;
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use embassy_hal_common::{into_ref, PeripheralRef};
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pub(crate) use self::descriptors::{RDes, RDesRing, TDes, TDesRing};
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use super::*;
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use crate::gpio::sealed::{AFType, Pin as _};
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use crate::gpio::{AnyPin, Speed};
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use crate::pac::ETH;
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use crate::{interrupt, Peripheral};
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/// Interrupt handler.
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pub struct InterruptHandler {}
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impl interrupt::Handler<interrupt::ETH> for InterruptHandler {
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unsafe fn on_interrupt() {
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WAKER.wake();
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// TODO: Check and clear more flags
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unsafe {
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let dma = ETH.ethernet_dma();
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dma.dmacsr().modify(|w| {
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w.set_ti(true);
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w.set_ri(true);
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w.set_nis(true);
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});
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// Delay two peripheral's clock
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dma.dmacsr().read();
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dma.dmacsr().read();
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}
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}
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}
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const MTU: usize = 1514; // 14 Ethernet header + 1500 IP packet
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pub struct Ethernet<'d, T: Instance, P: PHY> {
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_peri: PeripheralRef<'d, T>,
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pub(crate) tx: TDesRing<'d>,
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pub(crate) rx: RDesRing<'d>,
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pins: [PeripheralRef<'d, AnyPin>; 9],
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_phy: P,
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clock_range: u8,
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phy_addr: u8,
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pub(crate) mac_addr: [u8; 6],
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}
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macro_rules! config_pins {
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($($pin:ident),*) => {
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// NOTE(unsafe) Exclusive access to the registers
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critical_section::with(|_| {
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$(
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$pin.set_as_af($pin.af_num(), AFType::OutputPushPull);
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$pin.set_speed(Speed::VeryHigh);
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)*
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})
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};
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}
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impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
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pub fn new<const TX: usize, const RX: usize>(
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queue: &'d mut PacketQueue<TX, RX>,
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peri: impl Peripheral<P = T> + 'd,
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_irq: impl interrupt::Binding<interrupt::ETH, InterruptHandler> + 'd,
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ref_clk: impl Peripheral<P = impl RefClkPin<T>> + 'd,
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mdio: impl Peripheral<P = impl MDIOPin<T>> + 'd,
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mdc: impl Peripheral<P = impl MDCPin<T>> + 'd,
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crs: impl Peripheral<P = impl CRSPin<T>> + 'd,
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rx_d0: impl Peripheral<P = impl RXD0Pin<T>> + 'd,
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rx_d1: impl Peripheral<P = impl RXD1Pin<T>> + 'd,
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tx_d0: impl Peripheral<P = impl TXD0Pin<T>> + 'd,
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tx_d1: impl Peripheral<P = impl TXD1Pin<T>> + 'd,
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tx_en: impl Peripheral<P = impl TXEnPin<T>> + 'd,
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phy: P,
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mac_addr: [u8; 6],
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phy_addr: u8,
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) -> Self {
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into_ref!(peri, ref_clk, mdio, mdc, crs, rx_d0, rx_d1, tx_d0, tx_d1, tx_en);
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unsafe {
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// Enable the necessary Clocks
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// NOTE(unsafe) We have exclusive access to the registers
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#[cfg(not(rcc_h5))]
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critical_section::with(|_| {
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crate::pac::RCC.apb4enr().modify(|w| w.set_syscfgen(true));
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crate::pac::RCC.ahb1enr().modify(|w| {
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w.set_eth1macen(true);
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w.set_eth1txen(true);
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w.set_eth1rxen(true);
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});
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// RMII
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crate::pac::SYSCFG.pmcr().modify(|w| w.set_epis(0b100));
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});
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#[cfg(rcc_h5)]
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critical_section::with(|_| {
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crate::pac::RCC.apb3enr().modify(|w| w.set_sbsen(true));
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crate::pac::RCC.ahb1enr().modify(|w| {
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w.set_ethen(true);
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w.set_ethtxen(true);
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w.set_ethrxen(true);
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});
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// RMII
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crate::pac::SBS
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.pmcr()
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.modify(|w| w.set_eth_sel_phy(crate::pac::sbs::vals::EthSelPhy::B_0X4));
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});
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config_pins!(ref_clk, mdio, mdc, crs, rx_d0, rx_d1, tx_d0, tx_d1, tx_en);
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// NOTE(unsafe) We have exclusive access to the registers
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let dma = ETH.ethernet_dma();
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let mac = ETH.ethernet_mac();
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let mtl = ETH.ethernet_mtl();
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// Reset and wait
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dma.dmamr().modify(|w| w.set_swr(true));
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while dma.dmamr().read().swr() {}
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mac.maccr().modify(|w| {
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w.set_ipg(0b000); // 96 bit times
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w.set_acs(true);
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w.set_fes(true);
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w.set_dm(true);
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// TODO: Carrier sense ? ECRSFD
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});
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// Note: Writing to LR triggers synchronisation of both LR and HR into the MAC core,
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// so the LR write must happen after the HR write.
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mac.maca0hr()
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.modify(|w| w.set_addrhi(u16::from(mac_addr[4]) | (u16::from(mac_addr[5]) << 8)));
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mac.maca0lr().write(|w| {
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w.set_addrlo(
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u32::from(mac_addr[0])
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| (u32::from(mac_addr[1]) << 8)
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| (u32::from(mac_addr[2]) << 16)
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| (u32::from(mac_addr[3]) << 24),
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)
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});
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mac.macqtx_fcr().modify(|w| w.set_pt(0x100));
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// disable all MMC RX interrupts
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mac.mmc_rx_interrupt_mask().write(|w| {
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w.set_rxcrcerpim(true);
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w.set_rxalgnerpim(true);
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w.set_rxucgpim(true);
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w.set_rxlpiuscim(true);
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w.set_rxlpitrcim(true)
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});
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// disable all MMC TX interrupts
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mac.mmc_tx_interrupt_mask().write(|w| {
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w.set_txscolgpim(true);
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w.set_txmcolgpim(true);
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w.set_txgpktim(true);
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w.set_txlpiuscim(true);
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w.set_txlpitrcim(true);
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});
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mtl.mtlrx_qomr().modify(|w| w.set_rsf(true));
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mtl.mtltx_qomr().modify(|w| w.set_tsf(true));
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dma.dmactx_cr().modify(|w| w.set_txpbl(1)); // 32 ?
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dma.dmacrx_cr().modify(|w| {
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w.set_rxpbl(1); // 32 ?
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w.set_rbsz(MTU as u16);
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});
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// NOTE(unsafe) We got the peripheral singleton, which means that `rcc::init` was called
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let hclk = crate::rcc::get_freqs().ahb1;
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let hclk_mhz = hclk.0 / 1_000_000;
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// Set the MDC clock frequency in the range 1MHz - 2.5MHz
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let clock_range = match hclk_mhz {
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0..=34 => 2, // Divide by 16
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35..=59 => 3, // Divide by 26
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60..=99 => 0, // Divide by 42
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100..=149 => 1, // Divide by 62
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150..=249 => 4, // Divide by 102
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250..=310 => 5, // Divide by 124
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_ => {
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panic!("HCLK results in MDC clock > 2.5MHz even for the highest CSR clock divider")
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}
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};
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let pins = [
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ref_clk.map_into(),
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mdio.map_into(),
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mdc.map_into(),
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crs.map_into(),
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rx_d0.map_into(),
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rx_d1.map_into(),
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tx_d0.map_into(),
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tx_d1.map_into(),
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tx_en.map_into(),
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];
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let mut this = Self {
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_peri: peri,
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tx: TDesRing::new(&mut queue.tx_desc, &mut queue.tx_buf),
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rx: RDesRing::new(&mut queue.rx_desc, &mut queue.rx_buf),
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pins,
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_phy: phy,
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clock_range,
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phy_addr,
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mac_addr,
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};
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fence(Ordering::SeqCst);
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let mac = ETH.ethernet_mac();
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let mtl = ETH.ethernet_mtl();
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let dma = ETH.ethernet_dma();
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mac.maccr().modify(|w| {
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w.set_re(true);
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w.set_te(true);
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});
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mtl.mtltx_qomr().modify(|w| w.set_ftq(true));
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dma.dmactx_cr().modify(|w| w.set_st(true));
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dma.dmacrx_cr().modify(|w| w.set_sr(true));
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// Enable interrupts
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dma.dmacier().modify(|w| {
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w.set_nie(true);
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w.set_rie(true);
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w.set_tie(true);
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});
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P::phy_reset(&mut this);
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P::phy_init(&mut this);
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interrupt::ETH::unpend();
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interrupt::ETH::enable();
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this
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}
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}
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}
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unsafe impl<'d, T: Instance, P: PHY> StationManagement for Ethernet<'d, T, P> {
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fn smi_read(&mut self, reg: u8) -> u16 {
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// NOTE(unsafe) These registers aren't used in the interrupt and we have `&mut self`
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unsafe {
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let mac = ETH.ethernet_mac();
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mac.macmdioar().modify(|w| {
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w.set_pa(self.phy_addr);
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w.set_rda(reg);
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w.set_goc(0b11); // read
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w.set_cr(self.clock_range);
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w.set_mb(true);
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});
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while mac.macmdioar().read().mb() {}
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mac.macmdiodr().read().md()
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}
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}
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fn smi_write(&mut self, reg: u8, val: u16) {
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// NOTE(unsafe) These registers aren't used in the interrupt and we have `&mut self`
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unsafe {
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let mac = ETH.ethernet_mac();
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mac.macmdiodr().write(|w| w.set_md(val));
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mac.macmdioar().modify(|w| {
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w.set_pa(self.phy_addr);
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w.set_rda(reg);
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w.set_goc(0b01); // write
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w.set_cr(self.clock_range);
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w.set_mb(true);
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});
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while mac.macmdioar().read().mb() {}
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}
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}
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}
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impl<'d, T: Instance, P: PHY> Drop for Ethernet<'d, T, P> {
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fn drop(&mut self) {
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// NOTE(unsafe) We have `&mut self` and the interrupt doesn't use this registers
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unsafe {
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let dma = ETH.ethernet_dma();
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let mac = ETH.ethernet_mac();
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let mtl = ETH.ethernet_mtl();
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// Disable the TX DMA and wait for any previous transmissions to be completed
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dma.dmactx_cr().modify(|w| w.set_st(false));
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while {
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let txqueue = mtl.mtltx_qdr().read();
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txqueue.trcsts() == 0b01 || txqueue.txqsts()
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} {}
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// Disable MAC transmitter and receiver
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mac.maccr().modify(|w| {
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w.set_re(false);
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w.set_te(false);
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});
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// Wait for previous receiver transfers to be completed and then disable the RX DMA
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while {
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let rxqueue = mtl.mtlrx_qdr().read();
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rxqueue.rxqsts() != 0b00 || rxqueue.prxq() != 0
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} {}
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dma.dmacrx_cr().modify(|w| w.set_sr(false));
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}
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// NOTE(unsafe) Exclusive access to the regs
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critical_section::with(|_| unsafe {
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for pin in self.pins.iter_mut() {
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pin.set_as_disconnected();
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}
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})
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}
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}
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