434 lines
15 KiB
Rust
434 lines
15 KiB
Rust
use core::ops::Range;
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use core::sync::atomic::{compiler_fence, Ordering};
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use super::word::Word;
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/// A "read-only" ring-buffer to be used together with the DMA controller which
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/// writes in a circular way, "uncontrolled" to the buffer.
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///
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/// A snapshot of the ring buffer state can be attained by setting the `ndtr` field
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/// to the current register value. `ndtr` describes the current position of the DMA
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/// write.
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///
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/// # Safety
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///
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/// The ring buffer controls the TCIF (transfer completed interrupt flag) to
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/// detect buffer overruns, hence this interrupt must be disabled.
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/// The buffer can detect overruns up to one period, that is, for a X byte buffer,
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/// overruns can be detected if they happen from byte X+1 up to 2X. After this
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/// point, overrunds may or may not be detected.
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///
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/// # Buffer layout
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///
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/// ```text
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/// Without wraparound: With wraparound:
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///
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/// + buf +--- NDTR ---+ + buf +---------- NDTR ----------+
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/// | | | | | |
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/// v v v v v v
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/// +-----------------------------------------+ +-----------------------------------------+
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/// |oooooooooooXXXXXXXXXXXXXXXXoooooooooooooo| |XXXXXXXXXXXXXooooooooooooXXXXXXXXXXXXXXXX|
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/// +-----------------------------------------+ +-----------------------------------------+
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/// ^ ^ ^ ^ ^ ^
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/// | | | | | |
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/// +- first --+ | +- end ------+ |
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/// | | | |
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/// +- end --------------------+ +- first ----------------+
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/// ```
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pub struct DmaRingBuffer<'a, W: Word> {
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pub(crate) dma_buf: &'a mut [W],
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first: usize,
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pub ndtr: usize,
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expect_next_read_to_wrap: bool,
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}
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#[derive(Debug, PartialEq)]
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pub struct OverrunError;
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pub trait DmaCtrl {
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/// Get the NDTR register value, i.e. the space left in the underlying
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/// buffer until the dma writer wraps.
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fn ndtr(&self) -> usize;
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/// Read the transfer completed interrupt flag
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/// This flag is set by the dma controller when NDTR is reloaded,
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/// i.e. when the writing wraps.
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fn tcif(&self) -> bool;
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/// Clear the transfer completed interrupt flag
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fn clear_tcif(&mut self);
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}
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impl<'a, W: Word> DmaRingBuffer<'a, W> {
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pub fn new(dma_buf: &'a mut [W]) -> Self {
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let ndtr = dma_buf.len();
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Self {
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dma_buf,
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first: 0,
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ndtr,
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expect_next_read_to_wrap: false,
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}
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}
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/// Reset the ring buffer to its initial state
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pub fn clear(&mut self) {
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self.first = 0;
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self.ndtr = self.dma_buf.len();
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self.expect_next_read_to_wrap = false;
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}
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/// The buffer end position
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fn end(&self) -> usize {
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self.dma_buf.len() - self.ndtr
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}
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/// Returns whether the buffer is empty
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#[allow(dead_code)]
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pub fn is_empty(&self) -> bool {
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self.first == self.end()
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}
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/// The current number of bytes in the buffer
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/// This may change at any time if dma is currently active
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#[allow(dead_code)]
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pub fn len(&self) -> usize {
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// Read out a stable end (the dma periheral can change it at anytime)
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let end = self.end();
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if self.first <= end {
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// No wrap
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end - self.first
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} else {
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self.dma_buf.len() - self.first + end
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}
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}
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/// Read bytes from the ring buffer
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/// OverrunError is returned if the portion to be read was overwritten by the DMA controller.
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pub fn read(&mut self, dma: &mut impl DmaCtrl, buf: &mut [W]) -> Result<usize, OverrunError> {
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let end = self.end();
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compiler_fence(Ordering::SeqCst);
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if self.first == end {
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// The buffer is currently empty
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if dma.tcif() {
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// The dma controller has written such that the ring buffer now wraps
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// This is the special case where exactly n*dma_buf.len(), n = 1,2,..., bytes was written,
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// but where additional bytes are now written causing the ring buffer to wrap.
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// This is only an error if the writing has passed the current unread region.
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self.ndtr = dma.ndtr();
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if self.end() > self.first {
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dma.clear_tcif();
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return Err(OverrunError);
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}
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}
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self.expect_next_read_to_wrap = false;
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Ok(0)
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} else if self.first < end {
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// The available, unread portion in the ring buffer DOES NOT wrap
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if self.expect_next_read_to_wrap {
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// The read was expected to wrap but it did not
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dma.clear_tcif();
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return Err(OverrunError);
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}
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// Copy out the bytes from the dma buffer
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let len = self.copy_to(buf, self.first..end);
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compiler_fence(Ordering::SeqCst);
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if dma.tcif() {
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// The dma controller has written such that the ring buffer now wraps
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self.ndtr = dma.ndtr();
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if self.end() > self.first {
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// The bytes that we have copied out have overflowed
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// as the writer has now both wrapped and is currently writing
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// within the region that we have just copied out
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// Clear transfer completed interrupt flag
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dma.clear_tcif();
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return Err(OverrunError);
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}
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}
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self.first = (self.first + len) % self.dma_buf.len();
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self.expect_next_read_to_wrap = false;
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Ok(len)
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} else {
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// The available, unread portion in the ring buffer DOES wrap
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// The dma controller has wrapped since we last read and is currently
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// writing (or the next byte added will be) in the beginning of the ring buffer.
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// If the unread portion wraps then the writer must also have wrapped,
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// or it has wrapped and we already cleared the TCIF flag
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assert!(dma.tcif() || self.expect_next_read_to_wrap);
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// Clear transfer completed interrupt flag
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dma.clear_tcif();
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if self.first + buf.len() < self.dma_buf.len() {
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// The provided read buffer is not large enough to include all bytes from the tail of the dma buffer.
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// Copy out from the dma buffer
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let len = self.copy_to(buf, self.first..self.dma_buf.len());
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compiler_fence(Ordering::SeqCst);
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// We have now copied out the data from dma_buf
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// Make sure that the just read part was not overwritten during the copy
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self.ndtr = dma.ndtr();
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if self.end() > self.first || dma.tcif() {
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// The writer has entered the data that we have just read since we read out `end` in the beginning and until now.
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return Err(OverrunError);
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}
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self.first = (self.first + len) % self.dma_buf.len();
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self.expect_next_read_to_wrap = true;
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Ok(len)
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} else {
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// The provided read buffer is large enough to include all bytes from the tail of the dma buffer,
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// so the next read will not have any unread tail bytes in the ring buffer.
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// Copy out from the dma buffer
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let tail = self.copy_to(buf, self.first..self.dma_buf.len());
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let head = self.copy_to(&mut buf[tail..], 0..end);
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compiler_fence(Ordering::SeqCst);
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// We have now copied out the data from dma_buf
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// Make sure that the just read part was not overwritten during the copy
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self.ndtr = dma.ndtr();
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if self.end() > self.first || dma.tcif() {
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return Err(OverrunError);
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}
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self.first = head;
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self.expect_next_read_to_wrap = false;
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Ok(tail + head)
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}
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}
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}
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/// Copy from the dma buffer at `data_range` into `buf`
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fn copy_to(&mut self, buf: &mut [W], data_range: Range<usize>) -> usize {
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// Limit the number of bytes that can be copied
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let length = usize::min(data_range.len(), buf.len());
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// Copy from dma buffer into read buffer
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// We need to do it like this instead of a simple copy_from_slice() because
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// reading from a part of memory that may be simultaneously written to is unsafe
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unsafe {
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let dma_buf = self.dma_buf.as_ptr();
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for i in 0..length {
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buf[i] = core::ptr::read_volatile(dma_buf.offset((data_range.start + i) as isize));
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}
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}
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length
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}
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}
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#[cfg(test)]
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mod tests {
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use core::array;
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use core::cell::RefCell;
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use super::*;
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struct TestCtrl {
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next_ndtr: RefCell<Option<usize>>,
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tcif: bool,
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}
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impl TestCtrl {
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pub const fn new() -> Self {
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Self {
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next_ndtr: RefCell::new(None),
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tcif: false,
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}
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}
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pub fn set_next_ndtr(&mut self, ndtr: usize) {
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self.next_ndtr.borrow_mut().replace(ndtr);
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}
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}
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impl DmaCtrl for TestCtrl {
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fn ndtr(&self) -> usize {
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self.next_ndtr.borrow_mut().unwrap()
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}
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fn tcif(&self) -> bool {
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self.tcif
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}
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fn clear_tcif(&mut self) {
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self.tcif = false;
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}
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}
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#[test]
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fn empty() {
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let mut dma_buf = [0u8; 16];
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let ringbuf = DmaRingBuffer::new(&mut dma_buf);
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assert!(ringbuf.is_empty());
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assert_eq!(0, ringbuf.len());
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}
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#[test]
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fn can_read() {
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let mut dma_buf: [u8; 16] = array::from_fn(|idx| idx as u8); // 0, 1, ..., 15
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let mut ctrl = TestCtrl::new();
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let mut ringbuf = DmaRingBuffer::new(&mut dma_buf);
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ringbuf.ndtr = 6;
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assert!(!ringbuf.is_empty());
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assert_eq!(10, ringbuf.len());
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let mut buf = [0; 2];
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assert_eq!(2, ringbuf.read(&mut ctrl, &mut buf).unwrap());
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assert_eq!([0, 1], buf);
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assert_eq!(8, ringbuf.len());
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let mut buf = [0; 2];
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assert_eq!(2, ringbuf.read(&mut ctrl, &mut buf).unwrap());
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assert_eq!([2, 3], buf);
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assert_eq!(6, ringbuf.len());
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let mut buf = [0; 8];
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assert_eq!(6, ringbuf.read(&mut ctrl, &mut buf).unwrap());
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assert_eq!([4, 5, 6, 7, 8, 9], buf[..6]);
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assert_eq!(0, ringbuf.len());
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let mut buf = [0; 2];
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assert_eq!(0, ringbuf.read(&mut ctrl, &mut buf).unwrap());
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}
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#[test]
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fn can_read_with_wrap() {
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let mut dma_buf: [u8; 16] = array::from_fn(|idx| idx as u8); // 0, 1, ..., 15
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let mut ctrl = TestCtrl::new();
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let mut ringbuf = DmaRingBuffer::new(&mut dma_buf);
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ringbuf.first = 12;
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ringbuf.ndtr = 10;
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// The dma controller has written 4 + 6 bytes and has reloaded NDTR
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ctrl.tcif = true;
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ctrl.set_next_ndtr(10);
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assert!(!ringbuf.is_empty());
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assert_eq!(6 + 4, ringbuf.len());
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let mut buf = [0; 2];
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assert_eq!(2, ringbuf.read(&mut ctrl, &mut buf).unwrap());
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assert_eq!([12, 13], buf);
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assert_eq!(6 + 2, ringbuf.len());
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let mut buf = [0; 4];
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assert_eq!(4, ringbuf.read(&mut ctrl, &mut buf).unwrap());
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assert_eq!([14, 15, 0, 1], buf);
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assert_eq!(4, ringbuf.len());
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}
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#[test]
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fn can_read_when_dma_writer_is_wrapped_and_read_does_not_wrap() {
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let mut dma_buf: [u8; 16] = array::from_fn(|idx| idx as u8); // 0, 1, ..., 15
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let mut ctrl = TestCtrl::new();
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let mut ringbuf = DmaRingBuffer::new(&mut dma_buf);
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ringbuf.first = 2;
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ringbuf.ndtr = 6;
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// The dma controller has written 6 + 2 bytes and has reloaded NDTR
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ctrl.tcif = true;
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ctrl.set_next_ndtr(14);
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let mut buf = [0; 2];
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assert_eq!(2, ringbuf.read(&mut ctrl, &mut buf).unwrap());
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assert_eq!([2, 3], buf);
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assert_eq!(true, ctrl.tcif); // The interrupt flag IS NOT cleared
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}
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#[test]
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fn can_read_when_dma_writer_is_wrapped_and_read_wraps() {
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let mut dma_buf: [u8; 16] = array::from_fn(|idx| idx as u8); // 0, 1, ..., 15
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let mut ctrl = TestCtrl::new();
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let mut ringbuf = DmaRingBuffer::new(&mut dma_buf);
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ringbuf.first = 12;
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ringbuf.ndtr = 10;
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// The dma controller has written 6 + 2 bytes and has reloaded NDTR
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ctrl.tcif = true;
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ctrl.set_next_ndtr(14);
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let mut buf = [0; 10];
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assert_eq!(10, ringbuf.read(&mut ctrl, &mut buf).unwrap());
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assert_eq!([12, 13, 14, 15, 0, 1, 2, 3, 4, 5], buf);
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assert_eq!(false, ctrl.tcif); // The interrupt flag IS cleared
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}
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#[test]
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fn cannot_read_when_dma_writer_wraps_with_same_ndtr() {
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let mut dma_buf = [0u8; 16];
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let mut ctrl = TestCtrl::new();
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let mut ringbuf = DmaRingBuffer::new(&mut dma_buf);
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ringbuf.first = 6;
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ringbuf.ndtr = 10;
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ctrl.set_next_ndtr(9);
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assert!(ringbuf.is_empty()); // The ring buffer thinks that it is empty
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// The dma controller has written exactly 16 bytes
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ctrl.tcif = true;
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let mut buf = [0; 2];
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assert_eq!(Err(OverrunError), ringbuf.read(&mut ctrl, &mut buf));
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assert_eq!(false, ctrl.tcif); // The interrupt flag IS cleared
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}
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#[test]
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fn cannot_read_when_dma_writer_overwrites_during_not_wrapping_read() {
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let mut dma_buf: [u8; 16] = array::from_fn(|idx| idx as u8); // 0, 1, ..., 15
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let mut ctrl = TestCtrl::new();
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let mut ringbuf = DmaRingBuffer::new(&mut dma_buf);
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ringbuf.first = 2;
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ringbuf.ndtr = 6;
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// The dma controller has written 6 + 3 bytes and has reloaded NDTR
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ctrl.tcif = true;
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ctrl.set_next_ndtr(13);
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let mut buf = [0; 2];
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assert_eq!(Err(OverrunError), ringbuf.read(&mut ctrl, &mut buf));
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assert_eq!(false, ctrl.tcif); // The interrupt flag IS cleared
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}
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#[test]
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fn cannot_read_when_dma_writer_overwrites_during_wrapping_read() {
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let mut dma_buf: [u8; 16] = array::from_fn(|idx| idx as u8); // 0, 1, ..., 15
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let mut ctrl = TestCtrl::new();
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let mut ringbuf = DmaRingBuffer::new(&mut dma_buf);
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ringbuf.first = 12;
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ringbuf.ndtr = 10;
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// The dma controller has written 6 + 13 bytes and has reloaded NDTR
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ctrl.tcif = true;
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ctrl.set_next_ndtr(3);
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let mut buf = [0; 2];
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assert_eq!(Err(OverrunError), ringbuf.read(&mut ctrl, &mut buf));
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assert_eq!(false, ctrl.tcif); // The interrupt flag IS cleared
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}
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}
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