278 lines
8.5 KiB
Rust
278 lines
8.5 KiB
Rust
use core::future::Future;
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use core::pin::Pin;
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use core::sync::atomic::{compiler_fence, Ordering};
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use core::task::Poll;
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use embassy::traits;
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use embassy::util::WakerRegistration;
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use embassy_extras::peripheral::{PeripheralMutex, PeripheralState};
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use futures::future::poll_fn;
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use traits::spi::FullDuplex;
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use crate::interrupt::{self, Interrupt};
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use crate::{pac, slice_in_ram_or};
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pub use crate::hal::spim::{
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Frequency, Mode, Phase, Pins, Polarity, MODE_0, MODE_1, MODE_2, MODE_3,
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};
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#[derive(Debug, Clone, Copy, PartialEq, Eq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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#[non_exhaustive]
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pub enum Error {
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TxBufferTooLong,
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RxBufferTooLong,
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/// EasyDMA can only read from data memory, read only buffers in flash will fail.
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DMABufferNotInDataMemory,
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}
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struct State<T: Instance> {
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spim: T,
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waker: WakerRegistration,
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}
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pub struct Spim<T: Instance> {
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inner: PeripheralMutex<State<T>>,
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}
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pub struct Config {
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pub pins: Pins,
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pub frequency: Frequency,
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pub mode: Mode,
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pub orc: u8,
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}
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impl<T: Instance> Spim<T> {
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pub fn new(mut spim: T, irq: T::Interrupt, config: Config) -> Self {
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let r = spim.regs();
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// Select pins.
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r.psel.sck.write(|w| {
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unsafe { w.bits(config.pins.sck.psel_bits()) };
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w.connect().connected()
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});
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match config.pins.mosi {
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Some(mosi) => r.psel.mosi.write(|w| {
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unsafe { w.bits(mosi.psel_bits()) };
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w.connect().connected()
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}),
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None => r.psel.mosi.write(|w| w.connect().disconnected()),
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}
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match config.pins.miso {
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Some(miso) => r.psel.miso.write(|w| {
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unsafe { w.bits(miso.psel_bits()) };
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w.connect().connected()
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}),
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None => r.psel.miso.write(|w| w.connect().disconnected()),
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}
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// Enable SPIM instance.
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r.enable.write(|w| w.enable().enabled());
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// Configure mode.
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let mode = config.mode;
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r.config.write(|w| {
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// Can't match on `mode` due to embedded-hal, see https://github.com/rust-embedded/embedded-hal/pull/126
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if mode == MODE_0 {
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w.order().msb_first();
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w.cpol().active_high();
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w.cpha().leading();
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} else if mode == MODE_1 {
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w.order().msb_first();
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w.cpol().active_high();
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w.cpha().trailing();
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} else if mode == MODE_2 {
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w.order().msb_first();
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w.cpol().active_low();
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w.cpha().leading();
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} else {
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w.order().msb_first();
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w.cpol().active_low();
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w.cpha().trailing();
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}
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w
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});
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// Configure frequency.
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let frequency = config.frequency;
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r.frequency.write(|w| w.frequency().variant(frequency));
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// Set over-read character
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let orc = config.orc;
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r.orc.write(|w|
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// The ORC field is 8 bits long, so any u8 is a valid value to write.
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unsafe { w.orc().bits(orc) });
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// Disable all events interrupts
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r.intenclr.write(|w| unsafe { w.bits(0xFFFF_FFFF) });
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Self {
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inner: PeripheralMutex::new(
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State {
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spim,
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waker: WakerRegistration::new(),
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},
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irq,
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),
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}
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}
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fn inner(self: Pin<&mut Self>) -> Pin<&mut PeripheralMutex<State<T>>> {
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unsafe { Pin::new_unchecked(&mut self.get_unchecked_mut().inner) }
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}
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pub fn free(self: Pin<&mut Self>) -> (T, T::Interrupt) {
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let (state, irq) = self.inner().free();
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(state.spim, irq)
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}
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}
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impl<T: Instance> FullDuplex<u8> for Spim<T> {
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type Error = Error;
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#[rustfmt::skip]
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type WriteFuture<'a> where Self: 'a = impl Future<Output = Result<(), Self::Error>> + 'a;
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#[rustfmt::skip]
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type ReadFuture<'a> where Self: 'a = impl Future<Output = Result<(), Self::Error>> + 'a;
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#[rustfmt::skip]
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type WriteReadFuture<'a> where Self: 'a = impl Future<Output = Result<(), Self::Error>> + 'a;
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fn read<'a>(self: Pin<&'a mut Self>, data: &'a mut [u8]) -> Self::ReadFuture<'a> {
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async move { todo!() }
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}
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fn write<'a>(self: Pin<&'a mut Self>, data: &'a [u8]) -> Self::WriteFuture<'a> {
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async move { todo!() }
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}
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fn read_write<'a>(
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mut self: Pin<&'a mut Self>,
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rx: &'a mut [u8],
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tx: &'a [u8],
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) -> Self::WriteReadFuture<'a> {
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async move {
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slice_in_ram_or(rx, Error::DMABufferNotInDataMemory)?;
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slice_in_ram_or(tx, Error::DMABufferNotInDataMemory)?;
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self.as_mut().inner().with(|s, _irq| {
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// Conservative compiler fence to prevent optimizations that do not
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// take in to account actions by DMA. The fence has been placed here,
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// before any DMA action has started.
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compiler_fence(Ordering::SeqCst);
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let r = s.spim.regs();
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// Set up the DMA write.
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r.txd
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.ptr
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.write(|w| unsafe { w.ptr().bits(tx.as_ptr() as u32) });
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r.txd
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.maxcnt
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.write(|w| unsafe { w.maxcnt().bits(tx.len() as _) });
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// Set up the DMA read.
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r.rxd
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.ptr
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.write(|w| unsafe { w.ptr().bits(rx.as_mut_ptr() as u32) });
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r.rxd
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.maxcnt
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.write(|w| unsafe { w.maxcnt().bits(rx.len() as _) });
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// Reset and enable the event
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r.events_end.reset();
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r.intenset.write(|w| w.end().set());
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// Start SPI transaction.
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r.tasks_start.write(|w| unsafe { w.bits(1) });
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// Conservative compiler fence to prevent optimizations that do not
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// take in to account actions by DMA. The fence has been placed here,
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// after all possible DMA actions have completed.
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compiler_fence(Ordering::SeqCst);
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});
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// Wait for 'end' event.
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poll_fn(|cx| {
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self.as_mut().inner().with(|s, _irq| {
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let r = s.spim.regs();
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if r.events_end.read().bits() != 0 {
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return Poll::Ready(());
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}
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s.waker.register(cx.waker());
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Poll::Pending
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})
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})
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.await;
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Ok(())
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}
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}
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}
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impl<U: Instance> PeripheralState for State<U> {
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type Interrupt = U::Interrupt;
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fn on_interrupt(&mut self) {
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if self.spim.regs().events_end.read().bits() != 0 {
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self.spim.regs().intenclr.write(|w| w.end().clear());
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self.waker.wake()
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}
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}
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}
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mod sealed {
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pub trait Instance {}
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}
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pub trait Instance: sealed::Instance {
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type Interrupt: Interrupt;
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fn regs(&mut self) -> &pac::spim0::RegisterBlock;
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}
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impl sealed::Instance for pac::SPIM0 {}
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impl Instance for pac::SPIM0 {
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#[cfg(feature = "52810")]
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type Interrupt = interrupt::SPIM0_SPIS0_SPI0;
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#[cfg(not(feature = "52810"))]
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type Interrupt = interrupt::SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0;
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fn regs(&mut self) -> &pac::spim0::RegisterBlock {
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self
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}
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}
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#[cfg(any(feature = "52832", feature = "52833", feature = "52840"))]
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impl sealed::Instance for pac::SPIM1 {}
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#[cfg(any(feature = "52832", feature = "52833", feature = "52840"))]
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impl Instance for pac::SPIM1 {
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type Interrupt = interrupt::SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1;
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fn regs(&mut self) -> &pac::spim0::RegisterBlock {
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self
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}
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}
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#[cfg(any(feature = "52832", feature = "52833", feature = "52840"))]
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impl sealed::Instance for pac::SPIM2 {}
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#[cfg(any(feature = "52832", feature = "52833", feature = "52840"))]
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impl Instance for pac::SPIM2 {
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type Interrupt = interrupt::SPIM2_SPIS2_SPI2;
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fn regs(&mut self) -> &pac::spim0::RegisterBlock {
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self
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}
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}
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#[cfg(any(feature = "52833", feature = "52840"))]
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impl sealed::Instance for pac::SPIM3 {}
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#[cfg(any(feature = "52833", feature = "52840"))]
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impl Instance for pac::SPIM3 {
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type Interrupt = interrupt::SPIM3;
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fn regs(&mut self) -> &pac::spim0::RegisterBlock {
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self
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}
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}
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impl<T: sealed::Instance> sealed::Instance for &mut T {}
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impl<T: Instance> Instance for &mut T {
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type Interrupt = T::Interrupt;
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fn regs(&mut self) -> &pac::spim0::RegisterBlock {
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T::regs(*self)
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}
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}
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