428 lines
12 KiB
Rust
428 lines
12 KiB
Rust
use crate::adc::{AdcPin, Instance};
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use core::marker::PhantomData;
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use embassy::util::Unborrow;
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use embassy_hal_common::unborrow;
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use embedded_hal_02::blocking::delay::DelayUs;
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pub const VDDA_CALIB_MV: u32 = 3000;
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/// Sadly we cannot use `RccPeripheral::enable` since devices are quite inconsistent ADC clock
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/// configuration.
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fn enable() {
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critical_section::with(|_| unsafe {
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#[cfg(stm32h7)]
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crate::pac::RCC.apb2enr().modify(|w| w.set_adcen(true));
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#[cfg(stm32g0)]
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crate::pac::RCC.apbenr2().modify(|w| w.set_adcen(true));
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#[cfg(any(stm32l4, stm32l5, stm32wb))]
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crate::pac::RCC.ahb2enr().modify(|w| w.set_adcen(true));
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});
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}
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pub enum Resolution {
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TwelveBit,
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TenBit,
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EightBit,
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SixBit,
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}
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impl Default for Resolution {
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fn default() -> Self {
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Self::TwelveBit
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}
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}
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impl Resolution {
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fn res(&self) -> crate::pac::adc::vals::Res {
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match self {
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Resolution::TwelveBit => crate::pac::adc::vals::Res::TWELVEBIT,
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Resolution::TenBit => crate::pac::adc::vals::Res::TENBIT,
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Resolution::EightBit => crate::pac::adc::vals::Res::EIGHTBIT,
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Resolution::SixBit => crate::pac::adc::vals::Res::SIXBIT,
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}
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}
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fn to_max_count(&self) -> u32 {
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match self {
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Resolution::TwelveBit => (1 << 12) - 1,
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Resolution::TenBit => (1 << 10) - 1,
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Resolution::EightBit => (1 << 8) - 1,
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Resolution::SixBit => (1 << 6) - 1,
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}
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}
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}
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pub struct Vref;
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impl<T: Instance> AdcPin<T> for Vref {}
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impl<T: Instance> super::sealed::AdcPin<T> for Vref {
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fn channel(&self) -> u8 {
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#[cfg(not(stm32g0))]
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let val = 0;
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#[cfg(stm32g0)]
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let val = 13;
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val
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}
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}
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pub struct Temperature;
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impl<T: Instance> AdcPin<T> for Temperature {}
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impl<T: Instance> super::sealed::AdcPin<T> for Temperature {
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fn channel(&self) -> u8 {
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#[cfg(not(stm32g0))]
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let val = 17;
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#[cfg(stm32g0)]
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let val = 12;
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val
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}
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}
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pub struct Vbat;
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impl<T: Instance> AdcPin<T> for Vbat {}
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impl<T: Instance> super::sealed::AdcPin<T> for Vbat {
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fn channel(&self) -> u8 {
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#[cfg(not(stm32g0))]
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let val = 18;
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#[cfg(stm32g0)]
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let val = 14;
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val
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}
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}
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#[cfg(not(adc_g0))]
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mod sample_time {
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/// ADC sample time
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///
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/// The default setting is 2.5 ADC clock cycles.
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#[derive(Clone, Copy, Debug, Eq, PartialEq, Ord, PartialOrd)]
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pub enum SampleTime {
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/// 2.5 ADC clock cycles
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Cycles2_5 = 0b000,
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/// 6.5 ADC clock cycles
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Cycles6_5 = 0b001,
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/// 12.5 ADC clock cycles
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Cycles12_5 = 0b010,
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/// 24.5 ADC clock cycles
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Cycles24_5 = 0b011,
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/// 47.5 ADC clock cycles
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Cycles47_5 = 0b100,
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/// 92.5 ADC clock cycles
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Cycles92_5 = 0b101,
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/// 247.5 ADC clock cycles
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Cycles247_5 = 0b110,
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/// 640.5 ADC clock cycles
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Cycles640_5 = 0b111,
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}
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impl SampleTime {
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pub(crate) fn sample_time(&self) -> crate::pac::adc::vals::SampleTime {
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match self {
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SampleTime::Cycles2_5 => crate::pac::adc::vals::SampleTime::CYCLES2_5,
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SampleTime::Cycles6_5 => crate::pac::adc::vals::SampleTime::CYCLES6_5,
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SampleTime::Cycles12_5 => crate::pac::adc::vals::SampleTime::CYCLES12_5,
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SampleTime::Cycles24_5 => crate::pac::adc::vals::SampleTime::CYCLES24_5,
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SampleTime::Cycles47_5 => crate::pac::adc::vals::SampleTime::CYCLES47_5,
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SampleTime::Cycles92_5 => crate::pac::adc::vals::SampleTime::CYCLES92_5,
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SampleTime::Cycles247_5 => crate::pac::adc::vals::SampleTime::CYCLES247_5,
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SampleTime::Cycles640_5 => crate::pac::adc::vals::SampleTime::CYCLES640_5,
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}
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}
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}
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impl Default for SampleTime {
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fn default() -> Self {
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Self::Cycles2_5
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}
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}
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}
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#[cfg(adc_g0)]
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mod sample_time {
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/// ADC sample time
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///
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/// The default setting is 1.5 ADC clock cycles.
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#[derive(Clone, Copy, Debug, Eq, PartialEq, Ord, PartialOrd)]
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pub enum SampleTime {
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/// 1.5 ADC clock cycles
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Cycles1_5 = 0b000,
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/// 3.5 ADC clock cycles
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Cycles3_5 = 0b001,
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/// 7.5 ADC clock cycles
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Cycles7_5 = 0b010,
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/// 12.5 ADC clock cycles
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Cycles12_5 = 0b011,
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/// 19.5 ADC clock cycles
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Cycles19_5 = 0b100,
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/// 39.5 ADC clock cycles
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Cycles39_5 = 0b101,
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/// 79.5 ADC clock cycles
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Cycles79_5 = 0b110,
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/// 160.5 ADC clock cycles
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Cycles160_5 = 0b111,
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}
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impl SampleTime {
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pub(crate) fn sample_time(&self) -> crate::pac::adc::vals::SampleTime {
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match self {
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SampleTime::Cycles1_5 => crate::pac::adc::vals::SampleTime::CYCLES1_5,
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SampleTime::Cycles3_5 => crate::pac::adc::vals::SampleTime::CYCLES3_5,
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SampleTime::Cycles7_5 => crate::pac::adc::vals::SampleTime::CYCLES7_5,
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SampleTime::Cycles12_5 => crate::pac::adc::vals::SampleTime::CYCLES12_5,
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SampleTime::Cycles19_5 => crate::pac::adc::vals::SampleTime::CYCLES19_5,
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SampleTime::Cycles39_5 => crate::pac::adc::vals::SampleTime::CYCLES39_5,
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SampleTime::Cycles79_5 => crate::pac::adc::vals::SampleTime::CYCLES79_5,
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SampleTime::Cycles160_5 => crate::pac::adc::vals::SampleTime::CYCLES160_5,
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}
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}
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}
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impl Default for SampleTime {
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fn default() -> Self {
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Self::Cycles1_5
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}
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}
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}
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pub use sample_time::SampleTime;
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pub struct Adc<'d, T: Instance> {
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sample_time: SampleTime,
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calibrated_vdda: u32,
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resolution: Resolution,
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phantom: PhantomData<&'d mut T>,
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}
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impl<'d, T: Instance> Adc<'d, T> {
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pub fn new(_peri: impl Unborrow<Target = T> + 'd, delay: &mut impl DelayUs<u32>) -> Self {
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unborrow!(_peri);
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enable();
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unsafe {
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T::regs().cr().modify(|reg| {
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#[cfg(not(adc_g0))]
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reg.set_deeppwd(false);
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reg.set_advregen(true);
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});
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#[cfg(adc_g0)]
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T::regs().cfgr1().modify(|reg| {
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reg.set_chselrmod(true);
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});
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}
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delay.delay_us(20);
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unsafe {
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T::regs().cr().modify(|reg| {
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reg.set_adcal(true);
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});
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while T::regs().cr().read().adcal() {
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// spin
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}
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}
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delay.delay_us(1);
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Self {
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sample_time: Default::default(),
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resolution: Resolution::default(),
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calibrated_vdda: VDDA_CALIB_MV,
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phantom: PhantomData,
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}
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}
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pub fn enable_vref(&self, delay: &mut impl DelayUs<u32>) -> Vref {
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unsafe {
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T::common_regs().ccr().modify(|reg| {
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reg.set_vrefen(true);
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});
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}
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// "Table 24. Embedded internal voltage reference" states that it takes a maximum of 12 us
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// to stabilize the internal voltage reference, we wait a little more.
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// TODO: delay 15us
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//cortex_m::asm::delay(20_000_000);
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delay.delay_us(15);
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Vref {}
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}
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pub fn enable_temperature(&self) -> Temperature {
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unsafe {
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T::common_regs().ccr().modify(|reg| {
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reg.set_ch17sel(true);
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});
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}
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Temperature {}
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}
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pub fn enable_vbat(&self) -> Vbat {
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unsafe {
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T::common_regs().ccr().modify(|reg| {
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reg.set_ch18sel(true);
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});
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}
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Vbat {}
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}
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/// Calculates the system VDDA by sampling the internal VREF channel and comparing
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/// the result with the value stored at the factory. If the chip's VDDA is not stable, run
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/// this before each ADC conversion.
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#[cfg(not(stm32g0))] // TODO is this supposed to be public?
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#[allow(unused)] // TODO is this supposed to be public?
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fn calibrate(&mut self, vref: &mut Vref) {
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#[cfg(stm32l5)]
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let vref_cal: u32 = todo!();
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#[cfg(not(stm32l5))]
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let vref_cal = unsafe { crate::pac::VREFINTCAL.data().read().value() };
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let old_sample_time = self.sample_time;
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// "Table 24. Embedded internal voltage reference" states that the sample time needs to be
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// at a minimum 4 us. With 640.5 ADC cycles we have a minimum of 8 us at 80 MHz, leaving
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// some headroom.
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self.sample_time = SampleTime::Cycles640_5;
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// This can't actually fail, it's just in a result to satisfy hal trait
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let vref_samp = self.read(vref);
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self.sample_time = old_sample_time;
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self.calibrated_vdda = (VDDA_CALIB_MV * u32::from(vref_cal)) / u32::from(vref_samp);
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}
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pub fn set_sample_time(&mut self, sample_time: SampleTime) {
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self.sample_time = sample_time;
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}
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pub fn set_resolution(&mut self, resolution: Resolution) {
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self.resolution = resolution;
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}
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/// Convert a measurement to millivolts
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pub fn to_millivolts(&self, sample: u16) -> u16 {
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((u32::from(sample) * self.calibrated_vdda) / self.resolution.to_max_count()) as u16
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}
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/*
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/// Convert a raw sample from the `Temperature` to deg C
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pub fn to_degrees_centigrade(sample: u16) -> f32 {
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(130.0 - 30.0) / (VtempCal130::get().read() as f32 - VtempCal30::get().read() as f32)
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* (sample as f32 - VtempCal30::get().read() as f32)
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+ 30.0
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}
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*/
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/// Perform a single conversion.
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fn convert(&mut self) -> u16 {
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unsafe {
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T::regs().isr().modify(|reg| {
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reg.set_eos(true);
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reg.set_eoc(true);
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});
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// Start conversion
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T::regs().cr().modify(|reg| {
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reg.set_adstart(true);
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});
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while !T::regs().isr().read().eos() {
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// spin
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}
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T::regs().dr().read().0 as u16
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}
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}
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pub fn read(&mut self, pin: &mut impl AdcPin<T>) -> u16 {
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unsafe {
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// Make sure bits are off
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while T::regs().cr().read().addis() {
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// spin
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}
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// Enable ADC
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T::regs().isr().modify(|reg| {
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reg.set_adrdy(true);
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});
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T::regs().cr().modify(|reg| {
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reg.set_aden(true);
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});
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while !T::regs().isr().read().adrdy() {
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// spin
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}
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// Configure ADC
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#[cfg(not(stm32g0))]
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T::regs()
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.cfgr()
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.modify(|reg| reg.set_res(self.resolution.res()));
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#[cfg(stm32g0)]
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T::regs()
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.cfgr1()
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.modify(|reg| reg.set_res(self.resolution.res()));
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// Configure channel
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Self::set_channel_sample_time(pin.channel(), self.sample_time);
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// Select channel
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#[cfg(not(stm32g0))]
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T::regs().sqr1().write(|reg| reg.set_sq(0, pin.channel()));
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#[cfg(stm32g0)]
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T::regs()
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.chselr()
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.write(|reg| reg.set_chsel(pin.channel() as u32));
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// Some models are affected by an erratum:
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// If we perform conversions slower than 1 kHz, the first read ADC value can be
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// corrupted, so we discard it and measure again.
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//
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// STM32L471xx: Section 2.7.3
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// STM32G4: Section 2.7.3
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#[cfg(any(rcc_l4, rcc_g4))]
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let _ = self.convert();
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let val = self.convert();
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T::regs().cr().modify(|reg| reg.set_addis(true));
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val
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}
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}
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#[cfg(stm32g0)]
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unsafe fn set_channel_sample_time(_ch: u8, sample_time: SampleTime) {
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T::regs()
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.smpr()
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.modify(|reg| reg.set_smp1(sample_time.sample_time()));
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}
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#[cfg(not(stm32g0))]
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unsafe fn set_channel_sample_time(ch: u8, sample_time: SampleTime) {
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if ch <= 9 {
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T::regs()
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.smpr1()
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.modify(|reg| reg.set_smp(ch as _, sample_time.sample_time()));
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} else {
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T::regs()
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.smpr2()
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.modify(|reg| reg.set_smp((ch - 10) as _, sample_time.sample_time()));
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}
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}
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}
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