570 lines
17 KiB
Rust
570 lines
17 KiB
Rust
#![macro_use]
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use core::future::poll_fn;
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use core::ptr;
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use core::task::Poll;
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use embassy_hal_common::drop::DropBomb;
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use embassy_hal_common::{into_ref, PeripheralRef};
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use crate::gpio::{self, Pin as GpioPin};
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use crate::interrupt::{Interrupt, InterruptExt};
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pub use crate::pac::qspi::ifconfig0::{
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ADDRMODE_A as AddressMode, PPSIZE_A as WritePageSize, READOC_A as ReadOpcode, WRITEOC_A as WriteOpcode,
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};
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pub use crate::pac::qspi::ifconfig1::SPIMODE_A as SpiMode;
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use crate::{pac, Peripheral};
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pub struct DeepPowerDownConfig {
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/// Time required for entering DPM, in units of 16us
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pub enter_time: u16,
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/// Time required for exiting DPM, in units of 16us
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pub exit_time: u16,
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}
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pub enum Frequency {
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M32 = 0,
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M16 = 1,
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M10_7 = 2,
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M8 = 3,
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M6_4 = 4,
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M5_3 = 5,
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M4_6 = 6,
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M4 = 7,
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M3_6 = 8,
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M3_2 = 9,
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M2_9 = 10,
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M2_7 = 11,
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M2_5 = 12,
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M2_3 = 13,
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M2_1 = 14,
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M2 = 15,
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}
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#[non_exhaustive]
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pub struct Config {
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pub xip_offset: u32,
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pub read_opcode: ReadOpcode,
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pub write_opcode: WriteOpcode,
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pub write_page_size: WritePageSize,
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pub deep_power_down: Option<DeepPowerDownConfig>,
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pub frequency: Frequency,
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/// Value is specified in number of 16 MHz periods (62.5 ns)
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pub sck_delay: u8,
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/// Whether data is captured on the clock rising edge and data is output on a falling edge (MODE0) or vice-versa (MODE3)
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pub spi_mode: SpiMode,
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pub address_mode: AddressMode,
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}
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impl Default for Config {
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fn default() -> Self {
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Self {
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read_opcode: ReadOpcode::READ4IO,
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write_opcode: WriteOpcode::PP4IO,
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xip_offset: 0,
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write_page_size: WritePageSize::_256BYTES,
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deep_power_down: None,
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frequency: Frequency::M8,
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sck_delay: 80,
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spi_mode: SpiMode::MODE0,
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address_mode: AddressMode::_24BIT,
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}
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}
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}
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#[derive(Debug, Copy, Clone, Eq, PartialEq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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#[non_exhaustive]
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pub enum Error {
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OutOfBounds,
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// TODO add "not in data memory" error and check for it
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}
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pub struct Qspi<'d, T: Instance, const FLASH_SIZE: usize> {
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irq: PeripheralRef<'d, T::Interrupt>,
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dpm_enabled: bool,
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}
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impl<'d, T: Instance, const FLASH_SIZE: usize> Qspi<'d, T, FLASH_SIZE> {
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pub fn new(
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_qspi: impl Peripheral<P = T> + 'd,
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irq: impl Peripheral<P = T::Interrupt> + 'd,
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sck: impl Peripheral<P = impl GpioPin> + 'd,
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csn: impl Peripheral<P = impl GpioPin> + 'd,
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io0: impl Peripheral<P = impl GpioPin> + 'd,
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io1: impl Peripheral<P = impl GpioPin> + 'd,
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io2: impl Peripheral<P = impl GpioPin> + 'd,
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io3: impl Peripheral<P = impl GpioPin> + 'd,
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config: Config,
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) -> Qspi<'d, T, FLASH_SIZE> {
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into_ref!(irq, sck, csn, io0, io1, io2, io3);
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let r = T::regs();
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sck.set_high();
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csn.set_high();
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io0.set_high();
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io1.set_high();
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io2.set_high();
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io3.set_high();
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sck.conf().write(|w| w.dir().output().drive().h0h1());
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csn.conf().write(|w| w.dir().output().drive().h0h1());
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io0.conf().write(|w| w.dir().output().drive().h0h1());
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io1.conf().write(|w| w.dir().output().drive().h0h1());
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io2.conf().write(|w| w.dir().output().drive().h0h1());
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io3.conf().write(|w| w.dir().output().drive().h0h1());
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r.psel.sck.write(|w| unsafe { w.bits(sck.psel_bits()) });
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r.psel.csn.write(|w| unsafe { w.bits(csn.psel_bits()) });
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r.psel.io0.write(|w| unsafe { w.bits(io0.psel_bits()) });
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r.psel.io1.write(|w| unsafe { w.bits(io1.psel_bits()) });
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r.psel.io2.write(|w| unsafe { w.bits(io2.psel_bits()) });
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r.psel.io3.write(|w| unsafe { w.bits(io3.psel_bits()) });
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r.ifconfig0.write(|w| {
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w.addrmode().variant(config.address_mode);
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w.dpmenable().bit(config.deep_power_down.is_some());
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w.ppsize().variant(config.write_page_size);
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w.readoc().variant(config.read_opcode);
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w.writeoc().variant(config.write_opcode);
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w
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});
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if let Some(dpd) = &config.deep_power_down {
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r.dpmdur.write(|w| unsafe {
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w.enter().bits(dpd.enter_time);
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w.exit().bits(dpd.exit_time);
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w
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})
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}
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r.ifconfig1.write(|w| unsafe {
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w.sckdelay().bits(config.sck_delay);
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w.dpmen().exit();
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w.spimode().variant(config.spi_mode);
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w.sckfreq().bits(config.frequency as u8);
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w
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});
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r.xipoffset.write(|w| unsafe {
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w.xipoffset().bits(config.xip_offset);
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w
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});
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irq.set_handler(Self::on_interrupt);
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irq.unpend();
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irq.enable();
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// Enable it
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r.enable.write(|w| w.enable().enabled());
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let mut res = Self {
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dpm_enabled: config.deep_power_down.is_some(),
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irq,
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};
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r.events_ready.reset();
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r.intenset.write(|w| w.ready().set());
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r.tasks_activate.write(|w| w.tasks_activate().bit(true));
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res.blocking_wait_ready();
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res
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}
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fn on_interrupt(_: *mut ()) {
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let r = T::regs();
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let s = T::state();
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if r.events_ready.read().bits() != 0 {
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s.ready_waker.wake();
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r.intenclr.write(|w| w.ready().clear());
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}
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}
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pub async fn custom_instruction(&mut self, opcode: u8, req: &[u8], resp: &mut [u8]) -> Result<(), Error> {
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let bomb = DropBomb::new();
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let len = core::cmp::max(req.len(), resp.len()) as u8;
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self.custom_instruction_start(opcode, req, len)?;
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self.wait_ready().await;
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self.custom_instruction_finish(resp)?;
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bomb.defuse();
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Ok(())
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}
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pub fn blocking_custom_instruction(&mut self, opcode: u8, req: &[u8], resp: &mut [u8]) -> Result<(), Error> {
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let len = core::cmp::max(req.len(), resp.len()) as u8;
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self.custom_instruction_start(opcode, req, len)?;
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self.blocking_wait_ready();
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self.custom_instruction_finish(resp)?;
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Ok(())
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}
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fn custom_instruction_start(&mut self, opcode: u8, req: &[u8], len: u8) -> Result<(), Error> {
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assert!(req.len() <= 8);
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let mut dat0: u32 = 0;
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let mut dat1: u32 = 0;
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for i in 0..4 {
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if i < req.len() {
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dat0 |= (req[i] as u32) << (i * 8);
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}
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}
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for i in 0..4 {
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if i + 4 < req.len() {
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dat1 |= (req[i + 4] as u32) << (i * 8);
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}
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}
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let r = T::regs();
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r.cinstrdat0.write(|w| unsafe { w.bits(dat0) });
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r.cinstrdat1.write(|w| unsafe { w.bits(dat1) });
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r.events_ready.reset();
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r.intenset.write(|w| w.ready().set());
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r.cinstrconf.write(|w| {
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let w = unsafe { w.opcode().bits(opcode) };
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let w = unsafe { w.length().bits(len + 1) };
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let w = w.lio2().bit(true);
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let w = w.lio3().bit(true);
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let w = w.wipwait().bit(true);
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let w = w.wren().bit(true);
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let w = w.lfen().bit(false);
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let w = w.lfstop().bit(false);
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w
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});
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Ok(())
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}
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fn custom_instruction_finish(&mut self, resp: &mut [u8]) -> Result<(), Error> {
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let r = T::regs();
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let dat0 = r.cinstrdat0.read().bits();
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let dat1 = r.cinstrdat1.read().bits();
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for i in 0..4 {
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if i < resp.len() {
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resp[i] = (dat0 >> (i * 8)) as u8;
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}
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}
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for i in 0..4 {
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if i + 4 < resp.len() {
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resp[i] = (dat1 >> (i * 8)) as u8;
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}
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}
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Ok(())
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}
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async fn wait_ready(&mut self) {
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poll_fn(move |cx| {
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let r = T::regs();
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let s = T::state();
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s.ready_waker.register(cx.waker());
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if r.events_ready.read().bits() != 0 {
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return Poll::Ready(());
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}
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Poll::Pending
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})
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.await
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}
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fn blocking_wait_ready(&mut self) {
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loop {
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let r = T::regs();
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if r.events_ready.read().bits() != 0 {
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break;
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}
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}
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}
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fn start_read(&mut self, address: usize, data: &mut [u8]) -> Result<(), Error> {
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assert_eq!(data.as_ptr() as u32 % 4, 0);
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assert_eq!(data.len() as u32 % 4, 0);
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assert_eq!(address as u32 % 4, 0);
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if address > FLASH_SIZE {
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return Err(Error::OutOfBounds);
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}
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let r = T::regs();
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r.read.src.write(|w| unsafe { w.src().bits(address as u32) });
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r.read.dst.write(|w| unsafe { w.dst().bits(data.as_ptr() as u32) });
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r.read.cnt.write(|w| unsafe { w.cnt().bits(data.len() as u32) });
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r.events_ready.reset();
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r.intenset.write(|w| w.ready().set());
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r.tasks_readstart.write(|w| w.tasks_readstart().bit(true));
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Ok(())
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}
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fn start_write(&mut self, address: usize, data: &[u8]) -> Result<(), Error> {
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assert_eq!(data.as_ptr() as u32 % 4, 0);
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assert_eq!(data.len() as u32 % 4, 0);
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assert_eq!(address as u32 % 4, 0);
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if address > FLASH_SIZE {
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return Err(Error::OutOfBounds);
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}
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let r = T::regs();
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r.write.src.write(|w| unsafe { w.src().bits(data.as_ptr() as u32) });
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r.write.dst.write(|w| unsafe { w.dst().bits(address as u32) });
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r.write.cnt.write(|w| unsafe { w.cnt().bits(data.len() as u32) });
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r.events_ready.reset();
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r.intenset.write(|w| w.ready().set());
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r.tasks_writestart.write(|w| w.tasks_writestart().bit(true));
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Ok(())
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}
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fn start_erase(&mut self, address: usize) -> Result<(), Error> {
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assert_eq!(address as u32 % 4096, 0);
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if address > FLASH_SIZE {
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return Err(Error::OutOfBounds);
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}
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let r = T::regs();
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r.erase.ptr.write(|w| unsafe { w.ptr().bits(address as u32) });
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r.erase.len.write(|w| w.len()._4kb());
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r.events_ready.reset();
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r.intenset.write(|w| w.ready().set());
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r.tasks_erasestart.write(|w| w.tasks_erasestart().bit(true));
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Ok(())
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}
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pub async fn read(&mut self, address: usize, data: &mut [u8]) -> Result<(), Error> {
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let bomb = DropBomb::new();
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self.start_read(address, data)?;
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self.wait_ready().await;
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bomb.defuse();
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Ok(())
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}
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pub async fn write(&mut self, address: usize, data: &[u8]) -> Result<(), Error> {
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let bomb = DropBomb::new();
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self.start_write(address, data)?;
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self.wait_ready().await;
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bomb.defuse();
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Ok(())
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}
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pub async fn erase(&mut self, address: usize) -> Result<(), Error> {
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let bomb = DropBomb::new();
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self.start_erase(address)?;
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self.wait_ready().await;
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bomb.defuse();
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Ok(())
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}
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pub fn blocking_read(&mut self, address: usize, data: &mut [u8]) -> Result<(), Error> {
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self.start_read(address, data)?;
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self.blocking_wait_ready();
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Ok(())
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}
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pub fn blocking_write(&mut self, address: usize, data: &[u8]) -> Result<(), Error> {
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self.start_write(address, data)?;
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self.blocking_wait_ready();
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Ok(())
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}
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pub fn blocking_erase(&mut self, address: usize) -> Result<(), Error> {
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self.start_erase(address)?;
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self.blocking_wait_ready();
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Ok(())
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}
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}
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impl<'d, T: Instance, const FLASH_SIZE: usize> Drop for Qspi<'d, T, FLASH_SIZE> {
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fn drop(&mut self) {
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let r = T::regs();
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if self.dpm_enabled {
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trace!("qspi: doing deep powerdown...");
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r.ifconfig1.modify(|_, w| w.dpmen().enter());
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// Wait for DPM enter.
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// Unfortunately we must spin. There's no way to do this interrupt-driven.
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// The READY event does NOT fire on DPM enter (but it does fire on DPM exit :shrug:)
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while r.status.read().dpm().is_disabled() {}
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// Wait MORE for DPM enter.
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// I have absolutely no idea why, but the wait above is not enough :'(
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// Tested with mx25r64 in nrf52840-dk, and with mx25r16 in custom board
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cortex_m::asm::delay(4096);
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}
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// it seems events_ready is not generated in response to deactivate. nrfx doesn't wait for it.
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r.tasks_deactivate.write(|w| w.tasks_deactivate().set_bit());
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// Workaround https://infocenter.nordicsemi.com/topic/errata_nRF52840_Rev1/ERR/nRF52840/Rev1/latest/anomaly_840_122.html?cp=4_0_1_2_1_7
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// Note that the doc has 2 register writes, but the first one is really the write to tasks_deactivate,
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// so we only do the second one here.
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unsafe { ptr::write_volatile(0x40029054 as *mut u32, 1) }
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r.enable.write(|w| w.enable().disabled());
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self.irq.disable();
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// Note: we do NOT deconfigure CSN here. If DPM is in use and we disconnect CSN,
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// leaving it floating, the flash chip might read it as zero which would cause it to
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// spuriously exit DPM.
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gpio::deconfigure_pin(r.psel.sck.read().bits());
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gpio::deconfigure_pin(r.psel.io0.read().bits());
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gpio::deconfigure_pin(r.psel.io1.read().bits());
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gpio::deconfigure_pin(r.psel.io2.read().bits());
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gpio::deconfigure_pin(r.psel.io3.read().bits());
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trace!("qspi: dropped");
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}
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}
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use embedded_storage::nor_flash::{ErrorType, NorFlash, NorFlashError, NorFlashErrorKind, ReadNorFlash};
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impl<'d, T: Instance, const FLASH_SIZE: usize> ErrorType for Qspi<'d, T, FLASH_SIZE> {
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type Error = Error;
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}
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impl NorFlashError for Error {
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fn kind(&self) -> NorFlashErrorKind {
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NorFlashErrorKind::Other
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}
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}
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impl<'d, T: Instance, const FLASH_SIZE: usize> ReadNorFlash for Qspi<'d, T, FLASH_SIZE> {
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const READ_SIZE: usize = 4;
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fn read(&mut self, offset: u32, bytes: &mut [u8]) -> Result<(), Self::Error> {
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self.blocking_read(offset as usize, bytes)?;
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Ok(())
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}
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fn capacity(&self) -> usize {
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FLASH_SIZE
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}
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}
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impl<'d, T: Instance, const FLASH_SIZE: usize> NorFlash for Qspi<'d, T, FLASH_SIZE> {
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const WRITE_SIZE: usize = 4;
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const ERASE_SIZE: usize = 4096;
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fn erase(&mut self, from: u32, to: u32) -> Result<(), Self::Error> {
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for address in (from as usize..to as usize).step_by(<Self as NorFlash>::ERASE_SIZE) {
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self.blocking_erase(address)?;
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}
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Ok(())
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}
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fn write(&mut self, offset: u32, bytes: &[u8]) -> Result<(), Self::Error> {
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self.blocking_write(offset as usize, bytes)?;
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Ok(())
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}
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}
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cfg_if::cfg_if! {
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if #[cfg(feature = "nightly")]
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{
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use embedded_storage_async::nor_flash::{AsyncNorFlash, AsyncReadNorFlash};
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use core::future::Future;
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impl<'d, T: Instance, const FLASH_SIZE: usize> AsyncNorFlash for Qspi<'d, T, FLASH_SIZE> {
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const WRITE_SIZE: usize = <Self as NorFlash>::WRITE_SIZE;
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const ERASE_SIZE: usize = <Self as NorFlash>::ERASE_SIZE;
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type WriteFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a;
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fn write<'a>(&'a mut self, offset: u32, data: &'a [u8]) -> Self::WriteFuture<'a> {
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async move { self.write(offset as usize, data).await }
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}
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type EraseFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a;
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fn erase<'a>(&'a mut self, from: u32, to: u32) -> Self::EraseFuture<'a> {
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async move {
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for address in (from as usize..to as usize).step_by(<Self as AsyncNorFlash>::ERASE_SIZE) {
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self.erase(address).await?
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}
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Ok(())
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}
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}
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}
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impl<'d, T: Instance, const FLASH_SIZE: usize> AsyncReadNorFlash for Qspi<'d, T, FLASH_SIZE> {
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const READ_SIZE: usize = 4;
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type ReadFuture<'a> = impl Future<Output = Result<(), Self::Error>> + 'a where Self: 'a;
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fn read<'a>(&'a mut self, address: u32, data: &'a mut [u8]) -> Self::ReadFuture<'a> {
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async move { self.read(address as usize, data).await }
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}
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fn capacity(&self) -> usize {
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FLASH_SIZE
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}
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}
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}
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}
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pub(crate) mod sealed {
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use embassy_sync::waitqueue::AtomicWaker;
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use super::*;
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pub struct State {
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pub ready_waker: AtomicWaker,
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}
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impl State {
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pub const fn new() -> Self {
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Self {
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ready_waker: AtomicWaker::new(),
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}
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}
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}
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pub trait Instance {
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fn regs() -> &'static pac::qspi::RegisterBlock;
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fn state() -> &'static State;
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}
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}
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pub trait Instance: Peripheral<P = Self> + sealed::Instance + 'static {
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type Interrupt: Interrupt;
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}
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macro_rules! impl_qspi {
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($type:ident, $pac_type:ident, $irq:ident) => {
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impl crate::qspi::sealed::Instance for peripherals::$type {
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fn regs() -> &'static pac::qspi::RegisterBlock {
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unsafe { &*pac::$pac_type::ptr() }
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}
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fn state() -> &'static crate::qspi::sealed::State {
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static STATE: crate::qspi::sealed::State = crate::qspi::sealed::State::new();
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&STATE
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}
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}
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impl crate::qspi::Instance for peripherals::$type {
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type Interrupt = crate::interrupt::$irq;
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}
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};
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}
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