305 lines
9.1 KiB
Rust
305 lines
9.1 KiB
Rust
//! Multicore support
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//!
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//! This module handles setup of the 2nd cpu core on the rp2040, which we refer to as core1.
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//! It provides functionality for setting up the stack, and starting core1.
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//!
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//! The entrypoint for core1 can be any function that never returns, including closures.
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//!
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//! Enable the `critical-section-impl` feature in embassy-rp when sharing data across cores using
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//! the `embassy-sync` primitives and `CriticalSectionRawMutex`.
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//!
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//! # Usage
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//! ```no_run
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//! static mut CORE1_STACK: Stack<4096> = Stack::new();
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//! static EXECUTOR0: StaticCell<Executor> = StaticCell::new();
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//! static EXECUTOR1: StaticCell<Executor> = StaticCell::new();
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//!
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//! #[cortex_m_rt::entry]
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//! fn main() -> ! {
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//! let p = embassy_rp::init(Default::default());
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//!
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//! spawn_core1(p.CORE1, unsafe { &mut CORE1_STACK }, move || {
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//! let executor1 = EXECUTOR1.init(Executor::new());
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//! executor1.run(|spawner| unwrap!(spawner.spawn(core1_task())));
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//! });
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//!
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//! let executor0 = EXECUTOR0.init(Executor::new());
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//! executor0.run(|spawner| unwrap!(spawner.spawn(core0_task())));
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//! }
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//! ```
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use core::mem::ManuallyDrop;
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use core::sync::atomic::{compiler_fence, AtomicBool, Ordering};
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use crate::interrupt::{Interrupt, InterruptExt};
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use crate::peripherals::CORE1;
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use crate::{interrupt, pac};
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const PAUSE_TOKEN: u32 = 0xDEADBEEF;
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const RESUME_TOKEN: u32 = !0xDEADBEEF;
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static IS_CORE1_INIT: AtomicBool = AtomicBool::new(false);
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#[inline(always)]
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fn install_stack_guard(stack_bottom: *mut usize) {
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let core = unsafe { cortex_m::Peripherals::steal() };
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// Trap if MPU is already configured
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if core.MPU.ctrl.read() != 0 {
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cortex_m::asm::udf();
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}
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// The minimum we can protect is 32 bytes on a 32 byte boundary, so round up which will
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// just shorten the valid stack range a tad.
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let addr = (stack_bottom as u32 + 31) & !31;
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// Mask is 1 bit per 32 bytes of the 256 byte range... clear the bit for the segment we want
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let subregion_select = 0xff ^ (1 << ((addr >> 5) & 7));
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unsafe {
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core.MPU.ctrl.write(5); // enable mpu with background default map
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core.MPU.rbar.write((addr & !0xff) | 0x8);
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core.MPU.rasr.write(
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1 // enable region
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| (0x7 << 1) // size 2^(7 + 1) = 256
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| (subregion_select << 8)
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| 0x10000000, // XN = disable instruction fetch; no other bits means no permissions
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);
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}
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}
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#[inline(always)]
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fn core1_setup(stack_bottom: *mut usize) {
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install_stack_guard(stack_bottom);
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}
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/// Data type for a properly aligned stack of N bytes
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#[repr(C, align(32))]
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pub struct Stack<const SIZE: usize> {
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/// Memory to be used for the stack
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pub mem: [u8; SIZE],
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}
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impl<const SIZE: usize> Stack<SIZE> {
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/// Construct a stack of length SIZE, initialized to 0
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pub const fn new() -> Stack<SIZE> {
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Stack { mem: [0_u8; SIZE] }
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}
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}
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#[interrupt]
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#[link_section = ".data.ram_func"]
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unsafe fn SIO_IRQ_PROC1() {
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let sio = pac::SIO;
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// Clear IRQ
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sio.fifo().st().write(|w| w.set_wof(false));
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while sio.fifo().st().read().vld() {
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// Pause CORE1 execution and disable interrupts
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if fifo_read_wfe() == PAUSE_TOKEN {
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cortex_m::interrupt::disable();
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// Signal to CORE0 that execution is paused
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fifo_write(PAUSE_TOKEN);
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// Wait for `resume` signal from CORE0
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while fifo_read_wfe() != RESUME_TOKEN {
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cortex_m::asm::nop();
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}
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cortex_m::interrupt::enable();
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// Signal to CORE0 that execution is resumed
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fifo_write(RESUME_TOKEN);
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}
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}
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}
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/// Spawn a function on this core
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pub fn spawn_core1<F, const SIZE: usize>(_core1: CORE1, stack: &'static mut Stack<SIZE>, entry: F)
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where
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F: FnOnce() -> bad::Never + Send + 'static,
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{
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// The first two ignored `u64` parameters are there to take up all of the registers,
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// which means that the rest of the arguments are taken from the stack,
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// where we're able to put them from core 0.
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extern "C" fn core1_startup<F: FnOnce() -> bad::Never>(
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_: u64,
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_: u64,
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entry: &mut ManuallyDrop<F>,
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stack_bottom: *mut usize,
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) -> ! {
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core1_setup(stack_bottom);
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let entry = unsafe { ManuallyDrop::take(entry) };
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// Signal that it's safe for core 0 to get rid of the original value now.
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fifo_write(1);
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IS_CORE1_INIT.store(true, Ordering::Release);
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// Enable fifo interrupt on CORE1 for `pause` functionality.
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let irq = unsafe { interrupt::SIO_IRQ_PROC1::steal() };
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irq.enable();
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entry()
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}
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// Reset the core
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unsafe {
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let psm = pac::PSM;
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psm.frce_off().modify(|w| w.set_proc1(true));
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while !psm.frce_off().read().proc1() {
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cortex_m::asm::nop();
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}
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psm.frce_off().modify(|w| w.set_proc1(false));
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}
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let mem = unsafe { core::slice::from_raw_parts_mut(stack.mem.as_mut_ptr() as *mut usize, stack.mem.len() / 4) };
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// Set up the stack
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let mut stack_ptr = unsafe { mem.as_mut_ptr().add(mem.len()) };
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// We don't want to drop this, since it's getting moved to the other core.
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let mut entry = ManuallyDrop::new(entry);
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// Push the arguments to `core1_startup` onto the stack.
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unsafe {
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// Push `stack_bottom`.
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stack_ptr = stack_ptr.sub(1);
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stack_ptr.cast::<*mut usize>().write(mem.as_mut_ptr());
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// Push `entry`.
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stack_ptr = stack_ptr.sub(1);
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stack_ptr.cast::<&mut ManuallyDrop<F>>().write(&mut entry);
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}
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// Make sure the compiler does not reorder the stack writes after to after the
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// below FIFO writes, which would result in them not being seen by the second
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// core.
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//
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// From the compiler perspective, this doesn't guarantee that the second core
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// actually sees those writes. However, we know that the RP2040 doesn't have
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// memory caches, and writes happen in-order.
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compiler_fence(Ordering::Release);
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let p = unsafe { cortex_m::Peripherals::steal() };
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let vector_table = p.SCB.vtor.read();
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// After reset, core 1 is waiting to receive commands over FIFO.
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// This is the sequence to have it jump to some code.
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let cmd_seq = [
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0,
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0,
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1,
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vector_table as usize,
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stack_ptr as usize,
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core1_startup::<F> as usize,
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];
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let mut seq = 0;
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let mut fails = 0;
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loop {
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let cmd = cmd_seq[seq] as u32;
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if cmd == 0 {
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fifo_drain();
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cortex_m::asm::sev();
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}
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fifo_write(cmd);
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let response = fifo_read();
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if cmd == response {
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seq += 1;
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} else {
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seq = 0;
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fails += 1;
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if fails > 16 {
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// The second core isn't responding, and isn't going to take the entrypoint
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panic!("CORE1 not responding");
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}
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}
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if seq >= cmd_seq.len() {
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break;
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}
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}
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// Wait until the other core has copied `entry` before returning.
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fifo_read();
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}
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/// Pause execution on CORE1.
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pub fn pause_core1() {
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if IS_CORE1_INIT.load(Ordering::Acquire) {
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fifo_write(PAUSE_TOKEN);
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// Wait for CORE1 to signal it has paused execution.
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while fifo_read() != PAUSE_TOKEN {}
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}
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}
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/// Resume CORE1 execution.
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pub fn resume_core1() {
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if IS_CORE1_INIT.load(Ordering::Acquire) {
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fifo_write(RESUME_TOKEN);
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// Wait for CORE1 to signal it has resumed execution.
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while fifo_read() != RESUME_TOKEN {}
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}
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}
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// Push a value to the inter-core FIFO, block until space is available
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#[inline(always)]
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fn fifo_write(value: u32) {
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unsafe {
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let sio = pac::SIO;
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// Wait for the FIFO to have enough space
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while !sio.fifo().st().read().rdy() {
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cortex_m::asm::nop();
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}
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sio.fifo().wr().write_value(value);
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}
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// Fire off an event to the other core.
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// This is required as the other core may be `wfe` (waiting for event)
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cortex_m::asm::sev();
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}
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// Pop a value from inter-core FIFO, block until available
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#[inline(always)]
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fn fifo_read() -> u32 {
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unsafe {
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let sio = pac::SIO;
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// Wait until FIFO has data
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while !sio.fifo().st().read().vld() {
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cortex_m::asm::nop();
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}
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sio.fifo().rd().read()
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}
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}
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// Pop a value from inter-core FIFO, `wfe` until available
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#[inline(always)]
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fn fifo_read_wfe() -> u32 {
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unsafe {
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let sio = pac::SIO;
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// Wait until FIFO has data
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while !sio.fifo().st().read().vld() {
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cortex_m::asm::wfe();
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}
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sio.fifo().rd().read()
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}
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}
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// Drain inter-core FIFO
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#[inline(always)]
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fn fifo_drain() {
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unsafe {
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let sio = pac::SIO;
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while sio.fifo().st().read().vld() {
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let _ = sio.fifo().rd().read();
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}
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}
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}
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// https://github.com/nvzqz/bad-rs/blob/master/src/never.rs
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mod bad {
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pub(crate) type Never = <F as HasOutput>::Output;
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pub trait HasOutput {
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type Output;
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}
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impl<O> HasOutput for fn() -> O {
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type Output = O;
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}
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type F = fn() -> !;
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}
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