444 lines
12 KiB
Rust
444 lines
12 KiB
Rust
use stm32_metapac::PWR;
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pub use super::bus::{AHBPrescaler, APBPrescaler};
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use crate::pac::rcc::vals::{Hpre, Msirange, Pllsrc, Ppre, Sw};
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use crate::pac::{FLASH, RCC};
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use crate::rcc::{set_freqs, Clocks};
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use crate::time::Hertz;
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/// HSI speed
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pub const HSI_FREQ: Hertz = Hertz(16_000_000);
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/// LSI speed
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pub const LSI_FREQ: Hertz = Hertz(32_000);
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/// System clock mux source
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#[derive(Clone, Copy)]
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pub enum ClockSrc {
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MSI(MSIRange),
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PLL(PLLSource, PLLClkDiv, PLLSrcDiv, PLLMul, Option<PLL48Div>),
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HSE(Hertz),
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HSI16,
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}
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/// MSI Clock Range
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///
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/// These ranges control the frequency of the MSI. Internally, these ranges map
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/// to the `MSIRANGE` bits in the `RCC_ICSCR` register.
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#[derive(Clone, Copy)]
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pub enum MSIRange {
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/// Around 100 kHz
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Range0,
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/// Around 200 kHz
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Range1,
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/// Around 400 kHz
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Range2,
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/// Around 800 kHz
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Range3,
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/// Around 1 MHz
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Range4,
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/// Around 2 MHz
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Range5,
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/// Around 4 MHz (reset value)
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Range6,
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/// Around 8 MHz
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Range7,
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/// Around 16 MHz
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Range8,
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/// Around 24 MHz
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Range9,
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/// Around 32 MHz
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Range10,
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/// Around 48 MHz
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Range11,
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}
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impl Default for MSIRange {
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fn default() -> MSIRange {
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MSIRange::Range6
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}
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}
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pub type PLL48Div = PLLClkDiv;
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pub type PLLSAI1RDiv = PLLClkDiv;
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pub type PLLSAI1QDiv = PLLClkDiv;
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pub type PLLSAI1PDiv = PLLClkDiv;
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/// PLL divider
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#[derive(Clone, Copy)]
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pub enum PLLDiv {
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Div2,
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Div3,
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Div4,
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}
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/// PLL clock input source
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#[derive(Clone, Copy)]
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pub enum PLLSource {
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HSI16,
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HSE(Hertz),
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MSI(MSIRange),
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}
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seq_macro::seq!(N in 8..=86 {
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#[derive(Clone, Copy)]
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pub enum PLLMul {
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#(
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Mul~N,
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)*
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}
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impl From<PLLMul> for u8 {
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fn from(val: PLLMul) -> u8 {
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match val {
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#(
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PLLMul::Mul~N => N,
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)*
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}
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}
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}
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impl PLLMul {
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pub fn to_mul(self) -> u32 {
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match self {
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#(
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PLLMul::Mul~N => N,
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)*
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}
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}
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}
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});
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#[derive(Clone, Copy)]
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pub enum PLLClkDiv {
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Div2,
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Div4,
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Div6,
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Div8,
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}
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impl PLLClkDiv {
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pub fn to_div(self) -> u32 {
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let val: u8 = self.into();
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(val as u32 + 1) * 2
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}
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}
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impl From<PLLClkDiv> for u8 {
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fn from(val: PLLClkDiv) -> u8 {
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match val {
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PLLClkDiv::Div2 => 0b00,
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PLLClkDiv::Div4 => 0b01,
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PLLClkDiv::Div6 => 0b10,
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PLLClkDiv::Div8 => 0b11,
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}
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}
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}
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#[derive(Clone, Copy)]
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pub enum PLLSrcDiv {
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Div1,
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Div2,
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Div3,
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Div4,
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Div5,
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Div6,
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Div7,
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Div8,
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}
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impl PLLSrcDiv {
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pub fn to_div(self) -> u32 {
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let val: u8 = self.into();
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val as u32 + 1
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}
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}
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impl From<PLLSrcDiv> for u8 {
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fn from(val: PLLSrcDiv) -> u8 {
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match val {
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PLLSrcDiv::Div1 => 0b000,
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PLLSrcDiv::Div2 => 0b001,
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PLLSrcDiv::Div3 => 0b010,
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PLLSrcDiv::Div4 => 0b011,
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PLLSrcDiv::Div5 => 0b100,
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PLLSrcDiv::Div6 => 0b101,
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PLLSrcDiv::Div7 => 0b110,
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PLLSrcDiv::Div8 => 0b111,
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}
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}
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}
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impl From<PLLSource> for Pllsrc {
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fn from(val: PLLSource) -> Pllsrc {
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match val {
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PLLSource::HSI16 => Pllsrc::HSI16,
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PLLSource::HSE(_) => Pllsrc::HSE,
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PLLSource::MSI(_) => Pllsrc::MSI,
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}
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}
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}
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impl From<MSIRange> for Msirange {
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fn from(val: MSIRange) -> Msirange {
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match val {
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MSIRange::Range0 => Msirange::RANGE100K,
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MSIRange::Range1 => Msirange::RANGE200K,
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MSIRange::Range2 => Msirange::RANGE400K,
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MSIRange::Range3 => Msirange::RANGE800K,
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MSIRange::Range4 => Msirange::RANGE1M,
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MSIRange::Range5 => Msirange::RANGE2M,
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MSIRange::Range6 => Msirange::RANGE4M,
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MSIRange::Range7 => Msirange::RANGE8M,
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MSIRange::Range8 => Msirange::RANGE16M,
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MSIRange::Range9 => Msirange::RANGE24M,
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MSIRange::Range10 => Msirange::RANGE32M,
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MSIRange::Range11 => Msirange::RANGE48M,
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}
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}
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}
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impl From<MSIRange> for u32 {
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fn from(val: MSIRange) -> u32 {
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match val {
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MSIRange::Range0 => 100_000,
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MSIRange::Range1 => 200_000,
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MSIRange::Range2 => 400_000,
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MSIRange::Range3 => 800_000,
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MSIRange::Range4 => 1_000_000,
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MSIRange::Range5 => 2_000_000,
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MSIRange::Range6 => 4_000_000,
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MSIRange::Range7 => 8_000_000,
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MSIRange::Range8 => 16_000_000,
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MSIRange::Range9 => 24_000_000,
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MSIRange::Range10 => 32_000_000,
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MSIRange::Range11 => 48_000_000,
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}
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}
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}
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/// Clocks configutation
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pub struct Config {
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pub mux: ClockSrc,
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pub ahb_pre: AHBPrescaler,
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pub apb1_pre: APBPrescaler,
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pub apb2_pre: APBPrescaler,
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pub pllsai1: Option<(
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PLLMul,
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PLLSrcDiv,
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Option<PLLSAI1RDiv>,
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Option<PLLSAI1QDiv>,
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Option<PLLSAI1PDiv>,
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)>,
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pub hsi48: bool,
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}
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impl Default for Config {
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#[inline]
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fn default() -> Config {
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Config {
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mux: ClockSrc::MSI(MSIRange::Range6),
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ahb_pre: AHBPrescaler::DIV1,
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apb1_pre: APBPrescaler::DIV1,
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apb2_pre: APBPrescaler::DIV1,
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pllsai1: None,
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hsi48: false,
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}
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}
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}
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pub(crate) unsafe fn init(config: Config) {
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PWR.cr1().modify(|w| w.set_vos(stm32_metapac::pwr::vals::Vos::RANGE0));
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let (sys_clk, sw) = match config.mux {
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ClockSrc::MSI(range) => {
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// Enable MSI
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RCC.cr().write(|w| {
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let bits: Msirange = range.into();
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w.set_msirange(bits);
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w.set_msipllen(false);
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w.set_msirgsel(true);
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w.set_msion(true);
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});
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while !RCC.cr().read().msirdy() {}
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// Enable as clock source for USB, RNG if running at 48 MHz
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if let MSIRange::Range11 = range {
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RCC.ccipr1().modify(|w| {
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w.set_clk48msel(0b11);
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});
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}
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(range.into(), Sw::MSI)
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}
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ClockSrc::HSI16 => {
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// Enable HSI16
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RCC.cr().write(|w| w.set_hsion(true));
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while !RCC.cr().read().hsirdy() {}
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(HSI_FREQ.0, Sw::HSI16)
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}
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ClockSrc::HSE(freq) => {
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// Enable HSE
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RCC.cr().write(|w| w.set_hseon(true));
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while !RCC.cr().read().hserdy() {}
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(freq.0, Sw::HSE)
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}
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ClockSrc::PLL(src, div, prediv, mul, pll48div) => {
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let src_freq = match src {
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PLLSource::HSE(freq) => {
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// Enable HSE
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RCC.cr().write(|w| w.set_hseon(true));
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while !RCC.cr().read().hserdy() {}
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freq.0
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}
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PLLSource::HSI16 => {
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// Enable HSI
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RCC.cr().write(|w| w.set_hsion(true));
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while !RCC.cr().read().hsirdy() {}
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HSI_FREQ.0
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}
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PLLSource::MSI(range) => {
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// Enable MSI
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RCC.cr().write(|w| {
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let bits: Msirange = range.into();
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w.set_msirange(bits);
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w.set_msipllen(false); // should be turned on if LSE is started
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w.set_msirgsel(true);
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w.set_msion(true);
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});
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while !RCC.cr().read().msirdy() {}
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range.into()
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}
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};
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// Disable PLL
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RCC.cr().modify(|w| w.set_pllon(false));
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while RCC.cr().read().pllrdy() {}
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let freq = (src_freq / prediv.to_div() * mul.to_mul()) / div.to_div();
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RCC.pllcfgr().write(move |w| {
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w.set_plln(mul.into());
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w.set_pllm(prediv.into());
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w.set_pllr(div.into());
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if let Some(pll48div) = pll48div {
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w.set_pllq(pll48div.into());
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w.set_pllqen(true);
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}
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w.set_pllsrc(src.into());
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});
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// Enable as clock source for USB, RNG if PLL48 divisor is provided
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if let Some(pll48div) = pll48div {
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let freq = (src_freq / prediv.to_div() * mul.to_mul()) / pll48div.to_div();
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assert!(freq == 48_000_000);
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RCC.ccipr1().modify(|w| {
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w.set_clk48msel(0b10);
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});
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}
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if let Some((mul, prediv, r_div, q_div, p_div)) = config.pllsai1 {
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RCC.pllsai1cfgr().write(move |w| {
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w.set_pllsai1n(mul.into());
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w.set_pllsai1m(prediv.into());
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if let Some(r_div) = r_div {
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w.set_pllsai1r(r_div.into());
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w.set_pllsai1ren(true);
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}
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if let Some(q_div) = q_div {
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w.set_pllsai1q(q_div.into());
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w.set_pllsai1qen(true);
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let freq = (src_freq / prediv.to_div() * mul.to_mul()) / q_div.to_div();
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if freq == 48_000_000 {
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RCC.ccipr1().modify(|w| {
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w.set_clk48msel(0b1);
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});
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}
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}
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if let Some(p_div) = p_div {
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w.set_pllsai1pdiv(p_div.into());
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w.set_pllsai1pen(true);
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}
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});
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RCC.cr().modify(|w| w.set_pllsai1on(true));
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}
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// Enable PLL
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RCC.cr().modify(|w| w.set_pllon(true));
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while !RCC.cr().read().pllrdy() {}
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RCC.pllcfgr().modify(|w| w.set_pllren(true));
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(freq, Sw::PLL)
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}
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};
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if config.hsi48 {
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RCC.crrcr().modify(|w| w.set_hsi48on(true));
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while !RCC.crrcr().read().hsi48rdy() {}
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// Enable as clock source for USB, RNG and SDMMC
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RCC.ccipr1().modify(|w| w.set_clk48msel(0));
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}
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// Set flash wait states
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// VCORE Range 0 (performance), others TODO
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FLASH.acr().modify(|w| {
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w.set_latency(match sys_clk {
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0..=20_000_000 => 0,
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0..=40_000_000 => 1,
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0..=60_000_000 => 2,
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0..=80_000_000 => 3,
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0..=100_000_000 => 4,
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_ => 5,
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})
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});
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RCC.cfgr().modify(|w| {
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w.set_sw(sw);
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w.set_hpre(config.ahb_pre.into());
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w.set_ppre1(config.apb1_pre.into());
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w.set_ppre2(config.apb2_pre.into());
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});
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let ahb_freq: u32 = match config.ahb_pre {
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AHBPrescaler::DIV1 => sys_clk,
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pre => {
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let pre: Hpre = pre.into();
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let pre = 1 << (pre.to_bits() as u32 - 7);
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sys_clk / pre
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}
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};
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let (apb1_freq, apb1_tim_freq) = match config.apb1_pre {
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APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
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pre => {
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let pre: Ppre = pre.into();
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let pre: u8 = 1 << (pre.to_bits() - 3);
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let freq = ahb_freq / pre as u32;
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(freq, freq * 2)
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}
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};
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let (apb2_freq, apb2_tim_freq) = match config.apb2_pre {
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APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
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pre => {
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let pre: Ppre = pre.into();
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let pre: u8 = 1 << (pre.to_bits() - 3);
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let freq = ahb_freq / pre as u32;
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(freq, freq * 2)
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}
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};
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set_freqs(Clocks {
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sys: Hertz(sys_clk),
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ahb1: Hertz(ahb_freq),
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ahb2: Hertz(ahb_freq),
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ahb3: Hertz(ahb_freq),
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apb1: Hertz(apb1_freq),
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apb2: Hertz(apb2_freq),
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apb1_tim: Hertz(apb1_tim_freq),
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apb2_tim: Hertz(apb2_tim_freq),
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});
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}
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