484 lines
19 KiB
Rust
484 lines
19 KiB
Rust
#![macro_use]
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pub use defmt::*;
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#[allow(unused)]
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use embassy_stm32::time::Hertz;
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use embassy_stm32::Config;
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use {defmt_rtt as _, panic_probe as _};
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#[cfg(feature = "stm32f103c8")]
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teleprobe_meta::target!(b"bluepill-stm32f103c8");
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#[cfg(feature = "stm32g491re")]
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teleprobe_meta::target!(b"nucleo-stm32g491re");
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#[cfg(feature = "stm32g071rb")]
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teleprobe_meta::target!(b"nucleo-stm32g071rb");
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#[cfg(feature = "stm32f429zi")]
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teleprobe_meta::target!(b"nucleo-stm32f429zi");
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#[cfg(feature = "stm32wb55rg")]
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teleprobe_meta::target!(b"nucleo-stm32wb55rg");
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#[cfg(feature = "stm32h755zi")]
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teleprobe_meta::target!(b"nucleo-stm32h755zi");
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#[cfg(feature = "stm32h753zi")]
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teleprobe_meta::target!(b"nucleo-stm32h753zi");
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#[cfg(feature = "stm32h7a3zi")]
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teleprobe_meta::target!(b"nucleo-stm32h7a3zi");
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#[cfg(feature = "stm32u585ai")]
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teleprobe_meta::target!(b"iot-stm32u585ai");
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#[cfg(feature = "stm32u5a5zj")]
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teleprobe_meta::target!(b"nucleo-stm32u5a5zj");
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#[cfg(feature = "stm32h563zi")]
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teleprobe_meta::target!(b"nucleo-stm32h563zi");
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#[cfg(feature = "stm32c031c6")]
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teleprobe_meta::target!(b"nucleo-stm32c031c6");
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#[cfg(feature = "stm32l073rz")]
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teleprobe_meta::target!(b"nucleo-stm32l073rz");
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#[cfg(feature = "stm32l152re")]
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teleprobe_meta::target!(b"nucleo-stm32l152re");
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#[cfg(feature = "stm32l4a6zg")]
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teleprobe_meta::target!(b"nucleo-stm32l4a6zg");
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#[cfg(feature = "stm32l4r5zi")]
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teleprobe_meta::target!(b"nucleo-stm32l4r5zi");
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#[cfg(feature = "stm32l552ze")]
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teleprobe_meta::target!(b"nucleo-stm32l552ze");
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#[cfg(feature = "stm32f767zi")]
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teleprobe_meta::target!(b"nucleo-stm32f767zi");
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#[cfg(feature = "stm32f207zg")]
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teleprobe_meta::target!(b"nucleo-stm32f207zg");
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#[cfg(feature = "stm32f303ze")]
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teleprobe_meta::target!(b"nucleo-stm32f303ze");
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#[cfg(feature = "stm32l496zg")]
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teleprobe_meta::target!(b"nucleo-stm32l496zg");
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#[cfg(feature = "stm32wl55jc")]
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teleprobe_meta::target!(b"nucleo-stm32wl55jc");
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#[cfg(feature = "stm32wba52cg")]
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teleprobe_meta::target!(b"nucleo-stm32wba52cg");
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macro_rules! define_peris {
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($($name:ident = $peri:ident,)* $(@irq $irq_name:ident = $irq_code:tt,)*) => {
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#[allow(unused_macros)]
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macro_rules! peri {
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$(
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($p:expr, $name) => {
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$p.$peri
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};
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)*
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}
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#[allow(unused_macros)]
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macro_rules! irqs {
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$(
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($irq_name) => {{
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embassy_stm32::bind_interrupts!(struct Irqs $irq_code);
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Irqs
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}};
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)*
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}
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#[allow(unused)]
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#[allow(non_camel_case_types)]
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pub mod peris {
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$(
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pub type $name = embassy_stm32::peripherals::$peri;
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)*
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}
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};
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}
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#[cfg(feature = "stm32f103c8")]
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define_peris!(
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UART = USART1, UART_TX = PA9, UART_RX = PA10, UART_TX_DMA = DMA1_CH4, UART_RX_DMA = DMA1_CH5,
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SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH3, SPI_RX_DMA = DMA1_CH2,
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@irq UART = {USART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART1>;},
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);
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#[cfg(feature = "stm32g491re")]
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define_peris!(
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UART = USART1, UART_TX = PC4, UART_RX = PC5, UART_TX_DMA = DMA1_CH1, UART_RX_DMA = DMA1_CH2,
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SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH1, SPI_RX_DMA = DMA1_CH2,
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@irq UART = {USART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART1>;},
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);
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#[cfg(feature = "stm32g071rb")]
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define_peris!(
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UART = USART1, UART_TX = PC4, UART_RX = PC5, UART_TX_DMA = DMA1_CH1, UART_RX_DMA = DMA1_CH2,
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SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH1, SPI_RX_DMA = DMA1_CH2,
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@irq UART = {USART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART1>;},
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);
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#[cfg(feature = "stm32f429zi")]
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define_peris!(
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UART = USART6, UART_TX = PG14, UART_RX = PG9, UART_TX_DMA = DMA2_CH6, UART_RX_DMA = DMA2_CH1,
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SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA2_CH3, SPI_RX_DMA = DMA2_CH2,
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@irq UART = {USART6 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART6>;},
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);
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#[cfg(feature = "stm32wb55rg")]
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define_peris!(
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UART = LPUART1, UART_TX = PA2, UART_RX = PA3, UART_TX_DMA = DMA1_CH1, UART_RX_DMA = DMA1_CH2,
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SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH1, SPI_RX_DMA = DMA1_CH2,
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@irq UART = {LPUART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::LPUART1>;},
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);
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#[cfg(any(feature = "stm32h755zi", feature = "stm32h753zi"))]
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define_peris!(
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UART = USART1, UART_TX = PB6, UART_RX = PB7, UART_TX_DMA = DMA1_CH0, UART_RX_DMA = DMA1_CH1,
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SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PB5, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH0, SPI_RX_DMA = DMA1_CH1,
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@irq UART = {USART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART1>;},
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);
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#[cfg(feature = "stm32h7a3zi")]
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define_peris!(
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UART = USART1, UART_TX = PB6, UART_RX = PB7, UART_TX_DMA = DMA1_CH0, UART_RX_DMA = DMA1_CH1,
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SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH0, SPI_RX_DMA = DMA1_CH1,
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@irq UART = {USART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART1>;},
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);
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#[cfg(feature = "stm32u585ai")]
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define_peris!(
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UART = USART3, UART_TX = PD8, UART_RX = PD9, UART_TX_DMA = GPDMA1_CH0, UART_RX_DMA = GPDMA1_CH1,
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SPI = SPI1, SPI_SCK = PE13, SPI_MOSI = PE15, SPI_MISO = PE14, SPI_TX_DMA = GPDMA1_CH0, SPI_RX_DMA = GPDMA1_CH1,
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@irq UART = {USART3 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART3>;},
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);
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#[cfg(feature = "stm32u5a5zj")]
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define_peris!(
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UART = LPUART1, UART_TX = PG7, UART_RX = PG8, UART_TX_DMA = GPDMA1_CH0, UART_RX_DMA = GPDMA1_CH1,
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SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = GPDMA1_CH0, SPI_RX_DMA = GPDMA1_CH1,
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@irq UART = {LPUART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::LPUART1>;},
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);
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#[cfg(feature = "stm32h563zi")]
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define_peris!(
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UART = LPUART1, UART_TX = PB6, UART_RX = PB7, UART_TX_DMA = GPDMA1_CH0, UART_RX_DMA = GPDMA1_CH1,
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SPI = SPI4, SPI_SCK = PE12, SPI_MOSI = PE14, SPI_MISO = PE13, SPI_TX_DMA = GPDMA1_CH0, SPI_RX_DMA = GPDMA1_CH1,
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@irq UART = {LPUART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::LPUART1>;},
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);
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#[cfg(feature = "stm32c031c6")]
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define_peris!(
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UART = USART1, UART_TX = PB6, UART_RX = PB7, UART_TX_DMA = DMA1_CH1, UART_RX_DMA = DMA1_CH2,
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SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH1, SPI_RX_DMA = DMA1_CH2,
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@irq UART = {USART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART1>;},
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);
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#[cfg(feature = "stm32l496zg")]
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define_peris!(
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UART = USART3, UART_TX = PD8, UART_RX = PD9, UART_TX_DMA = DMA1_CH2, UART_RX_DMA = DMA1_CH3,
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SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH3, SPI_RX_DMA = DMA1_CH2,
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@irq UART = {USART3 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART3>;},
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);
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#[cfg(feature = "stm32l4a6zg")]
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define_peris!(
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UART = USART3, UART_TX = PD8, UART_RX = PD9, UART_TX_DMA = DMA1_CH2, UART_RX_DMA = DMA1_CH3,
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SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH3, SPI_RX_DMA = DMA1_CH2,
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@irq UART = {USART3 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART3>;},
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);
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#[cfg(feature = "stm32l4r5zi")]
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define_peris!(
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UART = USART3, UART_TX = PD8, UART_RX = PD9, UART_TX_DMA = DMA1_CH1, UART_RX_DMA = DMA1_CH2,
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SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH1, SPI_RX_DMA = DMA1_CH2,
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@irq UART = {USART3 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART3>;},
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);
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#[cfg(feature = "stm32l073rz")]
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define_peris!(
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UART = USART4, UART_TX = PA0, UART_RX = PA1, UART_TX_DMA = DMA1_CH3, UART_RX_DMA = DMA1_CH2,
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SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH3, SPI_RX_DMA = DMA1_CH2,
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@irq UART = {USART4_5 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART4>;},
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);
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#[cfg(feature = "stm32l152re")]
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define_peris!(
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UART = USART3, UART_TX = PB10, UART_RX = PB11, UART_TX_DMA = DMA1_CH2, UART_RX_DMA = DMA1_CH3,
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SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH3, SPI_RX_DMA = DMA1_CH2,
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@irq UART = {USART3 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART3>;},
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);
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#[cfg(feature = "stm32l552ze")]
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define_peris!(
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UART = USART3, UART_TX = PD8, UART_RX = PD9, UART_TX_DMA = DMA1_CH1, UART_RX_DMA = DMA1_CH2,
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SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH1, SPI_RX_DMA = DMA1_CH2,
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@irq UART = {USART3 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART3>;},
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);
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#[cfg(feature = "stm32f767zi")]
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define_peris!(
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UART = USART6, UART_TX = PG14, UART_RX = PG9, UART_TX_DMA = DMA2_CH6, UART_RX_DMA = DMA2_CH1,
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SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA2_CH3, SPI_RX_DMA = DMA2_CH2,
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@irq UART = {USART6 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART6>;},
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);
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#[cfg(feature = "stm32f207zg")]
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define_peris!(
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UART = USART6, UART_TX = PG14, UART_RX = PG9, UART_TX_DMA = DMA2_CH6, UART_RX_DMA = DMA2_CH1,
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SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA2_CH3, SPI_RX_DMA = DMA2_CH2,
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@irq UART = {USART6 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART6>;},
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);
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#[cfg(feature = "stm32f303ze")]
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define_peris!(
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UART = USART1, UART_TX = PC4, UART_RX = PC5, UART_TX_DMA = DMA1_CH4, UART_RX_DMA = DMA1_CH5,
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SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH3, SPI_RX_DMA = DMA1_CH2,
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@irq UART = {USART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART1>;},
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);
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#[cfg(feature = "stm32wl55jc")]
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define_peris!(
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UART = USART1, UART_TX = PB6, UART_RX = PB7, UART_TX_DMA = DMA1_CH4, UART_RX_DMA = DMA1_CH5,
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SPI = SPI1, SPI_SCK = PA5, SPI_MOSI = PA7, SPI_MISO = PA6, SPI_TX_DMA = DMA1_CH3, SPI_RX_DMA = DMA1_CH2,
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@irq UART = {USART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::USART1>;},
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);
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#[cfg(feature = "stm32wba52cg")]
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define_peris!(
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UART = LPUART1, UART_TX = PB5, UART_RX = PA10, UART_TX_DMA = GPDMA1_CH0, UART_RX_DMA = GPDMA1_CH1,
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SPI = SPI1, SPI_SCK = PB4, SPI_MOSI = PA15, SPI_MISO = PB3, SPI_TX_DMA = GPDMA1_CH0, SPI_RX_DMA = GPDMA1_CH1,
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@irq UART = {LPUART1 => embassy_stm32::usart::InterruptHandler<embassy_stm32::peripherals::LPUART1>;},
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);
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pub fn config() -> Config {
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// Setting this bit is mandatory to use PG[15:2].
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#[cfg(feature = "stm32u5a5zj")]
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embassy_stm32::pac::PWR.svmcr().modify(|w| {
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w.set_io2sv(true);
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w.set_io2vmen(true);
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});
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#[allow(unused_mut)]
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let mut config = Config::default();
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#[cfg(feature = "stm32wb55rg")]
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{
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config.rcc = embassy_stm32::rcc::WPAN_DEFAULT;
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}
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#[cfg(feature = "stm32f207zg")]
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{
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use embassy_stm32::rcc::*;
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// By default, HSE on the board comes from a 8 MHz clock signal (not a crystal)
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config.rcc.hse = Some(HSEConfig {
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frequency: Hertz(8_000_000),
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source: HSESrc::Bypass,
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});
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// PLL uses HSE as the clock source
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config.rcc.pll_mux = PLLSrc::HSE;
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config.rcc.pll = PLLConfig {
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// 8 MHz clock source / 8 = 1 MHz PLL input
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pre_div: unwrap!(PLLPreDiv::try_from(8)),
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// 1 MHz PLL input * 240 = 240 MHz PLL VCO
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mul: unwrap!(PLLMul::try_from(240)),
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// 240 MHz PLL VCO / 2 = 120 MHz main PLL output
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p_div: PLLPDiv::DIV2,
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// 240 MHz PLL VCO / 5 = 48 MHz PLL48 output
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q_div: PLLQDiv::DIV5,
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};
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// System clock comes from PLL (= the 120 MHz main PLL output)
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config.rcc.mux = ClockSrc::PLL;
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// 120 MHz / 4 = 30 MHz APB1 frequency
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config.rcc.apb1_pre = APBPrescaler::DIV4;
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// 120 MHz / 2 = 60 MHz APB2 frequency
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config.rcc.apb2_pre = APBPrescaler::DIV2;
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}
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#[cfg(feature = "stm32f429zi")]
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{
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use embassy_stm32::rcc::*;
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config.rcc.hse = Some(Hse {
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freq: Hertz(8_000_000),
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mode: HseMode::Bypass,
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});
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config.rcc.pll_src = PllSource::HSE;
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config.rcc.pll = Some(Pll {
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prediv: PllPreDiv::DIV4,
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mul: PllMul::MUL180,
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divp: Some(Pllp::DIV2), // 8mhz / 4 * 180 / 2 = 180Mhz.
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divq: None,
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divr: None,
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});
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config.rcc.ahb_pre = AHBPrescaler::DIV1;
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config.rcc.apb1_pre = APBPrescaler::DIV4;
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config.rcc.apb2_pre = APBPrescaler::DIV2;
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config.rcc.sys = Sysclk::PLL1_P;
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}
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#[cfg(feature = "stm32f767zi")]
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{
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use embassy_stm32::rcc::*;
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config.rcc.hse = Some(Hse {
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freq: Hertz(8_000_000),
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mode: HseMode::Bypass,
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});
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config.rcc.pll_src = PllSource::HSE;
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config.rcc.pll = Some(Pll {
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prediv: PllPreDiv::DIV4,
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mul: PllMul::MUL216,
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divp: Some(Pllp::DIV2), // 8mhz / 4 * 216 / 2 = 216Mhz.
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divq: None,
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divr: None,
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});
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config.rcc.ahb_pre = AHBPrescaler::DIV1;
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config.rcc.apb1_pre = APBPrescaler::DIV4;
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config.rcc.apb2_pre = APBPrescaler::DIV2;
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config.rcc.sys = Sysclk::PLL1_P;
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}
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#[cfg(feature = "stm32h563zi")]
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{
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use embassy_stm32::rcc::*;
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config.rcc.hsi = None;
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config.rcc.hsi48 = true; // needed for rng
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config.rcc.hse = Some(Hse {
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freq: Hertz(8_000_000),
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mode: HseMode::BypassDigital,
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});
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config.rcc.pll1 = Some(Pll {
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source: PllSource::HSE,
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prediv: PllPreDiv::DIV2,
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mul: PllMul::MUL125,
|
|
divp: Some(PllDiv::DIV2),
|
|
divq: Some(PllDiv::DIV2),
|
|
divr: None,
|
|
});
|
|
config.rcc.ahb_pre = AHBPrescaler::DIV1;
|
|
config.rcc.apb1_pre = APBPrescaler::DIV1;
|
|
config.rcc.apb2_pre = APBPrescaler::DIV1;
|
|
config.rcc.apb3_pre = APBPrescaler::DIV1;
|
|
config.rcc.sys = Sysclk::PLL1_P;
|
|
config.rcc.voltage_scale = VoltageScale::Scale0;
|
|
}
|
|
|
|
#[cfg(any(feature = "stm32h755zi", feature = "stm32h753zi"))]
|
|
{
|
|
use embassy_stm32::rcc::*;
|
|
config.rcc.hsi = Some(HSIPrescaler::DIV1);
|
|
config.rcc.csi = true;
|
|
config.rcc.hsi48 = true; // needed for RNG
|
|
config.rcc.pll1 = Some(Pll {
|
|
source: PllSource::HSI,
|
|
prediv: PllPreDiv::DIV4,
|
|
mul: PllMul::MUL50,
|
|
divp: Some(PllDiv::DIV2),
|
|
divq: Some(PllDiv::DIV8), // SPI1 cksel defaults to pll1_q
|
|
divr: None,
|
|
});
|
|
config.rcc.pll2 = Some(Pll {
|
|
source: PllSource::HSI,
|
|
prediv: PllPreDiv::DIV4,
|
|
mul: PllMul::MUL50,
|
|
divp: Some(PllDiv::DIV8), // 100mhz
|
|
divq: None,
|
|
divr: None,
|
|
});
|
|
config.rcc.sys = Sysclk::PLL1_P; // 400 Mhz
|
|
config.rcc.ahb_pre = AHBPrescaler::DIV2; // 200 Mhz
|
|
config.rcc.apb1_pre = APBPrescaler::DIV2; // 100 Mhz
|
|
config.rcc.apb2_pre = APBPrescaler::DIV2; // 100 Mhz
|
|
config.rcc.apb3_pre = APBPrescaler::DIV2; // 100 Mhz
|
|
config.rcc.apb4_pre = APBPrescaler::DIV2; // 100 Mhz
|
|
config.rcc.voltage_scale = VoltageScale::Scale1;
|
|
config.rcc.adc_clock_source = AdcClockSource::PLL2_P;
|
|
}
|
|
|
|
#[cfg(any(feature = "stm32h7a3zi"))]
|
|
{
|
|
use embassy_stm32::rcc::*;
|
|
config.rcc.hsi = Some(HSIPrescaler::DIV1);
|
|
config.rcc.csi = true;
|
|
config.rcc.hsi48 = true; // needed for RNG
|
|
config.rcc.pll1 = Some(Pll {
|
|
source: PllSource::HSI,
|
|
prediv: PllPreDiv::DIV4,
|
|
mul: PllMul::MUL35,
|
|
divp: Some(PllDiv::DIV2), // 280 Mhz
|
|
divq: Some(PllDiv::DIV8), // SPI1 cksel defaults to pll1_q
|
|
divr: None,
|
|
});
|
|
config.rcc.pll2 = Some(Pll {
|
|
source: PllSource::HSI,
|
|
prediv: PllPreDiv::DIV4,
|
|
mul: PllMul::MUL35,
|
|
divp: Some(PllDiv::DIV8), // 70 Mhz
|
|
divq: None,
|
|
divr: None,
|
|
});
|
|
config.rcc.sys = Sysclk::PLL1_P; // 280 Mhz
|
|
config.rcc.ahb_pre = AHBPrescaler::DIV1; // 280 Mhz
|
|
config.rcc.apb1_pre = APBPrescaler::DIV2; // 140 Mhz
|
|
config.rcc.apb2_pre = APBPrescaler::DIV2; // 140 Mhz
|
|
config.rcc.apb3_pre = APBPrescaler::DIV2; // 140 Mhz
|
|
config.rcc.apb4_pre = APBPrescaler::DIV2; // 140 Mhz
|
|
config.rcc.voltage_scale = VoltageScale::Scale0;
|
|
config.rcc.adc_clock_source = AdcClockSource::PLL2_P;
|
|
}
|
|
|
|
#[cfg(any(feature = "stm32l496zg", feature = "stm32l4a6zg", feature = "stm32l4r5zi"))]
|
|
{
|
|
use embassy_stm32::rcc::*;
|
|
config.rcc.mux = ClockSrc::PLL1_R;
|
|
config.rcc.hsi = true;
|
|
config.rcc.pll = Some(Pll {
|
|
source: PLLSource::HSI,
|
|
prediv: PllPreDiv::DIV1,
|
|
mul: PllMul::MUL18,
|
|
divp: None,
|
|
divq: Some(PllQDiv::DIV6), // 48Mhz (16 / 1 * 18 / 6)
|
|
divr: Some(PllRDiv::DIV4), // sysclk 72Mhz clock (16 / 1 * 18 / 4)
|
|
});
|
|
}
|
|
|
|
#[cfg(feature = "stm32wl55jc")]
|
|
{
|
|
use embassy_stm32::rcc::*;
|
|
config.rcc.hse = Some(Hse {
|
|
freq: Hertz(32_000_000),
|
|
mode: HseMode::Bypass,
|
|
prescaler: HsePrescaler::DIV1,
|
|
});
|
|
config.rcc.mux = ClockSrc::PLL1_R;
|
|
config.rcc.pll = Some(Pll {
|
|
source: PLLSource::HSE,
|
|
prediv: PllPreDiv::DIV2,
|
|
mul: PllMul::MUL6,
|
|
divp: None,
|
|
divq: Some(PllQDiv::DIV2), // PLL1_Q clock (32 / 2 * 6 / 2), used for RNG
|
|
divr: Some(PllRDiv::DIV2), // sysclk 48Mhz clock (32 / 2 * 6 / 2)
|
|
});
|
|
}
|
|
|
|
#[cfg(any(feature = "stm32l552ze"))]
|
|
{
|
|
use embassy_stm32::rcc::*;
|
|
config.rcc.hsi = true;
|
|
config.rcc.mux = ClockSrc::PLL1_R;
|
|
config.rcc.pll = Some(Pll {
|
|
// 110Mhz clock (16 / 4 * 55 / 2)
|
|
source: PLLSource::HSI,
|
|
prediv: PllPreDiv::DIV4,
|
|
mul: PllMul::MUL55,
|
|
divp: None,
|
|
divq: None,
|
|
divr: Some(PllRDiv::DIV2),
|
|
});
|
|
}
|
|
|
|
#[cfg(any(feature = "stm32u585ai", feature = "stm32u5a5zj"))]
|
|
{
|
|
use embassy_stm32::rcc::*;
|
|
config.rcc.mux = ClockSrc::MSI(Msirange::RANGE_48MHZ);
|
|
}
|
|
|
|
#[cfg(feature = "stm32wba52cg")]
|
|
{
|
|
use embassy_stm32::rcc::*;
|
|
config.rcc.mux = ClockSrc::HSI;
|
|
|
|
embassy_stm32::pac::RCC.ccipr2().write(|w| {
|
|
w.set_rngsel(embassy_stm32::pac::rcc::vals::Rngsel::HSI);
|
|
});
|
|
}
|
|
|
|
#[cfg(feature = "stm32l073rz")]
|
|
{
|
|
use embassy_stm32::rcc::*;
|
|
config.rcc.mux = ClockSrc::PLL(
|
|
// 32Mhz clock (16 * 4 / 2)
|
|
PLLSource::HSI,
|
|
PLLMul::MUL4,
|
|
PLLDiv::DIV2,
|
|
);
|
|
}
|
|
|
|
#[cfg(any(feature = "stm32l152re"))]
|
|
{
|
|
use embassy_stm32::rcc::*;
|
|
config.rcc.mux = ClockSrc::PLL(
|
|
// 32Mhz clock (16 * 4 / 2)
|
|
PLLSource::HSI,
|
|
PLLMul::MUL4,
|
|
PLLDiv::DIV2,
|
|
);
|
|
}
|
|
|
|
config
|
|
}
|