b166ed6b78
this lets us treat pins and the temperature sensor uniformly using the same interface. uniformity in turn lets us add more adc features without combinatorial explosion of methods and types needed to handle them all.
368 lines
8.6 KiB
Rust
368 lines
8.6 KiB
Rust
#![no_std]
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#![cfg_attr(feature = "nightly", feature(async_fn_in_trait, impl_trait_projections))]
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// This mod MUST go first, so that the others see its macros.
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pub(crate) mod fmt;
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#[cfg(feature = "critical-section-impl")]
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mod critical_section_impl;
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mod intrinsics;
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pub mod adc;
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pub mod clocks;
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pub mod dma;
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pub mod flash;
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mod float;
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pub mod gpio;
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pub mod i2c;
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pub mod multicore;
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pub mod pwm;
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mod reset;
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pub mod rom_data;
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pub mod rtc;
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pub mod spi;
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#[cfg(feature = "time-driver")]
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pub mod timer;
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pub mod uart;
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#[cfg(feature = "nightly")]
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pub mod usb;
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pub mod watchdog;
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// PIO
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// TODO: move `pio_instr_util` and `relocate` to inside `pio`
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pub mod pio;
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pub mod pio_instr_util;
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pub(crate) mod relocate;
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// Reexports
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pub use embassy_hal_internal::{into_ref, Peripheral, PeripheralRef};
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#[cfg(feature = "unstable-pac")]
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pub use rp_pac as pac;
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#[cfg(not(feature = "unstable-pac"))]
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pub(crate) use rp_pac as pac;
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#[cfg(feature = "rt")]
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pub use crate::pac::NVIC_PRIO_BITS;
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embassy_hal_internal::interrupt_mod!(
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TIMER_IRQ_0,
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TIMER_IRQ_1,
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TIMER_IRQ_2,
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TIMER_IRQ_3,
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PWM_IRQ_WRAP,
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USBCTRL_IRQ,
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XIP_IRQ,
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PIO0_IRQ_0,
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PIO0_IRQ_1,
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PIO1_IRQ_0,
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PIO1_IRQ_1,
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DMA_IRQ_0,
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DMA_IRQ_1,
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IO_IRQ_BANK0,
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IO_IRQ_QSPI,
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SIO_IRQ_PROC0,
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SIO_IRQ_PROC1,
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CLOCKS_IRQ,
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SPI0_IRQ,
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SPI1_IRQ,
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UART0_IRQ,
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UART1_IRQ,
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ADC_IRQ_FIFO,
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I2C0_IRQ,
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I2C1_IRQ,
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RTC_IRQ,
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SWI_IRQ_0,
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SWI_IRQ_1,
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SWI_IRQ_2,
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SWI_IRQ_3,
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SWI_IRQ_4,
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SWI_IRQ_5,
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);
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/// Macro to bind interrupts to handlers.
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///
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/// This defines the right interrupt handlers, and creates a unit struct (like `struct Irqs;`)
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/// and implements the right [`Binding`]s for it. You can pass this struct to drivers to
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/// prove at compile-time that the right interrupts have been bound.
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// developer note: this macro can't be in `embassy-hal-internal` due to the use of `$crate`.
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#[macro_export]
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macro_rules! bind_interrupts {
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($vis:vis struct $name:ident { $($irq:ident => $($handler:ty),*;)* }) => {
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$vis struct $name;
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$(
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#[allow(non_snake_case)]
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#[no_mangle]
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unsafe extern "C" fn $irq() {
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$(
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<$handler as $crate::interrupt::typelevel::Handler<$crate::interrupt::typelevel::$irq>>::on_interrupt();
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)*
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}
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$(
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unsafe impl $crate::interrupt::typelevel::Binding<$crate::interrupt::typelevel::$irq, $handler> for $name {}
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)*
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)*
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};
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}
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embassy_hal_internal::peripherals! {
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PIN_0,
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PIN_1,
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PIN_2,
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PIN_3,
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PIN_4,
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PIN_5,
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PIN_6,
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PIN_7,
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PIN_8,
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PIN_9,
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PIN_10,
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PIN_11,
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PIN_12,
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PIN_13,
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PIN_14,
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PIN_15,
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PIN_16,
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PIN_17,
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PIN_18,
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PIN_19,
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PIN_20,
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PIN_21,
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PIN_22,
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PIN_23,
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PIN_24,
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PIN_25,
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PIN_26,
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PIN_27,
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PIN_28,
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PIN_29,
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PIN_QSPI_SCLK,
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PIN_QSPI_SS,
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PIN_QSPI_SD0,
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PIN_QSPI_SD1,
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PIN_QSPI_SD2,
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PIN_QSPI_SD3,
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UART0,
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UART1,
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SPI0,
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SPI1,
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I2C0,
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I2C1,
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DMA_CH0,
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DMA_CH1,
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DMA_CH2,
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DMA_CH3,
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DMA_CH4,
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DMA_CH5,
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DMA_CH6,
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DMA_CH7,
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DMA_CH8,
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DMA_CH9,
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DMA_CH10,
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DMA_CH11,
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PWM_CH0,
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PWM_CH1,
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PWM_CH2,
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PWM_CH3,
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PWM_CH4,
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PWM_CH5,
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PWM_CH6,
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PWM_CH7,
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USB,
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RTC,
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FLASH,
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ADC,
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ADC_TEMP_SENSOR,
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CORE1,
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PIO0,
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PIO1,
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WATCHDOG,
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}
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macro_rules! select_bootloader {
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( $( $feature:literal => $loader:ident, )+ default => $default:ident ) => {
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$(
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#[cfg(feature = $feature)]
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#[link_section = ".boot2"]
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#[used]
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static BOOT2: [u8; 256] = rp2040_boot2::$loader;
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)*
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#[cfg(not(any( $( feature = $feature),* )))]
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#[link_section = ".boot2"]
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#[used]
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static BOOT2: [u8; 256] = rp2040_boot2::$default;
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}
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}
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select_bootloader! {
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"boot2-at25sf128a" => BOOT_LOADER_AT25SF128A,
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"boot2-gd25q64cs" => BOOT_LOADER_GD25Q64CS,
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"boot2-generic-03h" => BOOT_LOADER_GENERIC_03H,
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"boot2-is25lp080" => BOOT_LOADER_IS25LP080,
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"boot2-ram-memcpy" => BOOT_LOADER_RAM_MEMCPY,
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"boot2-w25q080" => BOOT_LOADER_W25Q080,
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"boot2-w25x10cl" => BOOT_LOADER_W25X10CL,
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default => BOOT_LOADER_W25Q080
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}
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/// Installs a stack guard for the CORE0 stack in MPU region 0.
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/// Will fail if the MPU is already confgigured. This function requires
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/// a `_stack_end` symbol to be defined by the linker script, and expexcts
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/// `_stack_end` to be located at the lowest address (largest depth) of
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/// the stack.
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///
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/// This method can *only* set up stack guards on the currently
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/// executing core. Stack guards for CORE1 are set up automatically,
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/// only CORE0 should ever use this.
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///
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/// # Usage
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///
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/// ```no_run
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/// #![feature(type_alias_impl_trait)]
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/// use embassy_rp::install_core0_stack_guard;
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/// use embassy_executor::{Executor, Spawner};
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///
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/// #[embassy_executor::main]
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/// async fn main(_spawner: Spawner) {
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/// // set up by the linker as follows:
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/// //
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/// // MEMORY {
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/// // STACK0: ORIGIN = 0x20040000, LENGTH = 4K
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/// // }
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/// //
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/// // _stack_end = ORIGIN(STACK0);
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/// // _stack_start = _stack_end + LENGTH(STACK0);
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/// //
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/// install_core0_stack_guard().expect("MPU already configured");
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/// let p = embassy_rp::init(Default::default());
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///
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/// // ...
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/// }
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/// ```
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pub fn install_core0_stack_guard() -> Result<(), ()> {
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extern "C" {
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static mut _stack_end: usize;
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}
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unsafe { install_stack_guard(&mut _stack_end as *mut usize) }
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}
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#[inline(always)]
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fn install_stack_guard(stack_bottom: *mut usize) -> Result<(), ()> {
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let core = unsafe { cortex_m::Peripherals::steal() };
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// Fail if MPU is already configured
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if core.MPU.ctrl.read() != 0 {
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return Err(());
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}
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// The minimum we can protect is 32 bytes on a 32 byte boundary, so round up which will
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// just shorten the valid stack range a tad.
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let addr = (stack_bottom as u32 + 31) & !31;
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// Mask is 1 bit per 32 bytes of the 256 byte range... clear the bit for the segment we want
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let subregion_select = 0xff ^ (1 << ((addr >> 5) & 7));
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unsafe {
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core.MPU.ctrl.write(5); // enable mpu with background default map
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core.MPU.rbar.write((addr & !0xff) | (1 << 4)); // set address and update RNR
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core.MPU.rasr.write(
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1 // enable region
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| (0x7 << 1) // size 2^(7 + 1) = 256
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| (subregion_select << 8)
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| 0x10000000, // XN = disable instruction fetch; no other bits means no permissions
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);
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}
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Ok(())
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}
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pub mod config {
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use crate::clocks::ClockConfig;
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#[non_exhaustive]
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pub struct Config {
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pub clocks: ClockConfig,
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}
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impl Default for Config {
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fn default() -> Self {
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Self {
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clocks: ClockConfig::crystal(12_000_000),
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}
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}
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}
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impl Config {
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pub fn new(clocks: ClockConfig) -> Self {
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Self { clocks }
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}
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}
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}
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pub fn init(config: config::Config) -> Peripherals {
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// Do this first, so that it panics if user is calling `init` a second time
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// before doing anything important.
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let peripherals = Peripherals::take();
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unsafe {
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clocks::init(config.clocks);
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#[cfg(feature = "time-driver")]
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timer::init();
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dma::init();
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gpio::init();
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}
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peripherals
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}
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/// Extension trait for PAC regs, adding atomic xor/bitset/bitclear writes.
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trait RegExt<T: Copy> {
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fn write_xor<R>(&self, f: impl FnOnce(&mut T) -> R) -> R;
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fn write_set<R>(&self, f: impl FnOnce(&mut T) -> R) -> R;
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fn write_clear<R>(&self, f: impl FnOnce(&mut T) -> R) -> R;
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}
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impl<T: Default + Copy, A: pac::common::Write> RegExt<T> for pac::common::Reg<T, A> {
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fn write_xor<R>(&self, f: impl FnOnce(&mut T) -> R) -> R {
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let mut val = Default::default();
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let res = f(&mut val);
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unsafe {
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let ptr = (self.as_ptr() as *mut u8).add(0x1000) as *mut T;
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ptr.write_volatile(val);
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}
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res
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}
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fn write_set<R>(&self, f: impl FnOnce(&mut T) -> R) -> R {
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let mut val = Default::default();
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let res = f(&mut val);
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unsafe {
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let ptr = (self.as_ptr() as *mut u8).add(0x2000) as *mut T;
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ptr.write_volatile(val);
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}
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res
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}
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fn write_clear<R>(&self, f: impl FnOnce(&mut T) -> R) -> R {
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let mut val = Default::default();
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let res = f(&mut val);
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unsafe {
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let ptr = (self.as_ptr() as *mut u8).add(0x3000) as *mut T;
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ptr.write_volatile(val);
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}
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res
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}
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}
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