305 lines
9.4 KiB
Rust
305 lines
9.4 KiB
Rust
use crate::pac::rcc::regs::Cfgr;
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pub use crate::pac::rcc::vals::{
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Hpre as AHBPrescaler, Msirange as MSIRange, Pllm as PllPreDiv, Plln as PllMul, Pllp as PllPDiv, Pllq as PllQDiv,
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Pllr as PllRDiv, Ppre as APBPrescaler,
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};
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use crate::pac::rcc::vals::{Msirange, Pllsrc, Sw};
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use crate::pac::{FLASH, PWR, RCC};
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use crate::rcc::bd::RtcClockSource;
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use crate::rcc::{set_freqs, Clocks};
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use crate::time::Hertz;
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/// HSI speed
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pub const HSI_FREQ: Hertz = Hertz(16_000_000);
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/// LSI speed
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pub const LSI_FREQ: Hertz = Hertz(32_000);
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/// System clock mux source
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#[derive(Clone, Copy)]
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pub enum ClockSrc {
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MSI(MSIRange),
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PLL(PLLSource, PllRDiv, PllPreDiv, PllMul, Option<PllQDiv>),
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HSE(Hertz),
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HSI16,
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}
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/// PLL clock input source
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#[derive(Clone, Copy)]
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pub enum PLLSource {
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HSI16,
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HSE(Hertz),
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MSI(MSIRange),
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}
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impl From<PLLSource> for Pllsrc {
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fn from(val: PLLSource) -> Pllsrc {
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match val {
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PLLSource::HSI16 => Pllsrc::HSI16,
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PLLSource::HSE(_) => Pllsrc::HSE,
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PLLSource::MSI(_) => Pllsrc::MSI,
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}
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}
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}
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/// Clocks configutation
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pub struct Config {
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pub mux: ClockSrc,
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pub ahb_pre: AHBPrescaler,
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pub apb1_pre: APBPrescaler,
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pub apb2_pre: APBPrescaler,
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pub pllsai1: Option<(PllMul, PllPreDiv, Option<PllRDiv>, Option<PllQDiv>, Option<PllPDiv>)>,
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pub hsi48: bool,
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pub rtc_mux: RtcClockSource,
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pub lse: Option<Hertz>,
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pub lsi: bool,
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}
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impl Default for Config {
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#[inline]
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fn default() -> Config {
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Config {
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mux: ClockSrc::MSI(MSIRange::RANGE4M),
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ahb_pre: AHBPrescaler::DIV1,
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apb1_pre: APBPrescaler::DIV1,
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apb2_pre: APBPrescaler::DIV1,
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pllsai1: None,
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hsi48: false,
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rtc_mux: RtcClockSource::LSI,
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lsi: true,
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lse: None,
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}
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}
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}
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pub(crate) unsafe fn init(config: Config) {
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// Switch to MSI to prevent problems with PLL configuration.
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if !RCC.cr().read().msion() {
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// Turn on MSI and configure it to 4MHz.
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RCC.cr().modify(|w| {
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w.set_msirgsel(true); // MSI Range is provided by MSIRANGE[3:0].
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w.set_msirange(MSIRange::RANGE4M);
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w.set_msipllen(false);
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w.set_msion(true)
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});
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// Wait until MSI is running
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while !RCC.cr().read().msirdy() {}
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}
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if RCC.cfgr().read().sws() != Sw::MSI {
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// Set MSI as a clock source, reset prescalers.
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RCC.cfgr().write_value(Cfgr::default());
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// Wait for clock switch status bits to change.
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while RCC.cfgr().read().sws() != Sw::MSI {}
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}
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//BackupDomain::configure_ls(config.rtc_mux, config.lsi, config.lse.map(|_| Default::default()));
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PWR.cr1().modify(|w| w.set_vos(stm32_metapac::pwr::vals::Vos::RANGE0));
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let (sys_clk, sw) = match config.mux {
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ClockSrc::MSI(range) => {
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// Enable MSI
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RCC.cr().write(|w| {
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let bits: Msirange = range.into();
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w.set_msirange(bits);
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w.set_msirgsel(true);
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w.set_msion(true);
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if config.rtc_mux == RtcClockSource::LSE {
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// If LSE is enabled, enable calibration of MSI
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w.set_msipllen(true);
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} else {
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w.set_msipllen(false);
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}
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});
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while !RCC.cr().read().msirdy() {}
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// Enable as clock source for USB, RNG if running at 48 MHz
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if range == MSIRange::RANGE48M {
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RCC.ccipr1().modify(|w| {
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w.set_clk48msel(0b11);
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});
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}
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(msirange_to_hertz(range), Sw::MSI)
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}
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ClockSrc::HSI16 => {
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// Enable HSI16
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RCC.cr().write(|w| w.set_hsion(true));
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while !RCC.cr().read().hsirdy() {}
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(HSI_FREQ, Sw::HSI16)
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}
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ClockSrc::HSE(freq) => {
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// Enable HSE
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RCC.cr().write(|w| w.set_hseon(true));
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while !RCC.cr().read().hserdy() {}
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(freq, Sw::HSE)
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}
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ClockSrc::PLL(src, divr, prediv, mul, divq) => {
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let src_freq = match src {
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PLLSource::HSE(freq) => {
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// Enable HSE
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RCC.cr().write(|w| w.set_hseon(true));
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while !RCC.cr().read().hserdy() {}
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freq
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}
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PLLSource::HSI16 => {
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// Enable HSI
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RCC.cr().write(|w| w.set_hsion(true));
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while !RCC.cr().read().hsirdy() {}
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HSI_FREQ
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}
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PLLSource::MSI(range) => {
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// Enable MSI
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RCC.cr().write(|w| {
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let bits: Msirange = range.into();
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w.set_msirange(bits);
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w.set_msipllen(false); // should be turned on if LSE is started
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w.set_msirgsel(true);
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w.set_msion(true);
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});
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while !RCC.cr().read().msirdy() {}
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msirange_to_hertz(range)
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}
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};
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// Disable PLL
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RCC.cr().modify(|w| w.set_pllon(false));
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while RCC.cr().read().pllrdy() {}
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let freq = src_freq / prediv * mul / divr;
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RCC.pllcfgr().write(move |w| {
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w.set_plln(mul);
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w.set_pllm(prediv);
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w.set_pllr(divr);
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if let Some(divq) = divq {
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w.set_pllq(divq);
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w.set_pllqen(true);
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}
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w.set_pllsrc(src.into());
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});
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// Enable as clock source for USB, RNG if PLL48 divisor is provided
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if let Some(divq) = divq {
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let freq = src_freq / prediv * mul / divq;
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assert!(freq.0 == 48_000_000);
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RCC.ccipr1().modify(|w| {
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w.set_clk48msel(0b10);
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});
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}
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if let Some((mul, prediv, r_div, q_div, p_div)) = config.pllsai1 {
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RCC.pllsai1cfgr().write(move |w| {
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w.set_plln(mul);
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w.set_pllm(prediv);
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if let Some(r_div) = r_div {
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w.set_pllr(r_div);
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w.set_pllren(true);
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}
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if let Some(q_div) = q_div {
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w.set_pllq(q_div);
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w.set_pllqen(true);
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let freq = src_freq / prediv * mul / q_div;
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if freq.0 == 48_000_000 {
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RCC.ccipr1().modify(|w| {
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w.set_clk48msel(0b1);
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});
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}
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}
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if let Some(p_div) = p_div {
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w.set_pllp(p_div);
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w.set_pllpen(true);
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}
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});
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RCC.cr().modify(|w| w.set_pllsai1on(true));
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}
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// Enable PLL
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RCC.cr().modify(|w| w.set_pllon(true));
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while !RCC.cr().read().pllrdy() {}
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RCC.pllcfgr().modify(|w| w.set_pllren(true));
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(freq, Sw::PLL)
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}
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};
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if config.hsi48 {
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RCC.crrcr().modify(|w| w.set_hsi48on(true));
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while !RCC.crrcr().read().hsi48rdy() {}
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// Enable as clock source for USB, RNG and SDMMC
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RCC.ccipr1().modify(|w| w.set_clk48msel(0));
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}
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// Set flash wait states
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// VCORE Range 0 (performance), others TODO
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FLASH.acr().modify(|w| {
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w.set_latency(match sys_clk.0 {
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0..=20_000_000 => 0,
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0..=40_000_000 => 1,
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0..=60_000_000 => 2,
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0..=80_000_000 => 3,
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0..=100_000_000 => 4,
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_ => 5,
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})
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});
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RCC.cfgr().modify(|w| {
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w.set_sw(sw);
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w.set_hpre(config.ahb_pre.into());
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w.set_ppre1(config.apb1_pre.into());
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w.set_ppre2(config.apb2_pre.into());
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});
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let ahb_freq = sys_clk / config.ahb_pre;
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let (apb1_freq, apb1_tim_freq) = match config.apb1_pre {
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APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
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pre => {
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let freq = ahb_freq / pre;
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(freq, freq * 2u32)
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}
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};
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let (apb2_freq, apb2_tim_freq) = match config.apb2_pre {
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APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
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pre => {
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let freq = ahb_freq / pre;
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(freq, freq * 2u32)
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}
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};
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set_freqs(Clocks {
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sys: sys_clk,
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ahb1: ahb_freq,
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ahb2: ahb_freq,
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ahb3: ahb_freq,
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apb1: apb1_freq,
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apb2: apb2_freq,
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apb1_tim: apb1_tim_freq,
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apb2_tim: apb2_tim_freq,
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});
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}
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fn msirange_to_hertz(range: Msirange) -> Hertz {
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match range {
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MSIRange::RANGE100K => Hertz(100_000),
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MSIRange::RANGE200K => Hertz(200_000),
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MSIRange::RANGE400K => Hertz(400_000),
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MSIRange::RANGE800K => Hertz(800_000),
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MSIRange::RANGE1M => Hertz(1_000_000),
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MSIRange::RANGE2M => Hertz(2_000_000),
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MSIRange::RANGE4M => Hertz(4_000_000),
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MSIRange::RANGE8M => Hertz(8_000_000),
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MSIRange::RANGE16M => Hertz(16_000_000),
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MSIRange::RANGE24M => Hertz(24_000_000),
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MSIRange::RANGE32M => Hertz(32_000_000),
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MSIRange::RANGE48M => Hertz(48_000_000),
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_ => unreachable!(),
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}
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}
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