322 lines
8.9 KiB
Rust
322 lines
8.9 KiB
Rust
use super::sealed::RccPeripheral;
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use crate::pac::pwr::vals::Vos;
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use crate::pac::rcc::vals::{Hpre, Ppre, Sw};
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use crate::pac::{FLASH, PWR, RCC};
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use crate::rcc::{set_freqs, Clocks};
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use crate::time::Hertz;
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const HSI: u32 = 16_000_000;
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/// Clocks configuration
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#[non_exhaustive]
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#[derive(Default)]
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pub struct Config {
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pub hse: Option<Hertz>,
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pub bypass_hse: bool,
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pub hclk: Option<Hertz>,
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pub sys_ck: Option<Hertz>,
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pub pclk1: Option<Hertz>,
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pub pclk2: Option<Hertz>,
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pub pll48: bool,
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}
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unsafe fn setup_pll(
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pllsrcclk: u32,
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use_hse: bool,
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pllsysclk: Option<u32>,
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pll48clk: bool,
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) -> PllResults {
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use crate::pac::rcc::vals::{Pllp, Pllsrc};
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let sysclk = pllsysclk.unwrap_or(pllsrcclk);
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if pllsysclk.is_none() && !pll48clk {
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RCC.pllcfgr()
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.modify(|w| w.set_pllsrc(Pllsrc(use_hse as u8)));
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return PllResults {
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use_pll: false,
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pllsysclk: None,
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pll48clk: None,
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};
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}
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// Input divisor from PLL source clock, must result to frequency in
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// the range from 1 to 2 MHz
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let pllm_min = (pllsrcclk + 1_999_999) / 2_000_000;
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let pllm_max = pllsrcclk / 1_000_000;
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// Sysclk output divisor must be one of 2, 4, 6 or 8
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let sysclk_div = core::cmp::min(8, (432_000_000 / sysclk) & !1);
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let target_freq = if pll48clk {
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48_000_000
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} else {
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sysclk * sysclk_div
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};
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// Find the lowest pllm value that minimize the difference between
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// target frequency and the real vco_out frequency.
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let pllm = unwrap!((pllm_min..=pllm_max).min_by_key(|pllm| {
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let vco_in = pllsrcclk / pllm;
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let plln = target_freq / vco_in;
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target_freq - vco_in * plln
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}));
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let vco_in = pllsrcclk / pllm;
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assert!((1_000_000..=2_000_000).contains(&vco_in));
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// Main scaler, must result in >= 100MHz (>= 192MHz for F401)
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// and <= 432MHz, min 50, max 432
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let plln = if pll48clk {
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// try the different valid pllq according to the valid
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// main scaller values, and take the best
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let pllq = unwrap!((4..=9).min_by_key(|pllq| {
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let plln = 48_000_000 * pllq / vco_in;
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let pll48_diff = 48_000_000 - vco_in * plln / pllq;
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let sysclk_diff = (sysclk as i32 - (vco_in * plln / sysclk_div) as i32).abs();
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(pll48_diff, sysclk_diff)
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}));
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48_000_000 * pllq / vco_in
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} else {
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sysclk * sysclk_div / vco_in
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};
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let pllp = (sysclk_div / 2) - 1;
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let pllq = (vco_in * plln + 47_999_999) / 48_000_000;
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let real_pll48clk = vco_in * plln / pllq;
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RCC.pllcfgr().modify(|w| {
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w.set_pllm(pllm as u8);
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w.set_plln(plln as u16);
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w.set_pllp(Pllp(pllp as u8));
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w.set_pllq(pllq as u8);
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w.set_pllsrc(Pllsrc(use_hse as u8));
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});
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let real_pllsysclk = vco_in * plln / sysclk_div;
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PllResults {
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use_pll: true,
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pllsysclk: Some(real_pllsysclk),
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pll48clk: if pll48clk { Some(real_pll48clk) } else { None },
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}
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}
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unsafe fn flash_setup(sysclk: u32) {
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use crate::pac::flash::vals::Latency;
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// Be conservative with voltage ranges
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const FLASH_LATENCY_STEP: u32 = 30_000_000;
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critical_section::with(|_| {
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FLASH
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.acr()
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.modify(|w| w.set_latency(Latency(((sysclk - 1) / FLASH_LATENCY_STEP) as u8)));
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});
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}
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pub(crate) unsafe fn init(config: Config) {
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crate::peripherals::PWR::enable();
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if let Some(hse) = config.hse {
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if config.bypass_hse {
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assert!((max::HSE_BYPASS_MIN..=max::HSE_BYPASS_MAX).contains(&hse.0));
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} else {
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assert!((max::HSE_OSC_MIN..=max::HSE_OSC_MAX).contains(&hse.0));
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}
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}
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let pllsrcclk = config.hse.map(|hse| hse.0).unwrap_or(HSI);
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let sysclk = config.sys_ck.map(|sys| sys.0).unwrap_or(pllsrcclk);
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let sysclk_on_pll = sysclk != pllsrcclk;
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assert!((max::SYSCLK_MIN..=max::SYSCLK_MAX).contains(&sysclk));
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let plls = setup_pll(
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pllsrcclk,
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config.hse.is_some(),
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if sysclk_on_pll { Some(sysclk) } else { None },
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config.pll48,
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);
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if config.pll48 {
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let freq = unwrap!(plls.pll48clk);
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assert!((max::PLL_48_CLK as i32 - freq as i32).abs() <= max::PLL_48_TOLERANCE as i32);
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}
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let sysclk = if sysclk_on_pll {
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unwrap!(plls.pllsysclk)
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} else {
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sysclk
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};
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// AHB prescaler
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let hclk = config.hclk.map(|h| h.0).unwrap_or(sysclk);
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let (hpre_bits, hpre_div) = match (sysclk + hclk - 1) / hclk {
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0 => unreachable!(),
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1 => (Hpre::DIV1, 1),
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2 => (Hpre::DIV2, 2),
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3..=5 => (Hpre::DIV4, 4),
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6..=11 => (Hpre::DIV8, 8),
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12..=39 => (Hpre::DIV16, 16),
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40..=95 => (Hpre::DIV64, 64),
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96..=191 => (Hpre::DIV128, 128),
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192..=383 => (Hpre::DIV256, 256),
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_ => (Hpre::DIV512, 512),
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};
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// Calculate real AHB clock
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let hclk = sysclk / hpre_div;
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assert!(hclk <= max::HCLK_MAX);
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let pclk1 = config
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.pclk1
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.map(|p| p.0)
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.unwrap_or_else(|| core::cmp::min(max::PCLK1_MAX, hclk));
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let (ppre1_bits, ppre1) = match (hclk + pclk1 - 1) / pclk1 {
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0 => unreachable!(),
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1 => (0b000, 1),
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2 => (0b100, 2),
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3..=5 => (0b101, 4),
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6..=11 => (0b110, 8),
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_ => (0b111, 16),
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};
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let timer_mul1 = if ppre1 == 1 { 1 } else { 2 };
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// Calculate real APB1 clock
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let pclk1 = hclk / ppre1;
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assert!((max::PCLK1_MIN..=max::PCLK1_MAX).contains(&pclk1));
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let pclk2 = config
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.pclk2
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.map(|p| p.0)
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.unwrap_or_else(|| core::cmp::min(max::PCLK2_MAX, hclk));
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let (ppre2_bits, ppre2) = match (hclk + pclk2 - 1) / pclk2 {
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0 => unreachable!(),
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1 => (0b000, 1),
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2 => (0b100, 2),
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3..=5 => (0b101, 4),
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6..=11 => (0b110, 8),
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_ => (0b111, 16),
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};
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let timer_mul2 = if ppre2 == 1 { 1 } else { 2 };
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// Calculate real APB2 clock
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let pclk2 = hclk / ppre2;
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assert!((max::PCLK2_MIN..=max::PCLK2_MAX).contains(&pclk2));
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flash_setup(sysclk);
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if config.hse.is_some() {
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RCC.cr().modify(|w| {
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w.set_hsebyp(config.bypass_hse);
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w.set_hseon(true);
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});
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while !RCC.cr().read().hserdy() {}
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}
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if plls.use_pll {
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RCC.cr().modify(|w| w.set_pllon(false));
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// enable PWR and setup VOSScale
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RCC.apb1enr().modify(|w| w.set_pwren(true));
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let vos_scale = if sysclk <= 144_000_000 {
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3
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} else if sysclk <= 168_000_000 {
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2
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} else {
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1
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};
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PWR.cr1().modify(|w| {
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w.set_vos(match vos_scale {
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3 => Vos::SCALE3,
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2 => Vos::SCALE2,
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1 => Vos::SCALE1,
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_ => panic!("Invalid VOS Scale."),
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})
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});
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RCC.cr().modify(|w| w.set_pllon(true));
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if hclk > max::HCLK_OVERDRIVE_FREQUENCY {
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PWR.cr1().modify(|w| w.set_oden(true));
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while !PWR.csr1().read().odrdy() {}
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PWR.cr1().modify(|w| w.set_odswen(true));
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while !PWR.csr1().read().odswrdy() {}
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}
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while !RCC.cr().read().pllrdy() {}
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}
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RCC.cfgr().modify(|w| {
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w.set_ppre2(Ppre(ppre2_bits));
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w.set_ppre1(Ppre(ppre1_bits));
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w.set_hpre(hpre_bits);
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});
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// Wait for the new prescalers to kick in
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// "The clocks are divided with the new prescaler factor from 1 to 16 AHB cycles after write"
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cortex_m::asm::delay(16);
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RCC.cfgr().modify(|w| {
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w.set_sw(if sysclk_on_pll {
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Sw::PLL
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} else if config.hse.is_some() {
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Sw::HSE
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} else {
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Sw::HSI
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})
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});
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set_freqs(Clocks {
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sys: Hertz(sysclk),
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apb1: Hertz(pclk1),
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apb2: Hertz(pclk2),
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apb1_tim: Hertz(pclk1 * timer_mul1),
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apb2_tim: Hertz(pclk2 * timer_mul2),
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ahb1: Hertz(hclk),
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ahb2: Hertz(hclk),
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ahb3: Hertz(hclk),
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pll48: plls.pll48clk.map(Hertz),
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});
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}
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struct PllResults {
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use_pll: bool,
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pllsysclk: Option<u32>,
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pll48clk: Option<u32>,
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}
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mod max {
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pub(crate) const HSE_OSC_MIN: u32 = 4_000_000;
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pub(crate) const HSE_OSC_MAX: u32 = 26_000_000;
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pub(crate) const HSE_BYPASS_MIN: u32 = 1_000_000;
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pub(crate) const HSE_BYPASS_MAX: u32 = 50_000_000;
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pub(crate) const HCLK_MAX: u32 = 216_000_000;
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pub(crate) const HCLK_OVERDRIVE_FREQUENCY: u32 = 180_000_000;
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pub(crate) const SYSCLK_MIN: u32 = 12_500_000;
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pub(crate) const SYSCLK_MAX: u32 = 216_000_000;
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pub(crate) const PCLK1_MIN: u32 = SYSCLK_MIN;
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pub(crate) const PCLK1_MAX: u32 = SYSCLK_MAX / 4;
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pub(crate) const PCLK2_MIN: u32 = SYSCLK_MIN;
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pub(crate) const PCLK2_MAX: u32 = SYSCLK_MAX / 2;
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// USB specification allows +-0.25%
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pub(crate) const PLL_48_CLK: u32 = 48_000_000;
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pub(crate) const PLL_48_TOLERANCE: u32 = 120_000;
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}
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