701 lines
23 KiB
Rust
701 lines
23 KiB
Rust
use core::marker::PhantomData;
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use embassy_hal_common::Peripheral;
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use embedded_storage::nor_flash::{
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check_erase, check_read, check_write, ErrorType, MultiwriteNorFlash, NorFlash, NorFlashError, NorFlashErrorKind,
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ReadNorFlash,
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};
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use crate::pac;
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use crate::peripherals::FLASH;
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pub const FLASH_BASE: usize = 0x10000000;
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// **NOTE**:
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//
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// These limitations are currently enforced because of using the
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// RP2040 boot-rom flash functions, that are optimized for flash compatibility
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// rather than performance.
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pub const PAGE_SIZE: usize = 256;
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pub const WRITE_SIZE: usize = 1;
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pub const READ_SIZE: usize = 1;
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pub const ERASE_SIZE: usize = 4096;
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/// Error type for NVMC operations.
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#[derive(Debug, Copy, Clone, PartialEq, Eq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum Error {
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/// Operation using a location not in flash.
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OutOfBounds,
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/// Unaligned operation or using unaligned buffers.
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Unaligned,
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InvalidCore,
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Other,
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}
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impl From<NorFlashErrorKind> for Error {
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fn from(e: NorFlashErrorKind) -> Self {
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match e {
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NorFlashErrorKind::NotAligned => Self::Unaligned,
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NorFlashErrorKind::OutOfBounds => Self::OutOfBounds,
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_ => Self::Other,
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}
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}
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}
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impl NorFlashError for Error {
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fn kind(&self) -> NorFlashErrorKind {
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match self {
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Self::OutOfBounds => NorFlashErrorKind::OutOfBounds,
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Self::Unaligned => NorFlashErrorKind::NotAligned,
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_ => NorFlashErrorKind::Other,
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}
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}
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}
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pub struct Flash<'d, T: Instance, const FLASH_SIZE: usize>(PhantomData<&'d mut T>);
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impl<'d, T: Instance, const FLASH_SIZE: usize> Flash<'d, T, FLASH_SIZE> {
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pub fn new(_flash: impl Peripheral<P = T> + 'd) -> Self {
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Self(PhantomData)
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}
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pub fn read(&mut self, offset: u32, bytes: &mut [u8]) -> Result<(), Error> {
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trace!(
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"Reading from 0x{:x} to 0x{:x}",
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FLASH_BASE + offset as usize,
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FLASH_BASE + offset as usize + bytes.len()
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);
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check_read(self, offset, bytes.len())?;
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let flash_data = unsafe { core::slice::from_raw_parts((FLASH_BASE as u32 + offset) as *const u8, bytes.len()) };
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bytes.copy_from_slice(flash_data);
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Ok(())
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}
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pub fn capacity(&self) -> usize {
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FLASH_SIZE
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}
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pub fn erase(&mut self, from: u32, to: u32) -> Result<(), Error> {
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check_erase(self, from, to)?;
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trace!(
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"Erasing from 0x{:x} to 0x{:x}",
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FLASH_BASE as u32 + from,
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FLASH_BASE as u32 + to
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);
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let len = to - from;
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unsafe { self.in_ram(|| ram_helpers::flash_range_erase(from, len, true))? };
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Ok(())
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}
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pub fn write(&mut self, offset: u32, bytes: &[u8]) -> Result<(), Error> {
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check_write(self, offset, bytes.len())?;
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trace!("Writing {:?} bytes to 0x{:x}", bytes.len(), FLASH_BASE as u32 + offset);
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let end_offset = offset as usize + bytes.len();
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let padded_offset = (offset as *const u8).align_offset(PAGE_SIZE);
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let start_padding = core::cmp::min(padded_offset, bytes.len());
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// Pad in the beginning
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if start_padding > 0 {
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let start = PAGE_SIZE - padded_offset;
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let end = start + start_padding;
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let mut pad_buf = [0xFF_u8; PAGE_SIZE];
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pad_buf[start..end].copy_from_slice(&bytes[..start_padding]);
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let unaligned_offset = offset as usize - start;
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unsafe { self.in_ram(|| ram_helpers::flash_range_program(unaligned_offset as u32, &pad_buf, true))? }
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}
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let remaining_len = bytes.len() - start_padding;
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let end_padding = start_padding + PAGE_SIZE * (remaining_len / PAGE_SIZE);
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// Write aligned slice of length in multiples of 256 bytes
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// If the remaining bytes to be written is more than a full page.
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if remaining_len >= PAGE_SIZE {
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let mut aligned_offset = if start_padding > 0 {
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offset as usize + padded_offset
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} else {
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offset as usize
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};
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if bytes.as_ptr() as usize >= 0x2000_0000 {
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let aligned_data = &bytes[start_padding..end_padding];
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unsafe { self.in_ram(|| ram_helpers::flash_range_program(aligned_offset as u32, aligned_data, true))? }
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} else {
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for chunk in bytes[start_padding..end_padding].chunks_exact(PAGE_SIZE) {
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let mut ram_buf = [0xFF_u8; PAGE_SIZE];
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ram_buf.copy_from_slice(chunk);
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unsafe { self.in_ram(|| ram_helpers::flash_range_program(aligned_offset as u32, &ram_buf, true))? }
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aligned_offset += PAGE_SIZE;
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}
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}
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}
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// Pad in the end
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let rem_offset = (end_offset as *const u8).align_offset(PAGE_SIZE);
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let rem_padding = remaining_len % PAGE_SIZE;
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if rem_padding > 0 {
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let mut pad_buf = [0xFF_u8; PAGE_SIZE];
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pad_buf[..rem_padding].copy_from_slice(&bytes[end_padding..]);
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let unaligned_offset = end_offset - (PAGE_SIZE - rem_offset);
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unsafe { self.in_ram(|| ram_helpers::flash_range_program(unaligned_offset as u32, &pad_buf, true))? }
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}
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Ok(())
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}
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/// Make sure to uphold the contract points with rp2040-flash.
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/// - interrupts must be disabled
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/// - DMA must not access flash memory
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unsafe fn in_ram(&mut self, operation: impl FnOnce()) -> Result<(), Error> {
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// Make sure we're running on CORE0
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let core_id: u32 = unsafe { pac::SIO.cpuid().read() };
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if core_id != 0 {
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return Err(Error::InvalidCore);
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}
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// Make sure CORE1 is paused during the entire duration of the RAM function
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crate::multicore::pause_core1();
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critical_section::with(|_| {
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// Wait for all DMA channels in flash to finish before ram operation
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const SRAM_LOWER: u32 = 0x2000_0000;
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for n in 0..crate::dma::CHANNEL_COUNT {
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let ch = crate::pac::DMA.ch(n);
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while ch.read_addr().read() < SRAM_LOWER && ch.ctrl_trig().read().busy() {}
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}
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// Run our flash operation in RAM
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operation();
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});
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// Resume CORE1 execution
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crate::multicore::resume_core1();
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Ok(())
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}
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/// Read SPI flash unique ID
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pub fn unique_id(&mut self, uid: &mut [u8]) -> Result<(), Error> {
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unsafe { self.in_ram(|| ram_helpers::flash_unique_id(uid, true))? };
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Ok(())
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}
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/// Read SPI flash JEDEC ID
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pub fn jedec_id(&mut self) -> Result<u32, Error> {
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let mut jedec = None;
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unsafe {
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self.in_ram(|| {
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jedec.replace(ram_helpers::flash_jedec_id(true));
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})?;
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};
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Ok(jedec.unwrap())
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}
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}
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impl<'d, T: Instance, const FLASH_SIZE: usize> ErrorType for Flash<'d, T, FLASH_SIZE> {
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type Error = Error;
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}
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impl<'d, T: Instance, const FLASH_SIZE: usize> ReadNorFlash for Flash<'d, T, FLASH_SIZE> {
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const READ_SIZE: usize = READ_SIZE;
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fn read(&mut self, offset: u32, bytes: &mut [u8]) -> Result<(), Self::Error> {
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self.read(offset, bytes)
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}
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fn capacity(&self) -> usize {
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self.capacity()
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}
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}
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impl<'d, T: Instance, const FLASH_SIZE: usize> MultiwriteNorFlash for Flash<'d, T, FLASH_SIZE> {}
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impl<'d, T: Instance, const FLASH_SIZE: usize> NorFlash for Flash<'d, T, FLASH_SIZE> {
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const WRITE_SIZE: usize = WRITE_SIZE;
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const ERASE_SIZE: usize = ERASE_SIZE;
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fn erase(&mut self, from: u32, to: u32) -> Result<(), Self::Error> {
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self.erase(from, to)
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}
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fn write(&mut self, offset: u32, bytes: &[u8]) -> Result<(), Self::Error> {
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self.write(offset, bytes)
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}
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}
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#[allow(dead_code)]
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mod ram_helpers {
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use core::marker::PhantomData;
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use crate::rom_data;
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#[repr(C)]
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struct FlashFunctionPointers<'a> {
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connect_internal_flash: unsafe extern "C" fn() -> (),
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flash_exit_xip: unsafe extern "C" fn() -> (),
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flash_range_erase: Option<unsafe extern "C" fn(addr: u32, count: usize, block_size: u32, block_cmd: u8) -> ()>,
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flash_range_program: Option<unsafe extern "C" fn(addr: u32, data: *const u8, count: usize) -> ()>,
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flash_flush_cache: unsafe extern "C" fn() -> (),
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flash_enter_cmd_xip: unsafe extern "C" fn() -> (),
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phantom: PhantomData<&'a ()>,
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}
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#[allow(unused)]
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fn flash_function_pointers(erase: bool, write: bool) -> FlashFunctionPointers<'static> {
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FlashFunctionPointers {
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connect_internal_flash: rom_data::connect_internal_flash::ptr(),
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flash_exit_xip: rom_data::flash_exit_xip::ptr(),
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flash_range_erase: if erase {
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Some(rom_data::flash_range_erase::ptr())
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} else {
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None
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},
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flash_range_program: if write {
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Some(rom_data::flash_range_program::ptr())
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} else {
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None
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},
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flash_flush_cache: rom_data::flash_flush_cache::ptr(),
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flash_enter_cmd_xip: rom_data::flash_enter_cmd_xip::ptr(),
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phantom: PhantomData,
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}
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}
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#[allow(unused)]
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/// # Safety
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///
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/// `boot2` must contain a valid 2nd stage boot loader which can be called to re-initialize XIP mode
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unsafe fn flash_function_pointers_with_boot2(erase: bool, write: bool, boot2: &[u32; 64]) -> FlashFunctionPointers {
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let boot2_fn_ptr = (boot2 as *const u32 as *const u8).offset(1);
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let boot2_fn: unsafe extern "C" fn() -> () = core::mem::transmute(boot2_fn_ptr);
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FlashFunctionPointers {
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connect_internal_flash: rom_data::connect_internal_flash::ptr(),
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flash_exit_xip: rom_data::flash_exit_xip::ptr(),
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flash_range_erase: if erase {
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Some(rom_data::flash_range_erase::ptr())
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} else {
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None
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},
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flash_range_program: if write {
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Some(rom_data::flash_range_program::ptr())
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} else {
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None
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},
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flash_flush_cache: rom_data::flash_flush_cache::ptr(),
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flash_enter_cmd_xip: boot2_fn,
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phantom: PhantomData,
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}
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}
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/// Erase a flash range starting at `addr` with length `len`.
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///
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/// `addr` and `len` must be multiples of 4096
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///
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/// If `use_boot2` is `true`, a copy of the 2nd stage boot loader
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/// is used to re-initialize the XIP engine after flashing.
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///
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/// # Safety
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///
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/// Nothing must access flash while this is running.
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/// Usually this means:
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/// - interrupts must be disabled
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/// - 2nd core must be running code from RAM or ROM with interrupts disabled
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/// - DMA must not access flash memory
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///
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/// `addr` and `len` parameters must be valid and are not checked.
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pub unsafe fn flash_range_erase(addr: u32, len: u32, use_boot2: bool) {
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let mut boot2 = [0u32; 256 / 4];
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let ptrs = if use_boot2 {
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rom_data::memcpy44(&mut boot2 as *mut _, super::FLASH_BASE as *const _, 256);
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flash_function_pointers_with_boot2(true, false, &boot2)
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} else {
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flash_function_pointers(true, false)
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};
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core::sync::atomic::compiler_fence(core::sync::atomic::Ordering::SeqCst);
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write_flash_inner(addr, len, None, &ptrs as *const FlashFunctionPointers);
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}
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/// Erase and rewrite a flash range starting at `addr` with data `data`.
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///
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/// `addr` and `data.len()` must be multiples of 4096
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///
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/// If `use_boot2` is `true`, a copy of the 2nd stage boot loader
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/// is used to re-initialize the XIP engine after flashing.
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///
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/// # Safety
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///
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/// Nothing must access flash while this is running.
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/// Usually this means:
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/// - interrupts must be disabled
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/// - 2nd core must be running code from RAM or ROM with interrupts disabled
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/// - DMA must not access flash memory
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///
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/// `addr` and `len` parameters must be valid and are not checked.
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pub unsafe fn flash_range_erase_and_program(addr: u32, data: &[u8], use_boot2: bool) {
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let mut boot2 = [0u32; 256 / 4];
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let ptrs = if use_boot2 {
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rom_data::memcpy44(&mut boot2 as *mut _, super::FLASH_BASE as *const _, 256);
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flash_function_pointers_with_boot2(true, true, &boot2)
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} else {
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flash_function_pointers(true, true)
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};
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core::sync::atomic::compiler_fence(core::sync::atomic::Ordering::SeqCst);
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write_flash_inner(
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addr,
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data.len() as u32,
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Some(data),
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&ptrs as *const FlashFunctionPointers,
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);
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}
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/// Write a flash range starting at `addr` with data `data`.
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///
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/// `addr` and `data.len()` must be multiples of 256
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///
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/// If `use_boot2` is `true`, a copy of the 2nd stage boot loader
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/// is used to re-initialize the XIP engine after flashing.
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///
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/// # Safety
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///
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/// Nothing must access flash while this is running.
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/// Usually this means:
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/// - interrupts must be disabled
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/// - 2nd core must be running code from RAM or ROM with interrupts disabled
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/// - DMA must not access flash memory
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///
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/// `addr` and `len` parameters must be valid and are not checked.
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pub unsafe fn flash_range_program(addr: u32, data: &[u8], use_boot2: bool) {
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let mut boot2 = [0u32; 256 / 4];
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let ptrs = if use_boot2 {
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rom_data::memcpy44(&mut boot2 as *mut _, super::FLASH_BASE as *const _, 256);
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flash_function_pointers_with_boot2(false, true, &boot2)
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} else {
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flash_function_pointers(false, true)
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};
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core::sync::atomic::compiler_fence(core::sync::atomic::Ordering::SeqCst);
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write_flash_inner(
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addr,
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data.len() as u32,
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Some(data),
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&ptrs as *const FlashFunctionPointers,
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);
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}
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/// # Safety
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///
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/// Nothing must access flash while this is running.
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/// Usually this means:
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/// - interrupts must be disabled
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/// - 2nd core must be running code from RAM or ROM with interrupts disabled
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/// - DMA must not access flash memory
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/// Length of data must be a multiple of 4096
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/// addr must be aligned to 4096
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#[inline(never)]
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#[link_section = ".data.ram_func"]
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unsafe fn write_flash_inner(addr: u32, len: u32, data: Option<&[u8]>, ptrs: *const FlashFunctionPointers) {
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/*
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Should be equivalent to:
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rom_data::connect_internal_flash();
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rom_data::flash_exit_xip();
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rom_data::flash_range_erase(addr, len, 1 << 31, 0); // if selected
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rom_data::flash_range_program(addr, data as *const _, len); // if selected
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rom_data::flash_flush_cache();
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rom_data::flash_enter_cmd_xip();
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*/
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#[cfg(target_arch = "arm")]
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core::arch::asm!(
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"mov r8, r0",
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"mov r9, r2",
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"mov r10, r1",
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"ldr r4, [{ptrs}, #0]",
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"blx r4", // connect_internal_flash()
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"ldr r4, [{ptrs}, #4]",
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"blx r4", // flash_exit_xip()
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"mov r0, r8", // r0 = addr
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"mov r1, r10", // r1 = len
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"movs r2, #1",
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"lsls r2, r2, #31", // r2 = 1 << 31
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"movs r3, #0", // r3 = 0
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"ldr r4, [{ptrs}, #8]",
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"cmp r4, #0",
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"beq 1f",
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"blx r4", // flash_range_erase(addr, len, 1 << 31, 0)
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"1:",
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"mov r0, r8", // r0 = addr
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"mov r1, r9", // r0 = data
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"mov r2, r10", // r2 = len
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"ldr r4, [{ptrs}, #12]",
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"cmp r4, #0",
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"beq 1f",
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"blx r4", // flash_range_program(addr, data, len);
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"1:",
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"ldr r4, [{ptrs}, #16]",
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"blx r4", // flash_flush_cache();
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"ldr r4, [{ptrs}, #20]",
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"blx r4", // flash_enter_cmd_xip();
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ptrs = in(reg) ptrs,
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// Registers r8-r15 are not allocated automatically,
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// so assign them manually. We need to use them as
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// otherwise there are not enough registers available.
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in("r0") addr,
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in("r2") data.map(|d| d.as_ptr()).unwrap_or(core::ptr::null()),
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in("r1") len,
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out("r3") _,
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out("r4") _,
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lateout("r8") _,
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lateout("r9") _,
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lateout("r10") _,
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clobber_abi("C"),
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);
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}
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#[repr(C)]
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struct FlashCommand {
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cmd_addr: *const u8,
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cmd_addr_len: u32,
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dummy_len: u32,
|
|
data: *mut u8,
|
|
data_len: u32,
|
|
}
|
|
|
|
/// Return SPI flash unique ID
|
|
///
|
|
/// Not all SPI flashes implement this command, so check the JEDEC
|
|
/// ID before relying on it. The Winbond parts commonly seen on
|
|
/// RP2040 devboards (JEDEC=0xEF7015) support an 8-byte unique ID;
|
|
/// https://forums.raspberrypi.com/viewtopic.php?t=331949 suggests
|
|
/// that LCSC (Zetta) parts have a 16-byte unique ID (which is
|
|
/// *not* unique in just its first 8 bytes),
|
|
/// JEDEC=0xBA6015. Macronix and Spansion parts do not have a
|
|
/// unique ID.
|
|
///
|
|
/// The returned bytes are relatively predictable and should be
|
|
/// salted and hashed before use if that is an issue (e.g. for MAC
|
|
/// addresses).
|
|
///
|
|
/// # Safety
|
|
///
|
|
/// Nothing must access flash while this is running.
|
|
/// Usually this means:
|
|
/// - interrupts must be disabled
|
|
/// - 2nd core must be running code from RAM or ROM with interrupts disabled
|
|
/// - DMA must not access flash memory
|
|
///
|
|
/// Credit: taken from `rp2040-flash` (also licensed Apache+MIT)
|
|
pub unsafe fn flash_unique_id(out: &mut [u8], use_boot2: bool) {
|
|
let mut boot2 = [0u32; 256 / 4];
|
|
let ptrs = if use_boot2 {
|
|
rom_data::memcpy44(&mut boot2 as *mut _, 0x10000000 as *const _, 256);
|
|
flash_function_pointers_with_boot2(false, false, &boot2)
|
|
} else {
|
|
flash_function_pointers(false, false)
|
|
};
|
|
// 4B - read unique ID
|
|
let cmd = [0x4B];
|
|
read_flash(&cmd[..], 4, out, &ptrs as *const FlashFunctionPointers);
|
|
}
|
|
|
|
/// Return SPI flash JEDEC ID
|
|
///
|
|
/// This is the three-byte manufacturer-and-model identifier
|
|
/// commonly used to check before using manufacturer-specific SPI
|
|
/// flash features, e.g. 0xEF7015 for Winbond W25Q16JV.
|
|
///
|
|
/// # Safety
|
|
///
|
|
/// Nothing must access flash while this is running.
|
|
/// Usually this means:
|
|
/// - interrupts must be disabled
|
|
/// - 2nd core must be running code from RAM or ROM with interrupts disabled
|
|
/// - DMA must not access flash memory
|
|
///
|
|
/// Credit: taken from `rp2040-flash` (also licensed Apache+MIT)
|
|
pub unsafe fn flash_jedec_id(use_boot2: bool) -> u32 {
|
|
let mut boot2 = [0u32; 256 / 4];
|
|
let ptrs = if use_boot2 {
|
|
rom_data::memcpy44(&mut boot2 as *mut _, 0x10000000 as *const _, 256);
|
|
flash_function_pointers_with_boot2(false, false, &boot2)
|
|
} else {
|
|
flash_function_pointers(false, false)
|
|
};
|
|
let mut id = [0u8; 4];
|
|
// 9F - read JEDEC ID
|
|
let cmd = [0x9F];
|
|
read_flash(&cmd[..], 0, &mut id[1..4], &ptrs as *const FlashFunctionPointers);
|
|
u32::from_be_bytes(id)
|
|
}
|
|
|
|
unsafe fn read_flash(cmd_addr: &[u8], dummy_len: u32, out: &mut [u8], ptrs: *const FlashFunctionPointers) {
|
|
read_flash_inner(
|
|
FlashCommand {
|
|
cmd_addr: cmd_addr.as_ptr(),
|
|
cmd_addr_len: cmd_addr.len() as u32,
|
|
dummy_len,
|
|
data: out.as_mut_ptr(),
|
|
data_len: out.len() as u32,
|
|
},
|
|
ptrs,
|
|
);
|
|
}
|
|
|
|
/// Issue a generic SPI flash read command
|
|
///
|
|
/// # Arguments
|
|
///
|
|
/// * `cmd` - `FlashCommand` structure
|
|
/// * `ptrs` - Flash function pointers as per `write_flash_inner`
|
|
///
|
|
/// Credit: taken from `rp2040-flash` (also licensed Apache+MIT)
|
|
#[inline(never)]
|
|
#[link_section = ".data.ram_func"]
|
|
unsafe fn read_flash_inner(cmd: FlashCommand, ptrs: *const FlashFunctionPointers) {
|
|
core::arch::asm!(
|
|
"mov r10, r0", // cmd
|
|
"mov r5, r1", // ptrs
|
|
|
|
"ldr r4, [r5, #0]",
|
|
"blx r4", // connect_internal_flash()
|
|
|
|
"ldr r4, [r5, #4]",
|
|
"blx r4", // flash_exit_xip()
|
|
|
|
"mov r7, r10", // cmd
|
|
|
|
"movs r4, #0x18",
|
|
"lsls r4, r4, #24", // 0x18000000, SSI, RP2040 datasheet 4.10.13
|
|
|
|
// Disable, write 0 to SSIENR
|
|
"movs r0, #0",
|
|
"str r0, [r4, #8]", // SSIENR
|
|
|
|
// Write ctrlr0
|
|
"movs r0, #0x3",
|
|
"lsls r0, r0, #8", // TMOD=0x300
|
|
"ldr r1, [r4, #0]", // CTRLR0
|
|
"orrs r1, r0",
|
|
"str r1, [r4, #0]",
|
|
|
|
// Write ctrlr1 with len-1
|
|
"ldr r0, [r7, #8]", // dummy_len
|
|
"ldr r1, [r7, #16]", // data_len
|
|
"add r0, r1",
|
|
"subs r0, #1",
|
|
"str r0, [r4, #0x04]", // CTRLR1
|
|
|
|
// Enable, write 1 to ssienr
|
|
"movs r0, #1",
|
|
"str r0, [r4, #8]", // SSIENR
|
|
|
|
// Write cmd/addr phase to DR
|
|
"mov r2, r4",
|
|
"adds r2, 0x60", // &DR
|
|
"ldr r0, [r7, #0]", // cmd_addr
|
|
"ldr r1, [r7, #4]", // cmd_addr_len
|
|
"10:",
|
|
"ldrb r3, [r0]",
|
|
"strb r3, [r2]", // DR
|
|
"adds r0, #1",
|
|
"subs r1, #1",
|
|
"bne 10b",
|
|
|
|
// Skip any dummy cycles
|
|
"ldr r1, [r7, #8]", // dummy_len
|
|
"cmp r1, #0",
|
|
"beq 9f",
|
|
"4:",
|
|
"ldr r3, [r4, #0x28]", // SR
|
|
"movs r2, #0x8",
|
|
"tst r3, r2", // SR.RFNE
|
|
"beq 4b",
|
|
|
|
"mov r2, r4",
|
|
"adds r2, 0x60", // &DR
|
|
"ldrb r3, [r2]", // DR
|
|
"subs r1, #1",
|
|
"bne 4b",
|
|
|
|
// Read RX fifo
|
|
"9:",
|
|
"ldr r0, [r7, #12]", // data
|
|
"ldr r1, [r7, #16]", // data_len
|
|
|
|
"2:",
|
|
"ldr r3, [r4, #0x28]", // SR
|
|
"movs r2, #0x8",
|
|
"tst r3, r2", // SR.RFNE
|
|
"beq 2b",
|
|
|
|
"mov r2, r4",
|
|
"adds r2, 0x60", // &DR
|
|
"ldrb r3, [r2]", // DR
|
|
"strb r3, [r0]",
|
|
"adds r0, #1",
|
|
"subs r1, #1",
|
|
"bne 2b",
|
|
|
|
// Disable, write 0 to ssienr
|
|
"movs r0, #0",
|
|
"str r0, [r4, #8]", // SSIENR
|
|
|
|
// Write 0 to CTRLR1 (returning to its default value)
|
|
//
|
|
// flash_enter_cmd_xip does NOT do this, and everything goes
|
|
// wrong unless we do it here
|
|
"str r0, [r4, #4]", // CTRLR1
|
|
|
|
"ldr r4, [r5, #20]",
|
|
"blx r4", // flash_enter_cmd_xip();
|
|
|
|
in("r0") &cmd as *const FlashCommand,
|
|
in("r1") ptrs,
|
|
out("r2") _,
|
|
out("r3") _,
|
|
out("r4") _,
|
|
// Registers r8-r10 are used to store values
|
|
// from r0-r2 in registers not clobbered by
|
|
// function calls.
|
|
// The values can't be passed in using r8-r10 directly
|
|
// due to https://github.com/rust-lang/rust/issues/99071
|
|
out("r8") _,
|
|
out("r9") _,
|
|
out("r10") _,
|
|
clobber_abi("C"),
|
|
);
|
|
}
|
|
}
|
|
|
|
mod sealed {
|
|
pub trait Instance {}
|
|
}
|
|
|
|
pub trait Instance: sealed::Instance {}
|
|
|
|
impl sealed::Instance for FLASH {}
|
|
impl Instance for FLASH {}
|