62 lines
2.0 KiB
Rust
62 lines
2.0 KiB
Rust
use embedded_hal_async::spi::{Operation, SpiDevice};
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const SOCKET_BASE: u16 = 0x400;
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const TX_BASE: u16 = 0x4000;
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const RX_BASE: u16 = 0x6000;
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pub enum W5100S {}
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impl super::Chip for W5100S {}
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impl super::sealed::Chip for W5100S {
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type Address = u16;
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const COMMON_MODE: Self::Address = 0x00;
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const COMMON_MAC: Self::Address = 0x09;
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const COMMON_SOCKET_INTR: Self::Address = 0x16;
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const COMMON_PHY_CFG: Self::Address = 0x3c;
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const SOCKET_MODE: Self::Address = SOCKET_BASE + 0x00;
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const SOCKET_COMMAND: Self::Address = SOCKET_BASE + 0x01;
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const SOCKET_RXBUF_SIZE: Self::Address = SOCKET_BASE + 0x1E;
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const SOCKET_TXBUF_SIZE: Self::Address = SOCKET_BASE + 0x1F;
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const SOCKET_TX_FREE_SIZE: Self::Address = SOCKET_BASE + 0x20;
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const SOCKET_TX_DATA_WRITE_PTR: Self::Address = SOCKET_BASE + 0x24;
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const SOCKET_RECVD_SIZE: Self::Address = SOCKET_BASE + 0x26;
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const SOCKET_RX_DATA_READ_PTR: Self::Address = SOCKET_BASE + 0x28;
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const SOCKET_INTR_MASK: Self::Address = SOCKET_BASE + 0x2C;
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const SOCKET_INTR: Self::Address = SOCKET_BASE + 0x02;
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const SOCKET_MODE_VALUE: u8 = (1 << 2) | (1 << 6);
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const BUF_SIZE: u16 = 0x2000;
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const AUTO_WRAP: bool = false;
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fn rx_addr(addr: u16) -> Self::Address {
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RX_BASE + addr
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}
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fn tx_addr(addr: u16) -> Self::Address {
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TX_BASE + addr
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}
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async fn bus_read<SPI: SpiDevice>(
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spi: &mut SPI,
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address: Self::Address,
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data: &mut [u8],
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) -> Result<(), SPI::Error> {
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spi.transaction(&mut [
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Operation::Write(&[0x0F, (address >> 8) as u8, address as u8]),
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Operation::Read(data),
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])
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.await
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}
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async fn bus_write<SPI: SpiDevice>(spi: &mut SPI, address: Self::Address, data: &[u8]) -> Result<(), SPI::Error> {
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spi.transaction(&mut [
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Operation::Write(&[0xF0, (address >> 8) as u8, address as u8]),
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Operation::Write(data),
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])
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.await
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}
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}
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