370 lines
9.4 KiB
Rust
370 lines
9.4 KiB
Rust
use crate::pac::rcc::vals::{Hpre, Msirange, Plldiv, Pllmul, Pllsrc, Ppre, Sw};
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use crate::pac::RCC;
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#[cfg(crs)]
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use crate::pac::{CRS, SYSCFG};
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use crate::rcc::{set_freqs, Clocks};
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use crate::time::Hertz;
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/// HSI speed
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pub const HSI_FREQ: Hertz = Hertz(16_000_000);
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/// LSI speed
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pub const LSI_FREQ: Hertz = Hertz(32_000);
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/// System clock mux source
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#[derive(Clone, Copy)]
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pub enum ClockSrc {
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MSI(MSIRange),
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PLL(PLLSource, PLLMul, PLLDiv),
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HSE(Hertz),
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HSI16,
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}
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/// MSI Clock Range
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///
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/// These ranges control the frequency of the MSI. Internally, these ranges map
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/// to the `MSIRANGE` bits in the `RCC_ICSCR` register.
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#[derive(Clone, Copy)]
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pub enum MSIRange {
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/// Around 65.536 kHz
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Range0,
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/// Around 131.072 kHz
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Range1,
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/// Around 262.144 kHz
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Range2,
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/// Around 524.288 kHz
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Range3,
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/// Around 1.048 MHz
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Range4,
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/// Around 2.097 MHz (reset value)
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Range5,
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/// Around 4.194 MHz
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Range6,
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}
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impl Default for MSIRange {
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fn default() -> MSIRange {
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MSIRange::Range5
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}
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}
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/// PLL divider
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#[derive(Clone, Copy)]
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pub enum PLLDiv {
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Div2,
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Div3,
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Div4,
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}
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/// PLL multiplier
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#[derive(Clone, Copy)]
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pub enum PLLMul {
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Mul3,
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Mul4,
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Mul6,
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Mul8,
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Mul12,
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Mul16,
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Mul24,
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Mul32,
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Mul48,
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}
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/// AHB prescaler
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#[derive(Clone, Copy, PartialEq)]
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pub enum AHBPrescaler {
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NotDivided,
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Div2,
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Div4,
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Div8,
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Div16,
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Div64,
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Div128,
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Div256,
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Div512,
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}
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/// APB prescaler
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#[derive(Clone, Copy)]
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pub enum APBPrescaler {
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NotDivided,
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Div2,
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Div4,
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Div8,
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Div16,
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}
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/// PLL clock input source
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#[derive(Clone, Copy)]
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pub enum PLLSource {
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HSI16,
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HSE(Hertz),
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}
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impl From<PLLMul> for Pllmul {
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fn from(val: PLLMul) -> Pllmul {
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match val {
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PLLMul::Mul3 => Pllmul::MUL3,
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PLLMul::Mul4 => Pllmul::MUL4,
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PLLMul::Mul6 => Pllmul::MUL6,
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PLLMul::Mul8 => Pllmul::MUL8,
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PLLMul::Mul12 => Pllmul::MUL12,
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PLLMul::Mul16 => Pllmul::MUL16,
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PLLMul::Mul24 => Pllmul::MUL24,
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PLLMul::Mul32 => Pllmul::MUL32,
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PLLMul::Mul48 => Pllmul::MUL48,
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}
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}
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}
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impl From<PLLDiv> for Plldiv {
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fn from(val: PLLDiv) -> Plldiv {
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match val {
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PLLDiv::Div2 => Plldiv::DIV2,
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PLLDiv::Div3 => Plldiv::DIV3,
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PLLDiv::Div4 => Plldiv::DIV4,
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}
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}
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}
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impl From<PLLSource> for Pllsrc {
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fn from(val: PLLSource) -> Pllsrc {
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match val {
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PLLSource::HSI16 => Pllsrc::HSI16,
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PLLSource::HSE(_) => Pllsrc::HSE,
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}
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}
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}
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impl From<APBPrescaler> for Ppre {
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fn from(val: APBPrescaler) -> Ppre {
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match val {
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APBPrescaler::NotDivided => Ppre::DIV1,
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APBPrescaler::Div2 => Ppre::DIV2,
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APBPrescaler::Div4 => Ppre::DIV4,
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APBPrescaler::Div8 => Ppre::DIV8,
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APBPrescaler::Div16 => Ppre::DIV16,
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}
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}
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}
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impl From<AHBPrescaler> for Hpre {
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fn from(val: AHBPrescaler) -> Hpre {
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match val {
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AHBPrescaler::NotDivided => Hpre::DIV1,
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AHBPrescaler::Div2 => Hpre::DIV2,
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AHBPrescaler::Div4 => Hpre::DIV4,
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AHBPrescaler::Div8 => Hpre::DIV8,
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AHBPrescaler::Div16 => Hpre::DIV16,
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AHBPrescaler::Div64 => Hpre::DIV64,
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AHBPrescaler::Div128 => Hpre::DIV128,
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AHBPrescaler::Div256 => Hpre::DIV256,
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AHBPrescaler::Div512 => Hpre::DIV512,
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}
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}
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}
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impl From<MSIRange> for Msirange {
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fn from(val: MSIRange) -> Msirange {
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match val {
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MSIRange::Range0 => Msirange::RANGE0,
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MSIRange::Range1 => Msirange::RANGE1,
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MSIRange::Range2 => Msirange::RANGE2,
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MSIRange::Range3 => Msirange::RANGE3,
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MSIRange::Range4 => Msirange::RANGE4,
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MSIRange::Range5 => Msirange::RANGE5,
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MSIRange::Range6 => Msirange::RANGE6,
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}
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}
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}
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/// Clocks configutation
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pub struct Config {
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pub mux: ClockSrc,
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pub ahb_pre: AHBPrescaler,
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pub apb1_pre: APBPrescaler,
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pub apb2_pre: APBPrescaler,
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#[cfg(crs)]
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pub enable_hsi48: bool,
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}
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impl Default for Config {
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#[inline]
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fn default() -> Config {
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Config {
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mux: ClockSrc::MSI(MSIRange::default()),
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ahb_pre: AHBPrescaler::NotDivided,
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apb1_pre: APBPrescaler::NotDivided,
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apb2_pre: APBPrescaler::NotDivided,
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#[cfg(crs)]
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enable_hsi48: false,
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}
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}
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}
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pub(crate) unsafe fn init(config: Config) {
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let (sys_clk, sw) = match config.mux {
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ClockSrc::MSI(range) => {
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// Set MSI range
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RCC.icscr().write(|w| w.set_msirange(range.into()));
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// Enable MSI
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RCC.cr().write(|w| w.set_msion(true));
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while !RCC.cr().read().msirdy() {}
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let freq = 32_768 * (1 << (range as u8 + 1));
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(freq, Sw::MSI)
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}
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ClockSrc::HSI16 => {
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// Enable HSI16
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RCC.cr().write(|w| w.set_hsi16on(true));
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while !RCC.cr().read().hsi16rdyf() {}
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(HSI_FREQ.0, Sw::HSI16)
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}
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ClockSrc::HSE(freq) => {
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// Enable HSE
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RCC.cr().write(|w| w.set_hseon(true));
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while !RCC.cr().read().hserdy() {}
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(freq.0, Sw::HSE)
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}
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ClockSrc::PLL(src, mul, div) => {
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let freq = match src {
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PLLSource::HSE(freq) => {
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// Enable HSE
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RCC.cr().write(|w| w.set_hseon(true));
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while !RCC.cr().read().hserdy() {}
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freq.0
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}
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PLLSource::HSI16 => {
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// Enable HSI
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RCC.cr().write(|w| w.set_hsi16on(true));
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while !RCC.cr().read().hsi16rdyf() {}
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HSI_FREQ.0
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}
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};
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// Disable PLL
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RCC.cr().modify(|w| w.set_pllon(false));
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while RCC.cr().read().pllrdy() {}
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let freq = match mul {
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PLLMul::Mul3 => freq * 3,
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PLLMul::Mul4 => freq * 4,
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PLLMul::Mul6 => freq * 6,
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PLLMul::Mul8 => freq * 8,
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PLLMul::Mul12 => freq * 12,
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PLLMul::Mul16 => freq * 16,
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PLLMul::Mul24 => freq * 24,
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PLLMul::Mul32 => freq * 32,
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PLLMul::Mul48 => freq * 48,
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};
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let freq = match div {
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PLLDiv::Div2 => freq / 2,
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PLLDiv::Div3 => freq / 3,
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PLLDiv::Div4 => freq / 4,
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};
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assert!(freq <= 32_000_000);
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RCC.cfgr().write(move |w| {
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w.set_pllmul(mul.into());
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w.set_plldiv(div.into());
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w.set_pllsrc(src.into());
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});
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// Enable PLL
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RCC.cr().modify(|w| w.set_pllon(true));
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while !RCC.cr().read().pllrdy() {}
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(freq, Sw::PLL)
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}
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};
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RCC.cfgr().modify(|w| {
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w.set_sw(sw);
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w.set_hpre(config.ahb_pre.into());
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w.set_ppre1(config.apb1_pre.into());
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w.set_ppre2(config.apb2_pre.into());
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});
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let ahb_freq: u32 = match config.ahb_pre {
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AHBPrescaler::NotDivided => sys_clk,
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pre => {
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let pre: Hpre = pre.into();
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let pre = 1 << (pre.0 as u32 - 7);
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sys_clk / pre
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}
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};
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let (apb1_freq, apb1_tim_freq) = match config.apb1_pre {
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APBPrescaler::NotDivided => (ahb_freq, ahb_freq),
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pre => {
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let pre: Ppre = pre.into();
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let pre: u8 = 1 << (pre.0 - 3);
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let freq = ahb_freq / pre as u32;
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(freq, freq * 2)
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}
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};
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let (apb2_freq, apb2_tim_freq) = match config.apb2_pre {
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APBPrescaler::NotDivided => (ahb_freq, ahb_freq),
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pre => {
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let pre: Ppre = pre.into();
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let pre: u8 = 1 << (pre.0 - 3);
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let freq = ahb_freq / pre as u32;
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(freq, freq * 2)
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}
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};
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#[cfg(crs)]
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if config.enable_hsi48 {
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// Reset SYSCFG peripheral
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RCC.apb2rstr().modify(|w| w.set_syscfgrst(true));
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RCC.apb2rstr().modify(|w| w.set_syscfgrst(false));
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// Enable SYSCFG peripheral
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RCC.apb2enr().modify(|w| w.set_syscfgen(true));
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// Reset CRS peripheral
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RCC.apb1rstr().modify(|w| w.set_crsrst(true));
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RCC.apb1rstr().modify(|w| w.set_crsrst(false));
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// Enable CRS peripheral
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RCC.apb1enr().modify(|w| w.set_crsen(true));
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// Initialize CRS
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CRS.cfgr().write(|w|
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// Select LSE as synchronization source
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w.set_syncsrc(0b01));
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CRS.cr().modify(|w| {
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w.set_autotrimen(true);
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w.set_cen(true);
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});
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// Enable VREFINT reference for HSI48 oscillator
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SYSCFG.cfgr3().modify(|w| {
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w.set_enref_hsi48(true);
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w.set_en_vrefint(true);
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});
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// Select HSI48 as USB clock
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RCC.ccipr().modify(|w| w.set_hsi48msel(true));
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// Enable dedicated USB clock
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RCC.crrcr().modify(|w| w.set_hsi48on(true));
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while !RCC.crrcr().read().hsi48rdy() {}
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}
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set_freqs(Clocks {
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sys: Hertz(sys_clk),
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ahb1: Hertz(ahb_freq),
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apb1: Hertz(apb1_freq),
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apb2: Hertz(apb2_freq),
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apb1_tim: Hertz(apb1_tim_freq),
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apb2_tim: Hertz(apb2_tim_freq),
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});
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}
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