847 lines
26 KiB
Rust
847 lines
26 KiB
Rust
use core::marker::PhantomData;
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use core::slice;
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use core::sync::atomic::Ordering;
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use core::task::Poll;
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use atomic_polyfill::compiler_fence;
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use embassy_hal_common::into_ref;
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use embassy_sync::waitqueue::AtomicWaker;
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use embassy_usb::driver::{self, EndpointAllocError, EndpointError, Event, Unsupported};
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use embassy_usb::types::{EndpointAddress, EndpointInfo, EndpointType, UsbDirection};
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use futures::future::poll_fn;
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use futures::Future;
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use crate::interrupt::{Interrupt, InterruptExt};
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use crate::{pac, peripherals, Peripheral, RegExt};
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pub(crate) mod sealed {
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pub trait Instance {
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fn regs() -> crate::pac::usb::Usb;
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fn dpram() -> crate::pac::usb_dpram::UsbDpram;
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}
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}
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pub trait Instance: sealed::Instance + 'static {
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type Interrupt: Interrupt;
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}
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impl crate::usb::sealed::Instance for peripherals::USB {
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fn regs() -> pac::usb::Usb {
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pac::USBCTRL_REGS
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}
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fn dpram() -> crate::pac::usb_dpram::UsbDpram {
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pac::USBCTRL_DPRAM
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}
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}
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impl crate::usb::Instance for peripherals::USB {
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type Interrupt = crate::interrupt::USBCTRL_IRQ;
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}
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const EP_COUNT: usize = 16;
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const EP_MEMORY_SIZE: usize = 4096;
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const EP_MEMORY: *mut u8 = pac::USBCTRL_DPRAM.0;
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const NEW_AW: AtomicWaker = AtomicWaker::new();
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static BUS_WAKER: AtomicWaker = NEW_AW;
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static EP_IN_WAKERS: [AtomicWaker; EP_COUNT] = [NEW_AW; EP_COUNT];
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static EP_OUT_WAKERS: [AtomicWaker; EP_COUNT] = [NEW_AW; EP_COUNT];
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struct EndpointBuffer<T: Instance> {
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addr: u16,
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len: u16,
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_phantom: PhantomData<T>,
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}
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impl<T: Instance> EndpointBuffer<T> {
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const fn new(addr: u16, len: u16) -> Self {
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Self {
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addr,
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len,
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_phantom: PhantomData,
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}
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}
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fn read(&mut self, buf: &mut [u8]) {
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assert!(buf.len() <= self.len as usize);
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compiler_fence(Ordering::SeqCst);
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let mem = unsafe { slice::from_raw_parts(EP_MEMORY.add(self.addr as _), buf.len()) };
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buf.copy_from_slice(mem);
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compiler_fence(Ordering::SeqCst);
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}
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fn write(&mut self, buf: &[u8]) {
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assert!(buf.len() <= self.len as usize);
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compiler_fence(Ordering::SeqCst);
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let mem = unsafe { slice::from_raw_parts_mut(EP_MEMORY.add(self.addr as _), buf.len()) };
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mem.copy_from_slice(buf);
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compiler_fence(Ordering::SeqCst);
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}
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}
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#[derive(Debug, Clone, Copy)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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struct EndpointData {
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ep_type: EndpointType, // only valid if used
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max_packet_size: u16,
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used: bool,
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}
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impl EndpointData {
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const fn new() -> Self {
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Self {
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ep_type: EndpointType::Bulk,
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max_packet_size: 0,
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used: false,
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}
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}
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}
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pub struct Driver<'d, T: Instance> {
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phantom: PhantomData<&'d mut T>,
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ep_in: [EndpointData; EP_COUNT],
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ep_out: [EndpointData; EP_COUNT],
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ep_mem_free: u16, // first free address in EP mem, in bytes.
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}
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impl<'d, T: Instance> Driver<'d, T> {
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pub fn new(_usb: impl Peripheral<P = T> + 'd, irq: impl Peripheral<P = T::Interrupt> + 'd) -> Self {
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into_ref!(irq);
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irq.set_handler(Self::on_interrupt);
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irq.unpend();
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irq.enable();
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let regs = T::regs();
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unsafe {
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// zero fill regs
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let p = regs.0 as *mut u32;
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for i in 0..0x9c / 4 {
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p.add(i).write_volatile(0)
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}
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// zero fill epmem
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let p = EP_MEMORY as *mut u32;
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for i in 0..0x100 / 4 {
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p.add(i).write_volatile(0)
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}
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regs.usb_muxing().write(|w| {
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w.set_to_phy(true);
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w.set_softcon(true);
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});
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regs.usb_pwr().write(|w| {
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w.set_vbus_detect(true);
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w.set_vbus_detect_override_en(true);
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});
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regs.main_ctrl().write(|w| {
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w.set_controller_en(true);
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});
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}
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// Initialize the bus so that it signals that power is available
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BUS_WAKER.wake();
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Self {
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phantom: PhantomData,
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ep_in: [EndpointData::new(); EP_COUNT],
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ep_out: [EndpointData::new(); EP_COUNT],
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ep_mem_free: 0x180, // data buffer region
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}
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}
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fn on_interrupt(_: *mut ()) {
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unsafe {
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let regs = T::regs();
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//let x = regs.istr().read().0;
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//trace!("USB IRQ: {:08x}", x);
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let ints = regs.ints().read();
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if ints.bus_reset() {
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regs.inte().write_clear(|w| w.set_bus_reset(true));
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BUS_WAKER.wake();
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}
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if ints.dev_resume_from_host() {
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regs.inte().write_clear(|w| w.set_dev_resume_from_host(true));
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BUS_WAKER.wake();
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}
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if ints.dev_suspend() {
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regs.inte().write_clear(|w| w.set_dev_suspend(true));
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BUS_WAKER.wake();
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}
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if ints.setup_req() {
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regs.inte().write_clear(|w| w.set_setup_req(true));
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EP_OUT_WAKERS[0].wake();
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}
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if ints.buff_status() {
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let s = regs.buff_status().read();
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regs.buff_status().write_value(s);
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for i in 0..EP_COUNT {
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if s.ep_in(i) {
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EP_IN_WAKERS[i].wake();
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}
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if s.ep_out(i) {
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EP_OUT_WAKERS[i].wake();
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}
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}
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}
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}
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}
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fn alloc_endpoint<D: Dir>(
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&mut self,
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ep_type: EndpointType,
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max_packet_size: u16,
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interval: u8,
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) -> Result<Endpoint<'d, T, D>, driver::EndpointAllocError> {
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trace!(
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"allocating type={:?} mps={:?} interval={}, dir={:?}",
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ep_type,
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max_packet_size,
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interval,
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D::dir()
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);
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let alloc = match D::dir() {
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UsbDirection::Out => &mut self.ep_out,
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UsbDirection::In => &mut self.ep_in,
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};
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let index = alloc.iter_mut().enumerate().find(|(i, ep)| {
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if *i == 0 {
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return false; // reserved for control pipe
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}
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!ep.used
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});
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let (index, ep) = index.ok_or(EndpointAllocError)?;
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assert!(!ep.used);
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if max_packet_size > 64 {
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warn!("max_packet_size too high: {}", max_packet_size);
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return Err(EndpointAllocError);
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}
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// ep mem addrs must be 64-byte aligned, so there's no point in trying
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// to allocate smaller chunks to save memory.
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let len = 64;
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let addr = self.ep_mem_free;
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if addr + len > EP_MEMORY_SIZE as _ {
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warn!("Endpoint memory full");
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return Err(EndpointAllocError);
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}
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self.ep_mem_free += len;
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let buf = EndpointBuffer {
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addr,
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len,
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_phantom: PhantomData,
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};
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trace!(" index={} addr={} len={}", index, buf.addr, buf.len);
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ep.ep_type = ep_type;
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ep.used = true;
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ep.max_packet_size = max_packet_size;
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let ep_type_reg = match ep_type {
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EndpointType::Bulk => pac::usb_dpram::vals::EpControlEndpointType::BULK,
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EndpointType::Control => pac::usb_dpram::vals::EpControlEndpointType::CONTROL,
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EndpointType::Interrupt => pac::usb_dpram::vals::EpControlEndpointType::INTERRUPT,
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EndpointType::Isochronous => pac::usb_dpram::vals::EpControlEndpointType::ISOCHRONOUS,
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};
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match D::dir() {
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UsbDirection::Out => unsafe {
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T::dpram().ep_out_control(index - 1).write(|w| {
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w.set_enable(false);
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w.set_buffer_address(addr);
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w.set_interrupt_per_buff(true);
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w.set_endpoint_type(ep_type_reg);
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})
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},
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UsbDirection::In => unsafe {
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T::dpram().ep_in_control(index - 1).write(|w| {
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w.set_enable(false);
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w.set_buffer_address(addr);
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w.set_interrupt_per_buff(true);
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w.set_endpoint_type(ep_type_reg);
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})
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},
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}
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Ok(Endpoint {
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_phantom: PhantomData,
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info: EndpointInfo {
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addr: EndpointAddress::from_parts(index, D::dir()),
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ep_type,
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max_packet_size,
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interval,
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},
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buf,
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})
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}
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}
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impl<'d, T: Instance> driver::Driver<'d> for Driver<'d, T> {
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type EndpointOut = Endpoint<'d, T, Out>;
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type EndpointIn = Endpoint<'d, T, In>;
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type ControlPipe = ControlPipe<'d, T>;
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type Bus = Bus<'d, T>;
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fn alloc_endpoint_in(
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&mut self,
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ep_type: EndpointType,
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max_packet_size: u16,
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interval: u8,
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) -> Result<Self::EndpointIn, driver::EndpointAllocError> {
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self.alloc_endpoint(ep_type, max_packet_size, interval)
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}
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fn alloc_endpoint_out(
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&mut self,
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ep_type: EndpointType,
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max_packet_size: u16,
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interval: u8,
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) -> Result<Self::EndpointOut, driver::EndpointAllocError> {
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self.alloc_endpoint(ep_type, max_packet_size, interval)
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}
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fn start(self, control_max_packet_size: u16) -> (Self::Bus, Self::ControlPipe) {
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let regs = T::regs();
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unsafe {
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regs.inte().write(|w| {
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w.set_bus_reset(true);
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w.set_buff_status(true);
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w.set_dev_resume_from_host(true);
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w.set_dev_suspend(true);
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w.set_setup_req(true);
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});
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regs.int_ep_ctrl().write(|w| {
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w.set_int_ep_active(0xFFFE); // all EPs
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});
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regs.sie_ctrl().write(|w| {
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w.set_ep0_int_1buf(true);
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w.set_pullup_en(true);
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})
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}
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trace!("enabled");
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(
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Bus {
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phantom: PhantomData,
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inited: false,
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ep_out: self.ep_out,
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},
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ControlPipe {
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_phantom: PhantomData,
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max_packet_size: control_max_packet_size,
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},
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)
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}
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}
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pub struct Bus<'d, T: Instance> {
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phantom: PhantomData<&'d mut T>,
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ep_out: [EndpointData; EP_COUNT],
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inited: bool,
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}
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impl<'d, T: Instance> driver::Bus for Bus<'d, T> {
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type PollFuture<'a> = impl Future<Output = Event> + 'a where Self: 'a;
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fn poll<'a>(&'a mut self) -> Self::PollFuture<'a> {
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poll_fn(move |cx| unsafe {
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BUS_WAKER.register(cx.waker());
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if !self.inited {
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self.inited = true;
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return Poll::Ready(Event::PowerDetected);
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}
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let regs = T::regs();
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let siestatus = regs.sie_status().read();
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if siestatus.resume() {
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regs.sie_status().write(|w| w.set_resume(true));
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return Poll::Ready(Event::Resume);
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}
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if siestatus.bus_reset() {
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regs.sie_status().write(|w| {
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w.set_bus_reset(true);
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w.set_setup_rec(true);
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});
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regs.buff_status().write(|w| w.0 = 0xFFFF_FFFF);
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regs.addr_endp().write(|w| w.set_address(0));
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for i in 1..EP_COUNT {
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T::dpram().ep_in_control(i - 1).modify(|w| w.set_enable(false));
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T::dpram().ep_out_control(i - 1).modify(|w| w.set_enable(false));
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}
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for w in &EP_IN_WAKERS {
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w.wake()
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}
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for w in &EP_OUT_WAKERS {
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w.wake()
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}
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return Poll::Ready(Event::Reset);
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}
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if siestatus.suspended() {
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regs.sie_status().write(|w| w.set_suspended(true));
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return Poll::Ready(Event::Suspend);
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}
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// no pending event. Reenable all irqs.
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regs.inte().write_set(|w| {
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w.set_bus_reset(true);
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w.set_dev_resume_from_host(true);
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w.set_dev_suspend(true);
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});
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Poll::Pending
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})
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}
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#[inline]
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fn set_address(&mut self, addr: u8) {
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let regs = T::regs();
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trace!("setting addr: {}", addr);
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unsafe { regs.addr_endp().write(|w| w.set_address(addr)) }
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}
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fn endpoint_set_stalled(&mut self, _ep_addr: EndpointAddress, _stalled: bool) {
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todo!();
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}
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fn endpoint_is_stalled(&mut self, _ep_addr: EndpointAddress) -> bool {
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todo!();
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}
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fn endpoint_set_enabled(&mut self, ep_addr: EndpointAddress, enabled: bool) {
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trace!("set_enabled {:?} {}", ep_addr, enabled);
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if ep_addr.index() == 0 {
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return;
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}
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let n = ep_addr.index();
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match ep_addr.direction() {
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UsbDirection::In => unsafe {
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T::dpram().ep_in_control(n - 1).modify(|w| w.set_enable(enabled));
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T::dpram().ep_in_buffer_control(ep_addr.index()).write(|w| {
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w.set_pid(0, true); // first packet is DATA0, but PID is flipped before
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});
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EP_IN_WAKERS[n].wake();
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},
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UsbDirection::Out => unsafe {
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T::dpram().ep_out_control(n - 1).modify(|w| w.set_enable(enabled));
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T::dpram().ep_out_buffer_control(ep_addr.index()).write(|w| {
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w.set_pid(0, false);
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w.set_length(0, self.ep_out[n].max_packet_size);
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});
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cortex_m::asm::delay(12);
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T::dpram().ep_out_buffer_control(ep_addr.index()).write(|w| {
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w.set_pid(0, false);
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w.set_length(0, self.ep_out[n].max_packet_size);
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w.set_available(0, true);
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});
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EP_OUT_WAKERS[n].wake();
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},
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}
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}
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type EnableFuture<'a> = impl Future<Output = ()> + 'a where Self: 'a;
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fn enable(&mut self) -> Self::EnableFuture<'_> {
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async move {}
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}
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type DisableFuture<'a> = impl Future<Output = ()> + 'a where Self: 'a;
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fn disable(&mut self) -> Self::DisableFuture<'_> {
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async move {}
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}
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type RemoteWakeupFuture<'a> = impl Future<Output = Result<(), Unsupported>> + 'a where Self: 'a;
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fn remote_wakeup(&mut self) -> Self::RemoteWakeupFuture<'_> {
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async move { Err(Unsupported) }
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}
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}
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trait Dir {
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fn dir() -> UsbDirection;
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fn waker(i: usize) -> &'static AtomicWaker;
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}
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pub enum In {}
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impl Dir for In {
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fn dir() -> UsbDirection {
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UsbDirection::In
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}
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#[inline]
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fn waker(i: usize) -> &'static AtomicWaker {
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&EP_IN_WAKERS[i]
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}
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}
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pub enum Out {}
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impl Dir for Out {
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fn dir() -> UsbDirection {
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UsbDirection::Out
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}
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#[inline]
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fn waker(i: usize) -> &'static AtomicWaker {
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&EP_OUT_WAKERS[i]
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}
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}
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pub struct Endpoint<'d, T: Instance, D> {
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_phantom: PhantomData<(&'d mut T, D)>,
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info: EndpointInfo,
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buf: EndpointBuffer<T>,
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}
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impl<'d, T: Instance> driver::Endpoint for Endpoint<'d, T, In> {
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fn info(&self) -> &EndpointInfo {
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&self.info
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}
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type WaitEnabledFuture<'a> = impl Future<Output = ()> + 'a where Self: 'a;
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fn wait_enabled(&mut self) -> Self::WaitEnabledFuture<'_> {
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async move {
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trace!("wait_enabled IN WAITING");
|
|
let index = self.info.addr.index();
|
|
poll_fn(|cx| {
|
|
EP_OUT_WAKERS[index].register(cx.waker());
|
|
let val = unsafe { T::dpram().ep_in_control(self.info.addr.index() - 1).read() };
|
|
if val.enable() {
|
|
Poll::Ready(())
|
|
} else {
|
|
Poll::Pending
|
|
}
|
|
})
|
|
.await;
|
|
trace!("wait_enabled IN OK");
|
|
}
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Instance> driver::Endpoint for Endpoint<'d, T, Out> {
|
|
fn info(&self) -> &EndpointInfo {
|
|
&self.info
|
|
}
|
|
|
|
type WaitEnabledFuture<'a> = impl Future<Output = ()> + 'a where Self: 'a;
|
|
|
|
fn wait_enabled(&mut self) -> Self::WaitEnabledFuture<'_> {
|
|
async move {
|
|
trace!("wait_enabled OUT WAITING");
|
|
let index = self.info.addr.index();
|
|
poll_fn(|cx| {
|
|
EP_OUT_WAKERS[index].register(cx.waker());
|
|
let val = unsafe { T::dpram().ep_out_control(self.info.addr.index() - 1).read() };
|
|
if val.enable() {
|
|
Poll::Ready(())
|
|
} else {
|
|
Poll::Pending
|
|
}
|
|
})
|
|
.await;
|
|
trace!("wait_enabled OUT OK");
|
|
}
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Instance> driver::EndpointOut for Endpoint<'d, T, Out> {
|
|
type ReadFuture<'a> = impl Future<Output = Result<usize, EndpointError>> + 'a where Self: 'a;
|
|
|
|
fn read<'a>(&'a mut self, buf: &'a mut [u8]) -> Self::ReadFuture<'a> {
|
|
async move {
|
|
trace!("READ WAITING, buf.len() = {}", buf.len());
|
|
let index = self.info.addr.index();
|
|
let val = poll_fn(|cx| unsafe {
|
|
EP_OUT_WAKERS[index].register(cx.waker());
|
|
let val = T::dpram().ep_out_buffer_control(index).read();
|
|
if val.available(0) {
|
|
Poll::Pending
|
|
} else {
|
|
Poll::Ready(val)
|
|
}
|
|
})
|
|
.await;
|
|
|
|
let rx_len = val.length(0) as usize;
|
|
if rx_len > buf.len() {
|
|
return Err(EndpointError::BufferOverflow);
|
|
}
|
|
self.buf.read(&mut buf[..rx_len]);
|
|
|
|
trace!("READ OK, rx_len = {}", rx_len);
|
|
|
|
unsafe {
|
|
let pid = !val.pid(0);
|
|
T::dpram().ep_out_buffer_control(index).write(|w| {
|
|
w.set_pid(0, pid);
|
|
w.set_length(0, self.info.max_packet_size);
|
|
});
|
|
cortex_m::asm::delay(12);
|
|
T::dpram().ep_out_buffer_control(index).write(|w| {
|
|
w.set_pid(0, pid);
|
|
w.set_length(0, self.info.max_packet_size);
|
|
w.set_available(0, true);
|
|
});
|
|
}
|
|
|
|
Ok(rx_len)
|
|
}
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Instance> driver::EndpointIn for Endpoint<'d, T, In> {
|
|
type WriteFuture<'a> = impl Future<Output = Result<(), EndpointError>> + 'a where Self: 'a;
|
|
|
|
fn write<'a>(&'a mut self, buf: &'a [u8]) -> Self::WriteFuture<'a> {
|
|
async move {
|
|
if buf.len() > self.info.max_packet_size as usize {
|
|
return Err(EndpointError::BufferOverflow);
|
|
}
|
|
|
|
trace!("WRITE WAITING");
|
|
|
|
let index = self.info.addr.index();
|
|
let val = poll_fn(|cx| unsafe {
|
|
EP_IN_WAKERS[index].register(cx.waker());
|
|
let val = T::dpram().ep_in_buffer_control(index).read();
|
|
if val.available(0) {
|
|
Poll::Pending
|
|
} else {
|
|
Poll::Ready(val)
|
|
}
|
|
})
|
|
.await;
|
|
|
|
self.buf.write(buf);
|
|
|
|
unsafe {
|
|
let pid = !val.pid(0);
|
|
T::dpram().ep_in_buffer_control(index).write(|w| {
|
|
w.set_pid(0, pid);
|
|
w.set_length(0, buf.len() as _);
|
|
w.set_full(0, true);
|
|
});
|
|
cortex_m::asm::delay(12);
|
|
T::dpram().ep_in_buffer_control(index).write(|w| {
|
|
w.set_pid(0, pid);
|
|
w.set_length(0, buf.len() as _);
|
|
w.set_full(0, true);
|
|
w.set_available(0, true);
|
|
});
|
|
}
|
|
|
|
trace!("WRITE OK");
|
|
|
|
Ok(())
|
|
}
|
|
}
|
|
}
|
|
|
|
pub struct ControlPipe<'d, T: Instance> {
|
|
_phantom: PhantomData<&'d mut T>,
|
|
max_packet_size: u16,
|
|
}
|
|
|
|
impl<'d, T: Instance> driver::ControlPipe for ControlPipe<'d, T> {
|
|
type SetupFuture<'a> = impl Future<Output = [u8;8]> + 'a where Self: 'a;
|
|
type DataOutFuture<'a> = impl Future<Output = Result<usize, EndpointError>> + 'a where Self: 'a;
|
|
type DataInFuture<'a> = impl Future<Output = Result<(), EndpointError>> + 'a where Self: 'a;
|
|
type AcceptFuture<'a> = impl Future<Output = ()> + 'a where Self: 'a;
|
|
type RejectFuture<'a> = impl Future<Output = ()> + 'a where Self: 'a;
|
|
|
|
fn max_packet_size(&self) -> usize {
|
|
64
|
|
}
|
|
|
|
fn setup<'a>(&'a mut self) -> Self::SetupFuture<'a> {
|
|
async move {
|
|
loop {
|
|
trace!("SETUP read waiting");
|
|
let regs = T::regs();
|
|
unsafe { regs.inte().write_set(|w| w.set_setup_req(true)) };
|
|
|
|
poll_fn(|cx| unsafe {
|
|
EP_OUT_WAKERS[0].register(cx.waker());
|
|
let regs = T::regs();
|
|
if regs.sie_status().read().setup_rec() {
|
|
Poll::Ready(())
|
|
} else {
|
|
Poll::Pending
|
|
}
|
|
})
|
|
.await;
|
|
|
|
let mut buf = [0; 8];
|
|
EndpointBuffer::<T>::new(0, 8).read(&mut buf);
|
|
|
|
let regs = T::regs();
|
|
unsafe {
|
|
regs.sie_status().write(|w| w.set_setup_rec(true));
|
|
|
|
// set PID to 0, so (after toggling) first DATA is PID 1
|
|
T::dpram().ep_in_buffer_control(0).write(|w| w.set_pid(0, false));
|
|
T::dpram().ep_out_buffer_control(0).write(|w| w.set_pid(0, false));
|
|
}
|
|
|
|
trace!("SETUP read ok");
|
|
return buf;
|
|
}
|
|
}
|
|
}
|
|
|
|
fn data_out<'a>(&'a mut self, buf: &'a mut [u8], _first: bool, _last: bool) -> Self::DataOutFuture<'a> {
|
|
async move {
|
|
unsafe {
|
|
let bufcontrol = T::dpram().ep_out_buffer_control(0);
|
|
let pid = !bufcontrol.read().pid(0);
|
|
bufcontrol.write(|w| {
|
|
w.set_length(0, self.max_packet_size);
|
|
w.set_pid(0, pid);
|
|
});
|
|
cortex_m::asm::delay(12);
|
|
bufcontrol.write(|w| {
|
|
w.set_length(0, self.max_packet_size);
|
|
w.set_pid(0, pid);
|
|
w.set_available(0, true);
|
|
});
|
|
}
|
|
|
|
trace!("control: data_out len={} first={} last={}", buf.len(), _first, _last);
|
|
let val = poll_fn(|cx| unsafe {
|
|
EP_OUT_WAKERS[0].register(cx.waker());
|
|
let val = T::dpram().ep_out_buffer_control(0).read();
|
|
if val.available(0) {
|
|
Poll::Pending
|
|
} else {
|
|
Poll::Ready(val)
|
|
}
|
|
})
|
|
.await;
|
|
|
|
let rx_len = val.length(0) as _;
|
|
trace!("control data_out DONE, rx_len = {}", rx_len);
|
|
|
|
if rx_len > buf.len() {
|
|
return Err(EndpointError::BufferOverflow);
|
|
}
|
|
EndpointBuffer::<T>::new(0x100, 64).read(&mut buf[..rx_len]);
|
|
|
|
Ok(rx_len)
|
|
}
|
|
}
|
|
|
|
fn data_in<'a>(&'a mut self, buf: &'a [u8], _first: bool, _last: bool) -> Self::DataInFuture<'a> {
|
|
async move {
|
|
trace!("control: data_in len={} first={} last={}", buf.len(), _first, _last);
|
|
|
|
if buf.len() > 64 {
|
|
return Err(EndpointError::BufferOverflow);
|
|
}
|
|
EndpointBuffer::<T>::new(0x100, 64).write(buf);
|
|
|
|
unsafe {
|
|
let bufcontrol = T::dpram().ep_in_buffer_control(0);
|
|
let pid = !bufcontrol.read().pid(0);
|
|
bufcontrol.write(|w| {
|
|
w.set_length(0, buf.len() as _);
|
|
w.set_pid(0, pid);
|
|
w.set_full(0, true);
|
|
});
|
|
cortex_m::asm::delay(12);
|
|
bufcontrol.write(|w| {
|
|
w.set_length(0, buf.len() as _);
|
|
w.set_pid(0, pid);
|
|
w.set_full(0, true);
|
|
w.set_available(0, true);
|
|
});
|
|
}
|
|
|
|
poll_fn(|cx| unsafe {
|
|
EP_IN_WAKERS[0].register(cx.waker());
|
|
let bufcontrol = T::dpram().ep_in_buffer_control(0);
|
|
if bufcontrol.read().available(0) {
|
|
Poll::Pending
|
|
} else {
|
|
Poll::Ready(())
|
|
}
|
|
})
|
|
.await;
|
|
trace!("control: data_in DONE");
|
|
|
|
if _last {
|
|
// prepare status phase right away.
|
|
unsafe {
|
|
let bufcontrol = T::dpram().ep_out_buffer_control(0);
|
|
bufcontrol.write(|w| {
|
|
w.set_length(0, 0);
|
|
w.set_pid(0, true);
|
|
});
|
|
cortex_m::asm::delay(12);
|
|
bufcontrol.write(|w| {
|
|
w.set_length(0, 0);
|
|
w.set_pid(0, true);
|
|
w.set_available(0, true);
|
|
});
|
|
}
|
|
}
|
|
|
|
Ok(())
|
|
}
|
|
}
|
|
|
|
fn accept<'a>(&'a mut self) -> Self::AcceptFuture<'a> {
|
|
async move {
|
|
trace!("control: accept");
|
|
|
|
unsafe {
|
|
let bufcontrol = T::dpram().ep_in_buffer_control(0);
|
|
bufcontrol.write(|w| {
|
|
w.set_length(0, 0);
|
|
w.set_pid(0, true);
|
|
w.set_full(0, true);
|
|
});
|
|
cortex_m::asm::delay(12);
|
|
bufcontrol.write(|w| {
|
|
w.set_length(0, 0);
|
|
w.set_pid(0, true);
|
|
w.set_full(0, true);
|
|
w.set_available(0, true);
|
|
});
|
|
}
|
|
}
|
|
}
|
|
|
|
fn reject<'a>(&'a mut self) -> Self::RejectFuture<'a> {
|
|
async move {
|
|
trace!("control: reject");
|
|
|
|
let regs = T::regs();
|
|
unsafe {
|
|
regs.ep_stall_arm().write_set(|w| {
|
|
w.set_ep0_in(true);
|
|
w.set_ep0_out(true);
|
|
});
|
|
T::dpram().ep_out_buffer_control(0).write(|w| w.set_stall(true));
|
|
T::dpram().ep_in_buffer_control(0).write(|w| w.set_stall(true));
|
|
}
|
|
}
|
|
}
|
|
}
|