747 lines
23 KiB
Rust
747 lines
23 KiB
Rust
#![macro_use]
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//! HAL interface to the TWIM peripheral.
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//!
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//! See product specification:
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//!
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//! - nRF52832: Section 33
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//! - nRF52840: Section 6.31
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use core::future::Future;
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use core::marker::PhantomData;
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use core::sync::atomic::{compiler_fence, Ordering::SeqCst};
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use core::task::Poll;
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use embassy::interrupt::{Interrupt, InterruptExt};
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use embassy::traits;
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use embassy::util::{AtomicWaker, Unborrow};
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use embassy_extras::unborrow;
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use futures::future::poll_fn;
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use traits::i2c::I2c;
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use crate::chip::{EASY_DMA_SIZE, FORCE_COPY_BUFFER_SIZE};
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use crate::gpio::Pin as GpioPin;
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use crate::pac;
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use crate::util::{slice_in_ram, slice_in_ram_or};
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use crate::{fmt::*, gpio};
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pub enum Frequency {
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#[doc = "26738688: 100 kbps"]
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K100 = 26738688,
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#[doc = "67108864: 250 kbps"]
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K250 = 67108864,
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#[doc = "104857600: 400 kbps"]
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K400 = 104857600,
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}
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#[non_exhaustive]
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pub struct Config {
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pub frequency: Frequency,
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pub sda_pullup: bool,
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pub scl_pullup: bool,
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}
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impl Default for Config {
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fn default() -> Self {
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Self {
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frequency: Frequency::K100,
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sda_pullup: false,
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scl_pullup: false,
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}
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}
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}
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/// Interface to a TWIM instance.
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pub struct Twim<'d, T: Instance> {
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phantom: PhantomData<&'d mut T>,
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}
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impl<'d, T: Instance> Twim<'d, T> {
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pub fn new(
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_twim: impl Unborrow<Target = T> + 'd,
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irq: impl Unborrow<Target = T::Interrupt> + 'd,
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sda: impl Unborrow<Target = impl GpioPin> + 'd,
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scl: impl Unborrow<Target = impl GpioPin> + 'd,
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config: Config,
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) -> Self {
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unborrow!(irq, sda, scl);
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let r = T::regs();
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// Configure pins
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sda.conf().write(|w| {
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w.dir().input();
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w.input().connect();
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w.drive().s0d1();
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if config.sda_pullup {
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w.pull().pullup();
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}
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w
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});
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scl.conf().write(|w| {
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w.dir().input();
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w.input().connect();
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w.drive().s0d1();
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if config.scl_pullup {
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w.pull().pullup();
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}
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w
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});
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// Select pins.
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r.psel.sda.write(|w| unsafe { w.bits(sda.psel_bits()) });
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r.psel.scl.write(|w| unsafe { w.bits(scl.psel_bits()) });
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// Enable TWIM instance.
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r.enable.write(|w| w.enable().enabled());
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// Configure frequency.
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r.frequency
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.write(|w| unsafe { w.frequency().bits(config.frequency as u32) });
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// Disable all events interrupts
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r.intenclr.write(|w| unsafe { w.bits(0xFFFF_FFFF) });
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irq.set_handler(Self::on_interrupt);
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irq.unpend();
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irq.enable();
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Self {
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phantom: PhantomData,
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}
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}
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fn on_interrupt(_: *mut ()) {
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let r = T::regs();
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let s = T::state();
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if r.events_stopped.read().bits() != 0 {
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s.end_waker.wake();
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r.intenclr.write(|w| w.stopped().clear());
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}
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if r.events_error.read().bits() != 0 {
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s.end_waker.wake();
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r.intenclr.write(|w| w.error().clear());
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}
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}
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/// Set TX buffer, checking that it is in RAM and has suitable length.
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unsafe fn set_tx_buffer(&mut self, buffer: &[u8]) -> Result<(), Error> {
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slice_in_ram_or(buffer, Error::DMABufferNotInDataMemory)?;
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if buffer.len() == 0 {
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return Err(Error::TxBufferZeroLength);
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}
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if buffer.len() > EASY_DMA_SIZE {
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return Err(Error::TxBufferTooLong);
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}
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let r = T::regs();
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r.txd.ptr.write(|w|
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// We're giving the register a pointer to the stack. Since we're
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// waiting for the I2C transaction to end before this stack pointer
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// becomes invalid, there's nothing wrong here.
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//
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// The PTR field is a full 32 bits wide and accepts the full range
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// of values.
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w.ptr().bits(buffer.as_ptr() as u32));
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r.txd.maxcnt.write(|w|
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// We're giving it the length of the buffer, so no danger of
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// accessing invalid memory. We have verified that the length of the
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// buffer fits in an `u8`, so the cast to `u8` is also fine.
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//
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// The MAXCNT field is 8 bits wide and accepts the full range of
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// values.
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w.maxcnt().bits(buffer.len() as _));
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Ok(())
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}
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/// Set RX buffer, checking that it has suitable length.
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unsafe fn set_rx_buffer(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
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// NOTE: RAM slice check is not necessary, as a mutable
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// slice can only be built from data located in RAM.
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if buffer.len() == 0 {
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return Err(Error::RxBufferZeroLength);
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}
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if buffer.len() > EASY_DMA_SIZE {
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return Err(Error::RxBufferTooLong);
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}
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let r = T::regs();
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r.rxd.ptr.write(|w|
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// We're giving the register a pointer to the stack. Since we're
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// waiting for the I2C transaction to end before this stack pointer
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// becomes invalid, there's nothing wrong here.
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//
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// The PTR field is a full 32 bits wide and accepts the full range
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// of values.
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w.ptr().bits(buffer.as_mut_ptr() as u32));
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r.rxd.maxcnt.write(|w|
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// We're giving it the length of the buffer, so no danger of
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// accessing invalid memory. We have verified that the length of the
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// buffer fits in an `u8`, so the cast to the type of maxcnt
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// is also fine.
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//
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// Note that that nrf52840 maxcnt is a wider
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// type than a u8, so we use a `_` cast rather than a `u8` cast.
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// The MAXCNT field is thus at least 8 bits wide and accepts the
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// full range of values that fit in a `u8`.
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w.maxcnt().bits(buffer.len() as _));
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Ok(())
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}
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fn clear_errorsrc(&mut self) {
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let r = T::regs();
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r.errorsrc
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.write(|w| w.anack().bit(true).dnack().bit(true).overrun().bit(true));
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}
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/// Get Error instance, if any occurred.
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fn read_errorsrc(&self) -> Result<(), Error> {
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let r = T::regs();
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let err = r.errorsrc.read();
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if err.anack().is_received() {
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return Err(Error::AddressNack);
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}
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if err.dnack().is_received() {
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return Err(Error::DataNack);
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}
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if err.overrun().is_received() {
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return Err(Error::DataNack);
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}
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Ok(())
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}
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/// Wait for stop or error
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fn wait(&mut self) {
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let r = T::regs();
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loop {
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if r.events_stopped.read().bits() != 0 {
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r.events_stopped.reset();
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break;
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}
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if r.events_error.read().bits() != 0 {
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r.events_error.reset();
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r.tasks_stop.write(|w| unsafe { w.bits(1) });
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}
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}
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}
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/// Write to an I2C slave.
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///
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/// The buffer must have a length of at most 255 bytes on the nRF52832
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/// and at most 65535 bytes on the nRF52840.
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pub fn write(&mut self, address: u8, buffer: &[u8]) -> Result<(), Error> {
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let r = T::regs();
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// Conservative compiler fence to prevent optimizations that do not
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// take in to account actions by DMA. The fence has been placed here,
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// before any DMA action has started.
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compiler_fence(SeqCst);
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r.address.write(|w| unsafe { w.address().bits(address) });
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// Set up the DMA write.
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unsafe { self.set_tx_buffer(buffer)? };
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// Clear events
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r.events_stopped.reset();
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r.events_error.reset();
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r.events_lasttx.reset();
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self.clear_errorsrc();
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// Start write operation.
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r.shorts.write(|w| w.lasttx_stop().enabled());
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r.tasks_starttx.write(|w|
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// `1` is a valid value to write to task registers.
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unsafe { w.bits(1) });
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self.wait();
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// Conservative compiler fence to prevent optimizations that do not
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// take in to account actions by DMA. The fence has been placed here,
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// after all possible DMA actions have completed.
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compiler_fence(SeqCst);
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self.read_errorsrc()?;
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if r.txd.amount.read().bits() != buffer.len() as u32 {
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return Err(Error::Transmit);
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}
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Ok(())
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}
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/// Read from an I2C slave.
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///
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/// The buffer must have a length of at most 255 bytes on the nRF52832
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/// and at most 65535 bytes on the nRF52840.
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pub fn read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), Error> {
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let r = T::regs();
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// Conservative compiler fence to prevent optimizations that do not
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// take in to account actions by DMA. The fence has been placed here,
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// before any DMA action has started.
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compiler_fence(SeqCst);
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r.address.write(|w| unsafe { w.address().bits(address) });
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// Set up the DMA read.
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unsafe { self.set_rx_buffer(buffer)? };
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// Clear events
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r.events_stopped.reset();
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r.events_error.reset();
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self.clear_errorsrc();
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// Start read operation.
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r.shorts.write(|w| w.lastrx_stop().enabled());
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r.tasks_startrx.write(|w|
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// `1` is a valid value to write to task registers.
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unsafe { w.bits(1) });
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self.wait();
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// Conservative compiler fence to prevent optimizations that do not
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// take in to account actions by DMA. The fence has been placed here,
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// after all possible DMA actions have completed.
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compiler_fence(SeqCst);
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self.read_errorsrc()?;
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if r.rxd.amount.read().bits() != buffer.len() as u32 {
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return Err(Error::Receive);
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}
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Ok(())
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}
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/// Write data to an I2C slave, then read data from the slave without
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/// triggering a stop condition between the two.
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///
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/// The buffers must have a length of at most 255 bytes on the nRF52832
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/// and at most 65535 bytes on the nRF52840.
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pub fn write_then_read(
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&mut self,
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address: u8,
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wr_buffer: &[u8],
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rd_buffer: &mut [u8],
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) -> Result<(), Error> {
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let r = T::regs();
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// Conservative compiler fence to prevent optimizations that do not
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// take in to account actions by DMA. The fence has been placed here,
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// before any DMA action has started.
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compiler_fence(SeqCst);
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r.address.write(|w| unsafe { w.address().bits(address) });
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// Set up DMA buffers.
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unsafe {
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self.set_tx_buffer(wr_buffer)?;
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self.set_rx_buffer(rd_buffer)?;
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}
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// Clear events
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r.events_stopped.reset();
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r.events_error.reset();
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self.clear_errorsrc();
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// Start write+read operation.
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r.shorts.write(|w| {
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w.lasttx_startrx().enabled();
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w.lastrx_stop().enabled();
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w
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});
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// `1` is a valid value to write to task registers.
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r.tasks_starttx.write(|w| unsafe { w.bits(1) });
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self.wait();
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// Conservative compiler fence to prevent optimizations that do not
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// take in to account actions by DMA. The fence has been placed here,
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// after all possible DMA actions have completed.
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compiler_fence(SeqCst);
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self.read_errorsrc()?;
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let bad_write = r.txd.amount.read().bits() != wr_buffer.len() as u32;
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let bad_read = r.rxd.amount.read().bits() != rd_buffer.len() as u32;
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if bad_write {
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return Err(Error::Transmit);
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}
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if bad_read {
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return Err(Error::Receive);
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}
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Ok(())
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}
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/// Copy data into RAM and write to an I2C slave.
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///
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/// The write buffer must have a length of at most 255 bytes on the nRF52832
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/// and at most 1024 bytes on the nRF52840.
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pub fn copy_write(&mut self, address: u8, wr_buffer: &[u8]) -> Result<(), Error> {
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if wr_buffer.len() > FORCE_COPY_BUFFER_SIZE {
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return Err(Error::TxBufferTooLong);
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}
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// Copy to RAM
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let wr_ram_buffer = &mut [0; FORCE_COPY_BUFFER_SIZE][..wr_buffer.len()];
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wr_ram_buffer.copy_from_slice(wr_buffer);
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self.write(address, wr_ram_buffer)
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}
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/// Copy data into RAM and write to an I2C slave, then read data from the slave without
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/// triggering a stop condition between the two.
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///
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/// The write buffer must have a length of at most 255 bytes on the nRF52832
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/// and at most 1024 bytes on the nRF52840.
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///
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/// The read buffer must have a length of at most 255 bytes on the nRF52832
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/// and at most 65535 bytes on the nRF52840.
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pub fn copy_write_then_read(
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&mut self,
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address: u8,
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wr_buffer: &[u8],
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rd_buffer: &mut [u8],
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) -> Result<(), Error> {
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if wr_buffer.len() > FORCE_COPY_BUFFER_SIZE {
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return Err(Error::TxBufferTooLong);
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}
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// Copy to RAM
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let wr_ram_buffer = &mut [0; FORCE_COPY_BUFFER_SIZE][..wr_buffer.len()];
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wr_ram_buffer.copy_from_slice(wr_buffer);
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self.write_then_read(address, wr_ram_buffer, rd_buffer)
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}
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fn wait_for_stopped_event(cx: &mut core::task::Context) -> Poll<()> {
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let r = T::regs();
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let s = T::state();
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s.end_waker.register(cx.waker());
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if r.events_stopped.read().bits() != 0 {
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r.events_stopped.reset();
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return Poll::Ready(());
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}
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// stop if an error occured
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if r.events_error.read().bits() != 0 {
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r.events_error.reset();
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r.tasks_stop.write(|w| unsafe { w.bits(1) });
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}
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Poll::Pending
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}
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}
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impl<'a, T: Instance> Drop for Twim<'a, T> {
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fn drop(&mut self) {
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info!("twim drop");
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// TODO when implementing async here, check for abort
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// disable!
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let r = T::regs();
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r.enable.write(|w| w.enable().disabled());
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gpio::deconfigure_pin(r.psel.sda.read().bits());
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gpio::deconfigure_pin(r.psel.scl.read().bits());
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info!("twim drop: done");
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}
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}
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impl<'d, T> I2c for Twim<'d, T>
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where
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T: Instance,
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{
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type Error = Error;
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|
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#[rustfmt::skip]
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type WriteFuture<'a> where Self: 'a = impl Future<Output = Result<(), Self::Error>> + 'a;
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#[rustfmt::skip]
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type ReadFuture<'a> where Self: 'a = impl Future<Output = Result<(), Self::Error>> + 'a;
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#[rustfmt::skip]
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type WriteReadFuture<'a> where Self: 'a = impl Future<Output = Result<(), Self::Error>> + 'a;
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fn read<'a>(&'a mut self, address: u8, buffer: &'a mut [u8]) -> Self::ReadFuture<'a> {
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async move {
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// NOTE: RAM slice check for buffer is not necessary, as a mutable
|
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// slice can only be built from data located in RAM.
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let r = T::regs();
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// Conservative compiler fence to prevent optimizations that do not
|
|
// take in to account actions by DMA. The fence has been placed here,
|
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// before any DMA action has started.
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compiler_fence(SeqCst);
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r.address.write(|w| unsafe { w.address().bits(address) });
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// Set up the DMA read.
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unsafe { self.set_rx_buffer(buffer)? };
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// Reset events
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r.events_stopped.reset();
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r.events_error.reset();
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self.clear_errorsrc();
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// Enable events
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r.intenset.write(|w| w.stopped().set().error().set());
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// Start read operation.
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r.shorts.write(|w| w.lastrx_stop().enabled());
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r.tasks_startrx.write(|w|
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// `1` is a valid value to write to task registers.
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unsafe { w.bits(1) });
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// Conservative compiler fence to prevent optimizations that do not
|
|
// take in to account actions by DMA. The fence has been placed here,
|
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// after all possible DMA actions have completed.
|
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compiler_fence(SeqCst);
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// Wait for 'stopped' event.
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poll_fn(Self::wait_for_stopped_event).await;
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self.read_errorsrc()?;
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if r.rxd.amount.read().bits() != buffer.len() as u32 {
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return Err(Error::Receive);
|
|
}
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Ok(())
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}
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}
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|
|
fn write<'a>(&'a mut self, address: u8, bytes: &'a [u8]) -> Self::WriteFuture<'a> {
|
|
async move {
|
|
slice_in_ram_or(bytes, Error::DMABufferNotInDataMemory)?;
|
|
|
|
// Conservative compiler fence to prevent optimizations that do not
|
|
// take in to account actions by DMA. The fence has been placed here,
|
|
// before any DMA action has started.
|
|
compiler_fence(SeqCst);
|
|
|
|
let r = T::regs();
|
|
|
|
// Set up current address we're trying to talk to
|
|
r.address.write(|w| unsafe { w.address().bits(address) });
|
|
|
|
// Set up DMA write.
|
|
unsafe {
|
|
self.set_tx_buffer(bytes)?;
|
|
}
|
|
|
|
// Reset events
|
|
r.events_stopped.reset();
|
|
r.events_error.reset();
|
|
r.events_lasttx.reset();
|
|
self.clear_errorsrc();
|
|
|
|
// Enable events
|
|
r.intenset.write(|w| w.stopped().set().error().set());
|
|
|
|
// Start write operation.
|
|
r.shorts.write(|w| w.lasttx_stop().enabled());
|
|
r.tasks_starttx.write(|w|
|
|
// `1` is a valid value to write to task registers.
|
|
unsafe { w.bits(1) });
|
|
|
|
// Conservative compiler fence to prevent optimizations that do not
|
|
// take in to account actions by DMA. The fence has been placed here,
|
|
// after all possible DMA actions have completed.
|
|
compiler_fence(SeqCst);
|
|
|
|
// Wait for 'stopped' event.
|
|
poll_fn(Self::wait_for_stopped_event).await;
|
|
|
|
self.read_errorsrc()?;
|
|
|
|
if r.txd.amount.read().bits() != bytes.len() as u32 {
|
|
return Err(Error::Transmit);
|
|
}
|
|
|
|
Ok(())
|
|
}
|
|
}
|
|
|
|
fn write_read<'a>(
|
|
&'a mut self,
|
|
address: u8,
|
|
bytes: &'a [u8],
|
|
buffer: &'a mut [u8],
|
|
) -> Self::WriteReadFuture<'a> {
|
|
async move {
|
|
slice_in_ram_or(bytes, Error::DMABufferNotInDataMemory)?;
|
|
// NOTE: RAM slice check for buffer is not necessary, as a mutable
|
|
// slice can only be built from data located in RAM.
|
|
|
|
// Conservative compiler fence to prevent optimizations that do not
|
|
// take in to account actions by DMA. The fence has been placed here,
|
|
// before any DMA action has started.
|
|
compiler_fence(SeqCst);
|
|
|
|
let r = T::regs();
|
|
|
|
// Set up current address we're trying to talk to
|
|
r.address.write(|w| unsafe { w.address().bits(address) });
|
|
|
|
// Set up DMA buffers.
|
|
unsafe {
|
|
self.set_tx_buffer(bytes)?;
|
|
self.set_rx_buffer(buffer)?;
|
|
}
|
|
|
|
// Reset events
|
|
r.events_stopped.reset();
|
|
r.events_error.reset();
|
|
r.events_lasttx.reset();
|
|
self.clear_errorsrc();
|
|
|
|
// Enable events
|
|
r.intenset.write(|w| w.stopped().set().error().set());
|
|
|
|
// Start write+read operation.
|
|
r.shorts.write(|w| {
|
|
w.lasttx_startrx().enabled();
|
|
w.lastrx_stop().enabled();
|
|
w
|
|
});
|
|
// `1` is a valid value to write to task registers.
|
|
r.tasks_starttx.write(|w| unsafe { w.bits(1) });
|
|
|
|
// Conservative compiler fence to prevent optimizations that do not
|
|
// take in to account actions by DMA. The fence has been placed here,
|
|
// after all possible DMA actions have completed.
|
|
compiler_fence(SeqCst);
|
|
|
|
// Wait for 'stopped' event.
|
|
poll_fn(Self::wait_for_stopped_event).await;
|
|
|
|
self.read_errorsrc()?;
|
|
|
|
let bad_write = r.txd.amount.read().bits() != bytes.len() as u32;
|
|
let bad_read = r.rxd.amount.read().bits() != buffer.len() as u32;
|
|
|
|
if bad_write {
|
|
return Err(Error::Transmit);
|
|
}
|
|
|
|
if bad_read {
|
|
return Err(Error::Receive);
|
|
}
|
|
|
|
Ok(())
|
|
}
|
|
}
|
|
}
|
|
|
|
impl<'a, T: Instance> embedded_hal::blocking::i2c::Write for Twim<'a, T> {
|
|
type Error = Error;
|
|
|
|
fn write<'w>(&mut self, addr: u8, bytes: &'w [u8]) -> Result<(), Error> {
|
|
if slice_in_ram(bytes) {
|
|
self.write(addr, bytes)
|
|
} else {
|
|
let buf = &mut [0; FORCE_COPY_BUFFER_SIZE][..];
|
|
for chunk in bytes.chunks(FORCE_COPY_BUFFER_SIZE) {
|
|
buf[..chunk.len()].copy_from_slice(chunk);
|
|
self.write(addr, &buf[..chunk.len()])?;
|
|
}
|
|
Ok(())
|
|
}
|
|
}
|
|
}
|
|
|
|
impl<'a, T: Instance> embedded_hal::blocking::i2c::Read for Twim<'a, T> {
|
|
type Error = Error;
|
|
|
|
fn read<'w>(&mut self, addr: u8, bytes: &'w mut [u8]) -> Result<(), Error> {
|
|
self.read(addr, bytes)
|
|
}
|
|
}
|
|
|
|
impl<'a, T: Instance> embedded_hal::blocking::i2c::WriteRead for Twim<'a, T> {
|
|
type Error = Error;
|
|
|
|
fn write_read<'w>(
|
|
&mut self,
|
|
addr: u8,
|
|
bytes: &'w [u8],
|
|
buffer: &'w mut [u8],
|
|
) -> Result<(), Error> {
|
|
if slice_in_ram(bytes) {
|
|
self.write_then_read(addr, bytes, buffer)
|
|
} else {
|
|
self.copy_write_then_read(addr, bytes, buffer)
|
|
}
|
|
}
|
|
}
|
|
|
|
#[derive(Debug, Copy, Clone, Eq, PartialEq)]
|
|
pub enum Error {
|
|
TxBufferTooLong,
|
|
RxBufferTooLong,
|
|
TxBufferZeroLength,
|
|
RxBufferZeroLength,
|
|
Transmit,
|
|
Receive,
|
|
DMABufferNotInDataMemory,
|
|
AddressNack,
|
|
DataNack,
|
|
Overrun,
|
|
}
|
|
|
|
pub(crate) mod sealed {
|
|
use super::*;
|
|
|
|
pub struct State {
|
|
pub end_waker: AtomicWaker,
|
|
}
|
|
|
|
impl State {
|
|
pub const fn new() -> Self {
|
|
Self {
|
|
end_waker: AtomicWaker::new(),
|
|
}
|
|
}
|
|
}
|
|
|
|
pub trait Instance {
|
|
fn regs() -> &'static pac::twim0::RegisterBlock;
|
|
fn state() -> &'static State;
|
|
}
|
|
}
|
|
|
|
pub trait Instance: Unborrow<Target = Self> + sealed::Instance + 'static {
|
|
type Interrupt: Interrupt;
|
|
}
|
|
|
|
macro_rules! impl_twim {
|
|
($type:ident, $pac_type:ident, $irq:ident) => {
|
|
impl crate::twim::sealed::Instance for peripherals::$type {
|
|
fn regs() -> &'static pac::twim0::RegisterBlock {
|
|
unsafe { &*pac::$pac_type::ptr() }
|
|
}
|
|
fn state() -> &'static crate::twim::sealed::State {
|
|
static STATE: crate::twim::sealed::State = crate::twim::sealed::State::new();
|
|
&STATE
|
|
}
|
|
}
|
|
impl crate::twim::Instance for peripherals::$type {
|
|
type Interrupt = crate::interrupt::$irq;
|
|
}
|
|
};
|
|
}
|