7598b8a40f
Sequences are now passed in via the start method to avoid having to stop the PWM and restart it. Sequences continue to be constrained with the same lifetime of the Pwm object itself. The pwm_sequence example has been extended to illustrate multiple sequences being passed around.
663 lines
20 KiB
Rust
663 lines
20 KiB
Rust
#![macro_use]
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use core::marker::PhantomData;
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use core::sync::atomic::{compiler_fence, Ordering};
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use embassy::util::Unborrow;
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use embassy_hal_common::unborrow;
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use crate::gpio::sealed::Pin as _;
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use crate::gpio::{AnyPin, OptionalPin as GpioOptionalPin};
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use crate::interrupt::Interrupt;
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use crate::pac;
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use crate::ppi::{Event, Task};
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use crate::util::slice_in_ram_or;
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/// SimplePwm is the traditional pwm interface you're probably used to, allowing
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/// to simply set a duty cycle across up to four channels.
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pub struct SimplePwm<'d, T: Instance> {
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phantom: PhantomData<&'d mut T>,
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duty: [u16; 4],
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ch0: Option<AnyPin>,
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ch1: Option<AnyPin>,
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ch2: Option<AnyPin>,
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ch3: Option<AnyPin>,
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}
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/// SequencePwm allows you to offload the updating of a sequence of duty cycles
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/// to up to four channels, as well as repeat that sequence n times.
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pub struct SequencePwm<'d, T: Instance> {
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phantom: PhantomData<&'d mut T>,
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ch0: Option<AnyPin>,
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ch1: Option<AnyPin>,
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ch2: Option<AnyPin>,
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ch3: Option<AnyPin>,
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}
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#[derive(Debug, Clone, Copy, PartialEq, Eq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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#[non_exhaustive]
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pub enum Error {
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/// Max Sequence size is 32767
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SequenceTooLong,
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/// Min Sequence count is 1
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SequenceTimesAtLeastOne,
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/// EasyDMA can only read from data memory, read only buffers in flash will fail.
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DMABufferNotInDataMemory,
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}
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impl<'d, T: Instance> SequencePwm<'d, T> {
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/// Creates the interface to a `SequencePwm`.
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///
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/// Must be started by calling `start`
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///
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/// # Safety
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///
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/// The returned API is safe unless you use `mem::forget` (or similar safe
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/// mechanisms) on stack allocated buffers which which have been passed to
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/// [`new()`](SequencePwm::new).
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#[allow(unused_unsafe)]
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pub fn new(
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_pwm: impl Unborrow<Target = T> + 'd,
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ch0: impl Unborrow<Target = impl GpioOptionalPin> + 'd,
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ch1: impl Unborrow<Target = impl GpioOptionalPin> + 'd,
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ch2: impl Unborrow<Target = impl GpioOptionalPin> + 'd,
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ch3: impl Unborrow<Target = impl GpioOptionalPin> + 'd,
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config: SequenceConfig,
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) -> Result<Self, Error> {
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unborrow!(ch0, ch1, ch2, ch3);
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let r = T::regs();
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if let Some(pin) = ch0.pin_mut() {
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pin.set_low();
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pin.conf().write(|w| w.dir().output());
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}
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if let Some(pin) = ch1.pin_mut() {
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pin.set_low();
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pin.conf().write(|w| w.dir().output());
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}
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if let Some(pin) = ch2.pin_mut() {
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pin.set_low();
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pin.conf().write(|w| w.dir().output());
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}
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if let Some(pin) = ch3.pin_mut() {
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pin.set_low();
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pin.conf().write(|w| w.dir().output());
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}
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// if NoPin provided writes disconnected (top bit 1) 0x80000000 else
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// writes pin number ex 13 (0x0D) which is connected (top bit 0)
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r.psel.out[0].write(|w| unsafe { w.bits(ch0.psel_bits()) });
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r.psel.out[1].write(|w| unsafe { w.bits(ch1.psel_bits()) });
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r.psel.out[2].write(|w| unsafe { w.bits(ch2.psel_bits()) });
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r.psel.out[3].write(|w| unsafe { w.bits(ch3.psel_bits()) });
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// Disable all interrupts
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r.intenclr.write(|w| unsafe { w.bits(0xFFFF_FFFF) });
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r.shorts.reset();
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r.events_stopped.reset();
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r.events_loopsdone.reset();
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r.events_seqend[0].reset();
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r.events_seqend[1].reset();
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r.events_pwmperiodend.reset();
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r.events_seqstarted[0].reset();
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r.events_seqstarted[1].reset();
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r.decoder.write(|w| {
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w.load().bits(config.sequence_load as u8);
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w.mode().refresh_count()
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});
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r.mode.write(|w| match config.counter_mode {
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CounterMode::UpAndDown => w.updown().up_and_down(),
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CounterMode::Up => w.updown().up(),
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});
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r.prescaler
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.write(|w| w.prescaler().bits(config.prescaler as u8));
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r.countertop
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.write(|w| unsafe { w.countertop().bits(config.max_duty) });
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r.seq0.refresh.write(|w| unsafe { w.bits(config.refresh) });
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r.seq0
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.enddelay
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.write(|w| unsafe { w.bits(config.end_delay) });
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r.seq1.refresh.write(|w| unsafe { w.bits(config.refresh) });
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r.seq1
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.enddelay
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.write(|w| unsafe { w.bits(config.end_delay) });
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Ok(Self {
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phantom: PhantomData,
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ch0: ch0.degrade_optional(),
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ch1: ch1.degrade_optional(),
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ch2: ch2.degrade_optional(),
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ch3: ch3.degrade_optional(),
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})
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}
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/// Start or restart playback
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#[inline(always)]
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pub fn start(&self, sequence: &'d [u16], times: SequenceMode) -> Result<(), Error> {
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slice_in_ram_or(sequence, Error::DMABufferNotInDataMemory)?;
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if sequence.len() > 32767 {
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return Err(Error::SequenceTooLong);
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}
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if let SequenceMode::Times(0) = times {
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return Err(Error::SequenceTimesAtLeastOne);
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}
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let r = T::regs();
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r.seq0
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.ptr
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.write(|w| unsafe { w.bits(sequence.as_ptr() as u32) });
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r.seq0
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.cnt
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.write(|w| unsafe { w.bits(sequence.len() as u32) });
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r.seq1
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.ptr
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.write(|w| unsafe { w.bits(sequence.as_ptr() as u32) });
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r.seq1
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.cnt
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.write(|w| unsafe { w.bits(sequence.len() as u32) });
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self.stop();
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r.enable.write(|w| w.enable().enabled());
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// defensive before seqstart
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compiler_fence(Ordering::SeqCst);
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match times {
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// just the one time, no loop count
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SequenceMode::Times(1) => {
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r.loop_.write(|w| w.cnt().disabled());
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// tasks_seqstart() doesn't exist in all svds so write its bit instead
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r.tasks_seqstart[0].write(|w| unsafe { w.bits(0x01) });
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}
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// loop count is how many times to play BOTH sequences
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// 2 total (1 x 2)
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// 3 total, (2 x 2) - 1
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SequenceMode::Times(n) => {
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let odd = n & 1 == 1;
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let times = if odd { (n / 2) + 1 } else { n / 2 };
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r.loop_.write(|w| unsafe { w.cnt().bits(times) });
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// we can subtract 1 by starting at seq1 instead of seq0
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if odd {
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// tasks_seqstart() doesn't exist in all svds so write its bit instead
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r.tasks_seqstart[1].write(|w| unsafe { w.bits(0x01) });
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} else {
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// tasks_seqstart() doesn't exist in all svds so write its bit instead
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r.tasks_seqstart[0].write(|w| unsafe { w.bits(0x01) });
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}
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}
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// to play infinitely, repeat the sequence one time, then have loops done self trigger seq0 again
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SequenceMode::Infinite => {
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r.loop_.write(|w| unsafe { w.cnt().bits(0x1) });
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r.shorts.write(|w| w.loopsdone_seqstart0().enabled());
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// tasks_seqstart() doesn't exist in all svds so write its bit instead
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r.tasks_seqstart[0].write(|w| unsafe { w.bits(0x01) });
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}
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}
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Ok(())
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}
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/// Returns reference to `Stopped` event endpoint for PPI.
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#[inline(always)]
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pub fn event_stopped(&self) -> Event {
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let r = T::regs();
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Event::from_reg(&r.events_stopped)
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}
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/// Returns reference to `LoopsDone` event endpoint for PPI.
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#[inline(always)]
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pub fn event_loops_done(&self) -> Event {
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let r = T::regs();
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Event::from_reg(&r.events_loopsdone)
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}
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/// Returns reference to `PwmPeriodEnd` event endpoint for PPI.
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#[inline(always)]
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pub fn event_pwm_period_end(&self) -> Event {
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let r = T::regs();
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Event::from_reg(&r.events_pwmperiodend)
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}
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/// Returns reference to `Seq0 End` event endpoint for PPI.
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#[inline(always)]
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pub fn event_seq_end(&self) -> Event {
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let r = T::regs();
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Event::from_reg(&r.events_seqend[0])
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}
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/// Returns reference to `Seq1 End` event endpoint for PPI.
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#[inline(always)]
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pub fn event_seq1_end(&self) -> Event {
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let r = T::regs();
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Event::from_reg(&r.events_seqend[1])
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}
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/// Returns reference to `Seq0 Started` event endpoint for PPI.
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#[inline(always)]
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pub fn event_seq0_started(&self) -> Event {
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let r = T::regs();
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Event::from_reg(&r.events_seqstarted[0])
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}
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/// Returns reference to `Seq1 Started` event endpoint for PPI.
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#[inline(always)]
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pub fn event_seq1_started(&self) -> Event {
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let r = T::regs();
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Event::from_reg(&r.events_seqstarted[1])
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}
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/// Returns reference to `Seq0 Start` task endpoint for PPI.
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/// # Safety
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///
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/// Interacting with the sequence while it runs puts it in an unknown state
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#[inline(always)]
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pub unsafe fn task_start_seq0(&self) -> Task {
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let r = T::regs();
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Task::from_reg(&r.tasks_seqstart[0])
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}
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/// Returns reference to `Seq1 Started` task endpoint for PPI.
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/// # Safety
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///
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/// Interacting with the sequence while it runs puts it in an unknown state
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#[inline(always)]
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pub unsafe fn task_start_seq1(&self) -> Task {
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let r = T::regs();
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Task::from_reg(&r.tasks_seqstart[1])
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}
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/// Returns reference to `NextStep` task endpoint for PPI.
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/// # Safety
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///
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/// Interacting with the sequence while it runs puts it in an unknown state
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#[inline(always)]
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pub unsafe fn task_next_step(&self) -> Task {
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let r = T::regs();
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Task::from_reg(&r.tasks_nextstep)
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}
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/// Returns reference to `Stop` task endpoint for PPI.
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/// # Safety
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///
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/// Interacting with the sequence while it runs puts it in an unknown state
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#[inline(always)]
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pub unsafe fn task_stop(&self) -> Task {
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let r = T::regs();
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Task::from_reg(&r.tasks_stop)
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}
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/// Stop playback. Disables the peripheral. Does NOT clear the last duty
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/// cycle from the pin.
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#[inline(always)]
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pub fn stop(&self) {
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let r = T::regs();
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r.shorts.reset();
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compiler_fence(Ordering::SeqCst);
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// tasks_stop() doesn't exist in all svds so write its bit instead
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r.tasks_stop.write(|w| unsafe { w.bits(0x01) });
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r.enable.write(|w| w.enable().disabled());
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}
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}
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impl<'a, T: Instance> Drop for SequencePwm<'a, T> {
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fn drop(&mut self) {
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let r = T::regs();
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self.stop();
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if let Some(pin) = &self.ch0 {
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pin.set_low();
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pin.conf().reset();
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r.psel.out[0].reset();
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}
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if let Some(pin) = &self.ch1 {
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pin.set_low();
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pin.conf().reset();
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r.psel.out[1].reset();
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}
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if let Some(pin) = &self.ch2 {
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pin.set_low();
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pin.conf().reset();
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r.psel.out[2].reset();
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}
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if let Some(pin) = &self.ch3 {
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pin.set_low();
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pin.conf().reset();
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r.psel.out[3].reset();
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}
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}
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}
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/// Configure an infinite looping sequence for `SequencePwm`
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#[non_exhaustive]
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pub struct SequenceConfig {
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/// Selects up mode or up-and-down mode for the counter
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pub counter_mode: CounterMode,
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/// Top value to be compared against buffer values
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pub max_duty: u16,
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/// Configuration for PWM_CLK
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pub prescaler: Prescaler,
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/// How a sequence is read from RAM and is spread to the compare register
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pub sequence_load: SequenceLoad,
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/// Number of PWM periods to delay between each sequence sample
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pub refresh: u32,
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/// Number of PWM periods after the sequence ends before starting the next sequence
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pub end_delay: u32,
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}
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impl Default for SequenceConfig {
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fn default() -> SequenceConfig {
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SequenceConfig {
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counter_mode: CounterMode::Up,
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max_duty: 1000,
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prescaler: Prescaler::Div16,
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sequence_load: SequenceLoad::Common,
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refresh: 0,
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end_delay: 0,
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}
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}
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}
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/// How many times to run the sequence
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#[derive(Debug, Eq, PartialEq, Clone, Copy)]
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pub enum SequenceMode {
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/// Run sequence n Times total
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Times(u16),
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/// Repeat until `stop` is called.
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Infinite,
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}
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/// PWM Base clock is system clock (16MHz) divided by prescaler
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#[derive(Debug, Eq, PartialEq, Clone, Copy)]
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pub enum Prescaler {
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Div1,
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Div2,
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Div4,
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Div8,
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Div16,
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Div32,
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Div64,
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Div128,
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}
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/// How the sequence values are distributed across the channels
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#[derive(Debug, Eq, PartialEq, Clone, Copy)]
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pub enum SequenceLoad {
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/// Provided sequence will be used across all channels
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Common,
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/// Provided sequence contains grouped values for each channel ex:
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/// [ch0_0_and_ch1_0, ch2_0_and_ch3_0, ... ch0_n_and_ch1_n, ch2_n_and_ch3_n]
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Grouped,
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/// Provided sequence contains individual values for each channel ex:
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/// [ch0_0, ch1_0, ch2_0, ch3_0... ch0_n, ch1_n, ch2_n, ch3_n]
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Individual,
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/// Similar to Individual mode, but only three channels are used. The fourth
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/// value is loaded into the pulse generator counter as its top value.
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Waveform,
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}
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/// Selects up mode or up-and-down mode for the counter
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#[derive(Debug, Eq, PartialEq, Clone, Copy)]
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pub enum CounterMode {
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/// Up counter (edge-aligned PWM duty cycle)
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Up,
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/// Up and down counter (center-aligned PWM duty cycle)
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UpAndDown,
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}
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impl<'d, T: Instance> SimplePwm<'d, T> {
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/// Creates the interface to a `SimplePwm`
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///
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/// Enables the peripheral, defaults the freq to 1Mhz, max_duty 1000, duty
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/// 0, up mode, and pins low. Must be started by calling `set_duty`
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///
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/// # Safety
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///
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/// The returned API is safe unless you use `mem::forget` (or similar safe
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/// mechanisms) on stack allocated buffers which which have been passed to
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/// [`new()`](SimplePwm::new).
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#[allow(unused_unsafe)]
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pub fn new(
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_pwm: impl Unborrow<Target = T> + 'd,
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ch0: impl Unborrow<Target = impl GpioOptionalPin> + 'd,
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ch1: impl Unborrow<Target = impl GpioOptionalPin> + 'd,
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ch2: impl Unborrow<Target = impl GpioOptionalPin> + 'd,
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ch3: impl Unborrow<Target = impl GpioOptionalPin> + 'd,
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) -> Self {
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unborrow!(ch0, ch1, ch2, ch3);
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let r = T::regs();
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if let Some(pin) = ch0.pin_mut() {
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pin.set_low();
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pin.conf().write(|w| w.dir().output());
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}
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if let Some(pin) = ch1.pin_mut() {
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pin.set_low();
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pin.conf().write(|w| w.dir().output());
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}
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if let Some(pin) = ch2.pin_mut() {
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pin.set_low();
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pin.conf().write(|w| w.dir().output());
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}
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if let Some(pin) = ch3.pin_mut() {
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pin.set_low();
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pin.conf().write(|w| w.dir().output());
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}
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// if NoPin provided writes disconnected (top bit 1) 0x80000000 else
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// writes pin number ex 13 (0x0D) which is connected (top bit 0)
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r.psel.out[0].write(|w| unsafe { w.bits(ch0.psel_bits()) });
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r.psel.out[1].write(|w| unsafe { w.bits(ch1.psel_bits()) });
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r.psel.out[2].write(|w| unsafe { w.bits(ch2.psel_bits()) });
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r.psel.out[3].write(|w| unsafe { w.bits(ch3.psel_bits()) });
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let pwm = Self {
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phantom: PhantomData,
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ch0: ch0.degrade_optional(),
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ch1: ch1.degrade_optional(),
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ch2: ch2.degrade_optional(),
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ch3: ch3.degrade_optional(),
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duty: [0; 4],
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};
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// Disable all interrupts
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r.intenclr.write(|w| unsafe { w.bits(0xFFFF_FFFF) });
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r.shorts.reset();
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// Enable
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r.enable.write(|w| w.enable().enabled());
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r.seq0
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.ptr
|
|
.write(|w| unsafe { w.bits((&pwm.duty).as_ptr() as u32) });
|
|
|
|
r.seq0.cnt.write(|w| unsafe { w.bits(4) });
|
|
r.seq0.refresh.write(|w| unsafe { w.bits(0) });
|
|
r.seq0.enddelay.write(|w| unsafe { w.bits(0) });
|
|
|
|
r.decoder.write(|w| {
|
|
w.load().individual();
|
|
w.mode().refresh_count()
|
|
});
|
|
r.mode.write(|w| w.updown().up());
|
|
r.prescaler.write(|w| w.prescaler().div_16());
|
|
r.countertop.write(|w| unsafe { w.countertop().bits(1000) });
|
|
r.loop_.write(|w| w.cnt().disabled());
|
|
|
|
pwm
|
|
}
|
|
|
|
/// Enables the PWM generator.
|
|
#[inline(always)]
|
|
pub fn enable(&self) {
|
|
let r = T::regs();
|
|
r.enable.write(|w| w.enable().enabled());
|
|
}
|
|
|
|
/// Disables the PWM generator. Does NOT clear the last duty cycle from the pin.
|
|
#[inline(always)]
|
|
pub fn disable(&self) {
|
|
let r = T::regs();
|
|
r.enable.write(|w| w.enable().disabled());
|
|
}
|
|
|
|
/// Sets duty cycle (15 bit) for a PWM channel.
|
|
pub fn set_duty(&mut self, channel: usize, duty: u16) {
|
|
let r = T::regs();
|
|
|
|
self.duty[channel] = duty & 0x7FFF;
|
|
|
|
// reload ptr in case self was moved
|
|
r.seq0
|
|
.ptr
|
|
.write(|w| unsafe { w.bits((&self.duty).as_ptr() as u32) });
|
|
|
|
// defensive before seqstart
|
|
compiler_fence(Ordering::SeqCst);
|
|
|
|
r.events_seqend[0].reset();
|
|
|
|
// tasks_seqstart() doesn't exist in all svds so write its bit instead
|
|
r.tasks_seqstart[0].write(|w| unsafe { w.bits(1) });
|
|
|
|
// defensive wait until waveform is loaded after seqstart so set_duty
|
|
// can't be called again while dma is still reading
|
|
while r.events_seqend[0].read().bits() == 0 {}
|
|
}
|
|
|
|
/// Sets the PWM clock prescaler.
|
|
#[inline(always)]
|
|
pub fn set_prescaler(&self, div: Prescaler) {
|
|
T::regs().prescaler.write(|w| w.prescaler().bits(div as u8));
|
|
}
|
|
|
|
/// Gets the PWM clock prescaler.
|
|
#[inline(always)]
|
|
pub fn prescaler(&self) -> Prescaler {
|
|
match T::regs().prescaler.read().prescaler().bits() {
|
|
0 => Prescaler::Div1,
|
|
1 => Prescaler::Div2,
|
|
2 => Prescaler::Div4,
|
|
3 => Prescaler::Div8,
|
|
4 => Prescaler::Div16,
|
|
5 => Prescaler::Div32,
|
|
6 => Prescaler::Div64,
|
|
7 => Prescaler::Div128,
|
|
_ => unreachable!(),
|
|
}
|
|
}
|
|
|
|
/// Sets the maximum duty cycle value.
|
|
#[inline(always)]
|
|
pub fn set_max_duty(&self, duty: u16) {
|
|
T::regs()
|
|
.countertop
|
|
.write(|w| unsafe { w.countertop().bits(duty.min(32767u16)) });
|
|
}
|
|
|
|
/// Returns the maximum duty cycle value.
|
|
#[inline(always)]
|
|
pub fn max_duty(&self) -> u16 {
|
|
T::regs().countertop.read().countertop().bits()
|
|
}
|
|
|
|
/// Sets the PWM output frequency.
|
|
#[inline(always)]
|
|
pub fn set_period(&self, freq: u32) {
|
|
let clk = 16_000_000u32 >> (self.prescaler() as u8);
|
|
let duty = clk / freq;
|
|
self.set_max_duty(duty.min(32767) as u16);
|
|
}
|
|
|
|
/// Returns the PWM output frequency.
|
|
#[inline(always)]
|
|
pub fn period(&self) -> u32 {
|
|
let clk = 16_000_000u32 >> (self.prescaler() as u8);
|
|
let max_duty = self.max_duty() as u32;
|
|
clk / max_duty
|
|
}
|
|
}
|
|
|
|
impl<'a, T: Instance> Drop for SimplePwm<'a, T> {
|
|
fn drop(&mut self) {
|
|
let r = T::regs();
|
|
|
|
self.disable();
|
|
|
|
if let Some(pin) = &self.ch0 {
|
|
pin.set_low();
|
|
pin.conf().reset();
|
|
r.psel.out[0].reset();
|
|
}
|
|
if let Some(pin) = &self.ch1 {
|
|
pin.set_low();
|
|
pin.conf().reset();
|
|
r.psel.out[1].reset();
|
|
}
|
|
if let Some(pin) = &self.ch2 {
|
|
pin.set_low();
|
|
pin.conf().reset();
|
|
r.psel.out[2].reset();
|
|
}
|
|
if let Some(pin) = &self.ch3 {
|
|
pin.set_low();
|
|
pin.conf().reset();
|
|
r.psel.out[3].reset();
|
|
}
|
|
}
|
|
}
|
|
|
|
pub(crate) mod sealed {
|
|
use super::*;
|
|
|
|
pub trait Instance {
|
|
fn regs() -> &'static pac::pwm0::RegisterBlock;
|
|
}
|
|
}
|
|
|
|
pub trait Instance: Unborrow<Target = Self> + sealed::Instance + 'static {
|
|
type Interrupt: Interrupt;
|
|
}
|
|
|
|
macro_rules! impl_pwm {
|
|
($type:ident, $pac_type:ident, $irq:ident) => {
|
|
impl crate::pwm::sealed::Instance for peripherals::$type {
|
|
fn regs() -> &'static pac::pwm0::RegisterBlock {
|
|
unsafe { &*pac::$pac_type::ptr() }
|
|
}
|
|
}
|
|
impl crate::pwm::Instance for peripherals::$type {
|
|
type Interrupt = crate::interrupt::$irq;
|
|
}
|
|
};
|
|
}
|