619 lines
17 KiB
Rust
619 lines
17 KiB
Rust
use stm32_metapac::flash::vals::Latency;
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use stm32_metapac::rcc::vals::{Adcsel, Hpre, Pllsrc, Ppre, Sw};
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use stm32_metapac::FLASH;
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pub use super::bus::{AHBPrescaler, APBPrescaler};
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use crate::pac::{PWR, RCC};
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use crate::rcc::sealed::RccPeripheral;
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use crate::rcc::{set_freqs, Clocks};
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use crate::time::Hertz;
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/// HSI speed
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pub const HSI_FREQ: Hertz = Hertz(16_000_000);
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/// LSI speed
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pub const LSI_FREQ: Hertz = Hertz(32_000);
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#[derive(Clone, Copy)]
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pub enum AdcClockSource {
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NoClk,
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SysClk,
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PllP,
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}
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impl AdcClockSource {
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pub fn adcsel(&self) -> Adcsel {
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match self {
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AdcClockSource::NoClk => Adcsel::NOCLK,
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AdcClockSource::SysClk => Adcsel::SYSCLK,
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AdcClockSource::PllP => Adcsel::PLLP,
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}
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}
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}
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impl Default for AdcClockSource {
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fn default() -> Self {
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Self::NoClk
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}
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}
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/// System clock mux source
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#[derive(Clone, Copy)]
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pub enum ClockSrc {
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HSE(Hertz),
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HSI16,
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PLL,
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}
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/// PLL clock input source
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#[derive(Clone, Copy, Debug)]
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pub enum PllSrc {
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HSI16,
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HSE(Hertz),
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}
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impl Into<Pllsrc> for PllSrc {
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fn into(self) -> Pllsrc {
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match self {
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PllSrc::HSE(..) => Pllsrc::HSE,
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PllSrc::HSI16 => Pllsrc::HSI16,
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}
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}
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}
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seq_macro::seq!(P in 2..=31 {
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/// Output divider for the PLL P output.
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#[derive(Clone, Copy)]
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pub enum PllP {
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// Note: If PLL P is set to 0 the PLLP bit controls the output division. There does not seem to
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// a good reason to do this so the API does not support it.
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// Div1 is invalid
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#(
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Div~P,
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)*
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}
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impl From<PllP> for u8 {
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/// Returns the register value for the P output divider.
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fn from(val: PllP) -> u8 {
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match val {
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#(
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PllP::Div~P => P,
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)*
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}
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}
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}
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});
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impl PllP {
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/// Returns the numeric value of the P output divider.
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pub fn to_div(self) -> u32 {
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let val: u8 = self.into();
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val as u32
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}
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}
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/// Output divider for the PLL Q output.
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#[derive(Clone, Copy)]
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pub enum PllQ {
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Div2,
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Div4,
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Div6,
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Div8,
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}
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impl PllQ {
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/// Returns the numeric value of the Q output divider.
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pub fn to_div(self) -> u32 {
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let val: u8 = self.into();
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(val as u32 + 1) * 2
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}
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}
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impl From<PllQ> for u8 {
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/// Returns the register value for the Q output divider.
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fn from(val: PllQ) -> u8 {
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match val {
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PllQ::Div2 => 0b00,
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PllQ::Div4 => 0b01,
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PllQ::Div6 => 0b10,
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PllQ::Div8 => 0b11,
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}
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}
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}
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/// Output divider for the PLL R output.
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#[derive(Clone, Copy)]
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pub enum PllR {
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Div2,
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Div4,
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Div6,
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Div8,
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}
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impl PllR {
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/// Returns the numeric value of the R output divider.
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pub fn to_div(self) -> u32 {
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let val: u8 = self.into();
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(val as u32 + 1) * 2
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}
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}
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impl From<PllR> for u8 {
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/// Returns the register value for the R output divider.
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fn from(val: PllR) -> u8 {
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match val {
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PllR::Div2 => 0b00,
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PllR::Div4 => 0b01,
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PllR::Div6 => 0b10,
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PllR::Div8 => 0b11,
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}
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}
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}
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seq_macro::seq!(N in 8..=127 {
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/// Multiplication factor for the PLL VCO input clock.
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#[derive(Clone, Copy)]
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pub enum PllN {
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#(
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Mul~N,
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)*
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}
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impl From<PllN> for u8 {
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/// Returns the register value for the N multiplication factor.
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fn from(val: PllN) -> u8 {
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match val {
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#(
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PllN::Mul~N => N,
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)*
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}
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}
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}
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impl PllN {
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/// Returns the numeric value of the N multiplication factor.
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pub fn to_mul(self) -> u32 {
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match self {
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#(
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PllN::Mul~N => N,
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)*
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}
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}
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}
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});
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/// PLL Pre-division. This must be set such that the PLL input is between 2.66 MHz and 16 MHz.
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#[derive(Copy, Clone)]
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pub enum PllM {
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Div1,
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Div2,
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Div3,
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Div4,
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Div5,
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Div6,
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Div7,
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Div8,
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Div9,
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Div10,
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Div11,
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Div12,
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Div13,
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Div14,
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Div15,
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Div16,
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}
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impl PllM {
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/// Returns the numeric value of the M pre-division.
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pub fn to_div(self) -> u32 {
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let val: u8 = self.into();
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val as u32 + 1
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}
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}
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impl From<PllM> for u8 {
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/// Returns the register value for the M pre-division.
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fn from(val: PllM) -> u8 {
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match val {
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PllM::Div1 => 0b0000,
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PllM::Div2 => 0b0001,
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PllM::Div3 => 0b0010,
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PllM::Div4 => 0b0011,
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PllM::Div5 => 0b0100,
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PllM::Div6 => 0b0101,
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PllM::Div7 => 0b0110,
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PllM::Div8 => 0b0111,
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PllM::Div9 => 0b1000,
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PllM::Div10 => 0b1001,
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PllM::Div11 => 0b1010,
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PllM::Div12 => 0b1011,
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PllM::Div13 => 0b1100,
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PllM::Div14 => 0b1101,
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PllM::Div15 => 0b1110,
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PllM::Div16 => 0b1111,
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}
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}
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}
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/// PLL Configuration
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///
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/// Use this struct to configure the PLL source, input frequency, multiplication factor, and output
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/// dividers. Be sure to keep check the datasheet for your specific part for the appropriate
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/// frequency ranges for each of these settings.
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pub struct Pll {
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/// PLL Source clock selection.
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pub source: PllSrc,
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/// PLL pre-divider
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pub prediv_m: PllM,
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/// PLL multiplication factor for VCO
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pub mul_n: PllN,
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/// PLL division factor for P clock (ADC Clock)
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pub div_p: Option<PllP>,
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/// PLL division factor for Q clock (USB, I2S23, SAI1, FDCAN, QSPI)
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pub div_q: Option<PllQ>,
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/// PLL division factor for R clock (SYSCLK)
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pub div_r: Option<PllR>,
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}
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impl AHBPrescaler {
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const fn div(self) -> u32 {
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match self {
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AHBPrescaler::NotDivided => 1,
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AHBPrescaler::Div2 => 2,
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AHBPrescaler::Div4 => 4,
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AHBPrescaler::Div8 => 8,
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AHBPrescaler::Div16 => 16,
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AHBPrescaler::Div64 => 64,
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AHBPrescaler::Div128 => 128,
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AHBPrescaler::Div256 => 256,
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AHBPrescaler::Div512 => 512,
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}
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}
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}
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impl APBPrescaler {
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const fn div(self) -> u32 {
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match self {
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APBPrescaler::NotDivided => 1,
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APBPrescaler::Div2 => 2,
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APBPrescaler::Div4 => 4,
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APBPrescaler::Div8 => 8,
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APBPrescaler::Div16 => 16,
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}
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}
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}
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impl Into<Ppre> for APBPrescaler {
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fn into(self) -> Ppre {
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match self {
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APBPrescaler::NotDivided => Ppre::DIV1,
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APBPrescaler::Div2 => Ppre::DIV2,
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APBPrescaler::Div4 => Ppre::DIV4,
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APBPrescaler::Div8 => Ppre::DIV8,
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APBPrescaler::Div16 => Ppre::DIV16,
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}
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}
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}
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impl Into<Hpre> for AHBPrescaler {
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fn into(self) -> Hpre {
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match self {
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AHBPrescaler::NotDivided => Hpre::DIV1,
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AHBPrescaler::Div2 => Hpre::DIV2,
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AHBPrescaler::Div4 => Hpre::DIV4,
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AHBPrescaler::Div8 => Hpre::DIV8,
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AHBPrescaler::Div16 => Hpre::DIV16,
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AHBPrescaler::Div64 => Hpre::DIV64,
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AHBPrescaler::Div128 => Hpre::DIV128,
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AHBPrescaler::Div256 => Hpre::DIV256,
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AHBPrescaler::Div512 => Hpre::DIV512,
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}
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}
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}
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/// Sets the source for the 48MHz clock to the USB and RNG peripherals.
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pub enum Clock48MhzSrc {
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/// Use the High Speed Internal Oscillator. For USB usage, the CRS must be used to calibrate the
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/// oscillator to comply with the USB specification for oscillator tolerance.
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Hsi48(Option<CrsConfig>),
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/// Use the PLLQ output. The PLL must be configured to output a 48MHz clock. For USB usage the
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/// PLL needs to be using the HSE source to comply with the USB specification for oscillator
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/// tolerance.
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PllQ,
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}
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/// Sets the sync source for the Clock Recovery System (CRS).
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pub enum CrsSyncSource {
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/// Use an external GPIO to sync the CRS.
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Gpio,
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/// Use the Low Speed External oscillator to sync the CRS.
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Lse,
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/// Use the USB SOF to sync the CRS.
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Usb,
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}
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/// Clocks configutation
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pub struct Config {
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pub mux: ClockSrc,
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pub ahb_pre: AHBPrescaler,
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pub apb1_pre: APBPrescaler,
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pub apb2_pre: APBPrescaler,
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pub low_power_run: bool,
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/// Iff PLL is requested as the main clock source in the `mux` field then the PLL configuration
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/// MUST turn on the PLLR output.
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pub pll: Option<Pll>,
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/// Sets the clock source for the 48MHz clock used by the USB and RNG peripherals.
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pub clock_48mhz_src: Option<Clock48MhzSrc>,
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pub adc12_clock_source: AdcClockSource,
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pub adc345_clock_source: AdcClockSource,
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}
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/// Configuration for the Clock Recovery System (CRS) used to trim the HSI48 oscillator.
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pub struct CrsConfig {
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/// Sync source for the CRS.
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pub sync_src: CrsSyncSource,
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}
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impl Default for Config {
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#[inline]
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fn default() -> Config {
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Config {
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mux: ClockSrc::HSI16,
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ahb_pre: AHBPrescaler::NotDivided,
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apb1_pre: APBPrescaler::NotDivided,
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apb2_pre: APBPrescaler::NotDivided,
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low_power_run: false,
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pll: None,
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clock_48mhz_src: None,
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adc12_clock_source: Default::default(),
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adc345_clock_source: Default::default(),
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}
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}
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}
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pub struct PllFreq {
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pub pll_p: Option<Hertz>,
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pub pll_q: Option<Hertz>,
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pub pll_r: Option<Hertz>,
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}
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pub(crate) unsafe fn init(config: Config) {
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let pll_freq = config.pll.map(|pll_config| {
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let src_freq = match pll_config.source {
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PllSrc::HSI16 => {
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RCC.cr().write(|w| w.set_hsion(true));
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while !RCC.cr().read().hsirdy() {}
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HSI_FREQ.0
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}
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PllSrc::HSE(freq) => {
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RCC.cr().write(|w| w.set_hseon(true));
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while !RCC.cr().read().hserdy() {}
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freq.0
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}
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};
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// Disable PLL before configuration
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RCC.cr().modify(|w| w.set_pllon(false));
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while RCC.cr().read().pllrdy() {}
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let internal_freq = src_freq / pll_config.prediv_m.to_div() * pll_config.mul_n.to_mul();
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RCC.pllcfgr().write(|w| {
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w.set_plln(pll_config.mul_n.into());
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w.set_pllm(pll_config.prediv_m.into());
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w.set_pllsrc(pll_config.source.into());
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});
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let pll_p_freq = pll_config.div_p.map(|div_p| {
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RCC.pllcfgr().modify(|w| {
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w.set_pllpdiv(div_p.into());
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w.set_pllpen(true);
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});
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Hertz(internal_freq / div_p.to_div())
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});
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let pll_q_freq = pll_config.div_q.map(|div_q| {
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RCC.pllcfgr().modify(|w| {
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w.set_pllq(div_q.into());
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w.set_pllqen(true);
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});
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Hertz(internal_freq / div_q.to_div())
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});
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let pll_r_freq = pll_config.div_r.map(|div_r| {
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RCC.pllcfgr().modify(|w| {
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w.set_pllr(div_r.into());
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w.set_pllren(true);
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});
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Hertz(internal_freq / div_r.to_div())
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});
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// Enable the PLL
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RCC.cr().modify(|w| w.set_pllon(true));
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while !RCC.cr().read().pllrdy() {}
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PllFreq {
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pll_p: pll_p_freq,
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pll_q: pll_q_freq,
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pll_r: pll_r_freq,
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}
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});
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let (sys_clk, sw) = match config.mux {
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ClockSrc::HSI16 => {
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// Enable HSI16
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RCC.cr().write(|w| w.set_hsion(true));
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while !RCC.cr().read().hsirdy() {}
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(HSI_FREQ.0, Sw::HSI16)
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}
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ClockSrc::HSE(freq) => {
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// Enable HSE
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RCC.cr().write(|w| w.set_hseon(true));
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while !RCC.cr().read().hserdy() {}
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(freq.0, Sw::HSE)
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}
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ClockSrc::PLL => {
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assert!(pll_freq.is_some());
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assert!(pll_freq.as_ref().unwrap().pll_r.is_some());
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let freq = pll_freq.as_ref().unwrap().pll_r.unwrap().0;
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assert!(freq <= 170_000_000);
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if freq >= 150_000_000 {
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// Enable Core Boost mode on freq >= 150Mhz ([RM0440] p234)
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PWR.cr5().modify(|w| w.set_r1mode(false));
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// Set flash wait state in boost mode based on frequency ([RM0440] p191)
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if freq <= 36_000_000 {
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FLASH.acr().modify(|w| w.set_latency(Latency::WS0));
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} else if freq <= 68_000_000 {
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FLASH.acr().modify(|w| w.set_latency(Latency::WS1));
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} else if freq <= 102_000_000 {
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FLASH.acr().modify(|w| w.set_latency(Latency::WS2));
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} else if freq <= 136_000_000 {
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FLASH.acr().modify(|w| w.set_latency(Latency::WS3));
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} else {
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FLASH.acr().modify(|w| w.set_latency(Latency::WS4));
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}
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} else {
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PWR.cr5().modify(|w| w.set_r1mode(true));
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// Set flash wait state in normal mode based on frequency ([RM0440] p191)
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if freq <= 30_000_000 {
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FLASH.acr().modify(|w| w.set_latency(Latency::WS0));
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} else if freq <= 60_000_000 {
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FLASH.acr().modify(|w| w.set_latency(Latency::WS1));
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} else if freq <= 80_000_000 {
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FLASH.acr().modify(|w| w.set_latency(Latency::WS2));
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} else if freq <= 120_000_000 {
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FLASH.acr().modify(|w| w.set_latency(Latency::WS3));
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} else {
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FLASH.acr().modify(|w| w.set_latency(Latency::WS4));
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}
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}
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(freq, Sw::PLLRCLK)
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}
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};
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|
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RCC.cfgr().modify(|w| {
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w.set_sw(sw);
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w.set_hpre(config.ahb_pre.into());
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w.set_ppre1(config.apb1_pre.into());
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w.set_ppre2(config.apb2_pre.into());
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});
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|
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let ahb_freq: u32 = match config.ahb_pre {
|
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AHBPrescaler::NotDivided => sys_clk,
|
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pre => sys_clk / pre.div(),
|
|
};
|
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|
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let (apb1_freq, apb1_tim_freq) = match config.apb1_pre {
|
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APBPrescaler::NotDivided => (ahb_freq, ahb_freq),
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|
pre => {
|
|
let freq = ahb_freq / pre.div();
|
|
(freq, freq * 2)
|
|
}
|
|
};
|
|
|
|
let (apb2_freq, apb2_tim_freq) = match config.apb2_pre {
|
|
APBPrescaler::NotDivided => (ahb_freq, ahb_freq),
|
|
pre => {
|
|
let freq = ahb_freq / pre.div();
|
|
(freq, freq * 2)
|
|
}
|
|
};
|
|
|
|
// Setup the 48 MHz clock if needed
|
|
if let Some(clock_48mhz_src) = config.clock_48mhz_src {
|
|
let source = match clock_48mhz_src {
|
|
Clock48MhzSrc::PllQ => {
|
|
// Make sure the PLLQ is enabled and running at 48Mhz
|
|
let pllq_freq = pll_freq.as_ref().and_then(|f| f.pll_q);
|
|
assert!(pllq_freq.is_some() && pllq_freq.unwrap().0 == 48_000_000);
|
|
|
|
crate::pac::rcc::vals::Clk48sel::PLLQCLK
|
|
}
|
|
Clock48MhzSrc::Hsi48(crs_config) => {
|
|
// Enable HSI48
|
|
RCC.crrcr().modify(|w| w.set_hsi48on(true));
|
|
// Wait for HSI48 to turn on
|
|
while RCC.crrcr().read().hsi48rdy() == false {}
|
|
|
|
// Enable and setup CRS if needed
|
|
if let Some(crs_config) = crs_config {
|
|
crate::peripherals::CRS::enable();
|
|
|
|
let sync_src = match crs_config.sync_src {
|
|
CrsSyncSource::Gpio => crate::pac::crs::vals::Syncsrc::GPIO,
|
|
CrsSyncSource::Lse => crate::pac::crs::vals::Syncsrc::LSE,
|
|
CrsSyncSource::Usb => crate::pac::crs::vals::Syncsrc::USB,
|
|
};
|
|
|
|
crate::pac::CRS.cfgr().modify(|w| {
|
|
w.set_syncsrc(sync_src);
|
|
});
|
|
|
|
// These are the correct settings for standard USB operation. If other settings
|
|
// are needed there will need to be additional config options for the CRS.
|
|
crate::pac::CRS.cr().modify(|w| {
|
|
w.set_autotrimen(true);
|
|
w.set_cen(true);
|
|
});
|
|
}
|
|
crate::pac::rcc::vals::Clk48sel::HSI48
|
|
}
|
|
};
|
|
|
|
RCC.ccipr().modify(|w| w.set_clk48sel(source));
|
|
}
|
|
|
|
RCC.ccipr()
|
|
.modify(|w| w.set_adc12sel(config.adc12_clock_source.adcsel()));
|
|
RCC.ccipr()
|
|
.modify(|w| w.set_adc345sel(config.adc345_clock_source.adcsel()));
|
|
|
|
let adc12_ck = match config.adc12_clock_source {
|
|
AdcClockSource::NoClk => None,
|
|
AdcClockSource::PllP => match &pll_freq {
|
|
Some(pll) => pll.pll_p,
|
|
None => None,
|
|
},
|
|
AdcClockSource::SysClk => Some(Hertz(sys_clk)),
|
|
};
|
|
|
|
let adc345_ck = match config.adc345_clock_source {
|
|
AdcClockSource::NoClk => None,
|
|
AdcClockSource::PllP => match &pll_freq {
|
|
Some(pll) => pll.pll_p,
|
|
None => None,
|
|
},
|
|
AdcClockSource::SysClk => Some(Hertz(sys_clk)),
|
|
};
|
|
|
|
if config.low_power_run {
|
|
assert!(sys_clk <= 2_000_000);
|
|
PWR.cr1().modify(|w| w.set_lpr(true));
|
|
}
|
|
|
|
set_freqs(Clocks {
|
|
sys: Hertz(sys_clk),
|
|
ahb1: Hertz(ahb_freq),
|
|
ahb2: Hertz(ahb_freq),
|
|
apb1: Hertz(apb1_freq),
|
|
apb1_tim: Hertz(apb1_tim_freq),
|
|
apb2: Hertz(apb2_freq),
|
|
apb2_tim: Hertz(apb2_tim_freq),
|
|
adc: adc12_ck,
|
|
adc34: adc345_ck,
|
|
});
|
|
}
|