572 lines
17 KiB
Rust
572 lines
17 KiB
Rust
#![macro_use]
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use crate::dma::NoDma;
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use crate::gpio::{AnyPin, Pin};
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use crate::pac::gpio::vals::{Afr, Moder};
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use crate::pac::gpio::Gpio;
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use crate::pac::spi;
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use crate::spi::{
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ByteOrder, Config, Error, Instance, MisoPin, MosiPin, RxDmaChannel, SckPin, TxDmaChannel,
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WordSize,
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};
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use crate::time::Hertz;
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use core::future::Future;
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use core::marker::PhantomData;
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use core::ptr;
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use embassy::util::Unborrow;
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use embassy_hal_common::unborrow;
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use embassy_traits::spi as traits;
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pub use embedded_hal::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MODE_3};
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use futures::future::join3;
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impl WordSize {
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fn dsize(&self) -> u8 {
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match self {
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WordSize::EightBit => 0b0111,
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WordSize::SixteenBit => 0b1111,
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}
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}
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fn _frxth(&self) -> spi::vals::Fthlv {
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match self {
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WordSize::EightBit => spi::vals::Fthlv::ONEFRAME,
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WordSize::SixteenBit => spi::vals::Fthlv::ONEFRAME,
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}
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}
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}
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#[allow(unused)]
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pub struct Spi<'d, T: Instance, Tx = NoDma, Rx = NoDma> {
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sck: AnyPin,
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mosi: AnyPin,
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miso: AnyPin,
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txdma: Tx,
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rxdma: Rx,
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phantom: PhantomData<&'d mut T>,
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}
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impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
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pub fn new<F>(
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_peri: impl Unborrow<Target = T> + 'd,
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sck: impl Unborrow<Target = impl SckPin<T>>,
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mosi: impl Unborrow<Target = impl MosiPin<T>>,
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miso: impl Unborrow<Target = impl MisoPin<T>>,
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txdma: impl Unborrow<Target = Tx>,
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rxdma: impl Unborrow<Target = Rx>,
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freq: F,
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config: Config,
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) -> Self
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where
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F: Into<Hertz>,
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{
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unborrow!(sck, mosi, miso, txdma, rxdma);
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unsafe {
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Self::configure_pin(sck.block(), sck.pin() as _, sck.af_num());
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//sck.block().otyper().modify(|w| w.set_ot(sck.pin() as _, crate::pac::gpio::vals::Ot::PUSHPULL));
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Self::configure_pin(mosi.block(), mosi.pin() as _, mosi.af_num());
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//mosi.block().otyper().modify(|w| w.set_ot(mosi.pin() as _, crate::pac::gpio::vals::Ot::PUSHPULL));
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Self::configure_pin(miso.block(), miso.pin() as _, miso.af_num());
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}
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let sck = sck.degrade();
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let mosi = mosi.degrade();
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let miso = miso.degrade();
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let pclk = T::frequency();
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let br = Self::compute_baud_rate(pclk, freq.into());
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unsafe {
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T::enable();
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T::reset();
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T::regs().ifcr().write(|w| w.0 = 0xffff_ffff);
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T::regs().cfg2().modify(|w| {
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//w.set_ssoe(true);
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w.set_ssoe(false);
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w.set_cpha(
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match config.mode.phase == Phase::CaptureOnSecondTransition {
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true => spi::vals::Cpha::SECONDEDGE,
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false => spi::vals::Cpha::FIRSTEDGE,
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},
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);
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w.set_cpol(match config.mode.polarity == Polarity::IdleHigh {
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true => spi::vals::Cpol::IDLEHIGH,
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false => spi::vals::Cpol::IDLELOW,
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});
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w.set_lsbfrst(match config.byte_order {
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ByteOrder::LsbFirst => spi::vals::Lsbfrst::LSBFIRST,
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ByteOrder::MsbFirst => spi::vals::Lsbfrst::MSBFIRST,
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});
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w.set_ssm(true);
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w.set_master(spi::vals::Master::MASTER);
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w.set_comm(spi::vals::Comm::FULLDUPLEX);
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w.set_ssom(spi::vals::Ssom::ASSERTED);
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w.set_midi(0);
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w.set_mssi(0);
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w.set_afcntr(spi::vals::Afcntr::CONTROLLED);
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w.set_ssiop(spi::vals::Ssiop::ACTIVEHIGH);
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});
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T::regs().cfg1().modify(|w| {
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w.set_crcen(false);
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w.set_mbr(spi::vals::Mbr(br));
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w.set_dsize(WordSize::EightBit.dsize());
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});
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T::regs().cr2().modify(|w| {
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w.set_tsize(0);
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w.set_tser(0);
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});
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T::regs().cr1().modify(|w| {
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w.set_ssi(false);
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w.set_spe(true);
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});
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}
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Self {
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sck,
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mosi,
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miso,
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txdma,
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rxdma,
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phantom: PhantomData,
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}
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}
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unsafe fn configure_pin(block: Gpio, pin: usize, af_num: u8) {
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let (afr, n_af) = if pin < 8 { (0, pin) } else { (1, pin - 8) };
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block.moder().modify(|w| w.set_moder(pin, Moder::ALTERNATE));
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block.afr(afr).modify(|w| w.set_afr(n_af, Afr(af_num)));
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block
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.ospeedr()
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.modify(|w| w.set_ospeedr(pin, crate::pac::gpio::vals::Ospeedr::VERYHIGHSPEED));
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}
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unsafe fn unconfigure_pin(block: Gpio, pin: usize) {
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block.moder().modify(|w| w.set_moder(pin, Moder::ANALOG));
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}
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fn compute_baud_rate(clocks: Hertz, freq: Hertz) -> u8 {
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match clocks.0 / freq.0 {
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0 => unreachable!(),
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1..=2 => 0b000,
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3..=5 => 0b001,
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6..=11 => 0b010,
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12..=23 => 0b011,
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24..=39 => 0b100,
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40..=95 => 0b101,
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96..=191 => 0b110,
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_ => 0b111,
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}
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}
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fn set_word_size(word_size: WordSize) {
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unsafe {
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T::regs().cr1().modify(|w| {
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w.set_csusp(true);
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});
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while T::regs().sr().read().eot() {}
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T::regs().cr1().modify(|w| {
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w.set_spe(false);
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});
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T::regs().cfg1().modify(|w| {
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w.set_dsize(word_size.dsize());
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});
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T::regs().cr1().modify(|w| {
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w.set_spe(true);
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});
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}
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}
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#[allow(unused)]
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async fn write_dma_u8(&mut self, write: &[u8]) -> Result<(), Error>
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where
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Tx: TxDmaChannel<T>,
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{
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Self::set_word_size(WordSize::EightBit);
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unsafe {
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T::regs().cr1().modify(|w| {
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w.set_spe(false);
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});
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}
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let request = self.txdma.request();
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let dst = T::regs().txdr().ptr() as *mut u8;
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let f = self.txdma.write(request, write, dst);
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unsafe {
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T::regs().cfg1().modify(|reg| {
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reg.set_txdmaen(true);
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});
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T::regs().cr1().modify(|w| {
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w.set_spe(true);
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});
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T::regs().cr1().modify(|w| {
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w.set_cstart(true);
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});
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}
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f.await;
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unsafe {
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T::regs().cfg1().modify(|reg| {
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reg.set_txdmaen(false);
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});
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T::regs().cr1().modify(|w| {
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w.set_spe(false);
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});
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}
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Ok(())
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}
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#[allow(unused)]
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async fn read_dma_u8(&mut self, read: &mut [u8]) -> Result<(), Error>
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where
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Tx: TxDmaChannel<T>,
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Rx: RxDmaChannel<T>,
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{
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Self::set_word_size(WordSize::EightBit);
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unsafe {
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T::regs().cr1().modify(|w| {
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w.set_spe(false);
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});
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T::regs().cfg1().modify(|reg| {
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reg.set_rxdmaen(true);
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});
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}
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let clock_byte_count = read.len();
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let rx_request = self.rxdma.request();
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let rx_src = T::regs().rxdr().ptr() as *mut u8;
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let rx_f = self.rxdma.read(rx_request, rx_src, read);
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let tx_request = self.txdma.request();
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let tx_dst = T::regs().txdr().ptr() as *mut u8;
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let clock_byte = 0x00;
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let tx_f = self
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.txdma
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.write_x(tx_request, &clock_byte, clock_byte_count, tx_dst);
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unsafe {
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T::regs().cfg1().modify(|reg| {
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reg.set_txdmaen(true);
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});
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T::regs().cr1().modify(|w| {
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w.set_spe(true);
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});
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T::regs().cr1().modify(|w| {
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w.set_cstart(true);
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});
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}
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join3(tx_f, rx_f, Self::wait_for_idle()).await;
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unsafe {
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T::regs().cfg1().modify(|reg| {
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reg.set_rxdmaen(false);
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reg.set_txdmaen(false);
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});
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T::regs().cr1().modify(|w| {
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w.set_spe(false);
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});
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}
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Ok(())
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}
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#[allow(unused)]
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async fn read_write_dma_u8(&mut self, read: &mut [u8], write: &[u8]) -> Result<(), Error>
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where
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Tx: TxDmaChannel<T>,
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Rx: RxDmaChannel<T>,
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{
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assert!(read.len() >= write.len());
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Self::set_word_size(WordSize::EightBit);
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unsafe {
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T::regs().cr1().modify(|w| {
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w.set_spe(false);
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});
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T::regs().cfg1().modify(|reg| {
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reg.set_rxdmaen(true);
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});
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}
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let rx_request = self.rxdma.request();
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let rx_src = T::regs().rxdr().ptr() as *mut u8;
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let rx_f = self
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.rxdma
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.read(rx_request, rx_src, &mut read[0..write.len()]);
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let tx_request = self.txdma.request();
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let tx_dst = T::regs().txdr().ptr() as *mut u8;
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let tx_f = self.txdma.write(tx_request, write, tx_dst);
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unsafe {
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T::regs().cfg1().modify(|reg| {
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reg.set_txdmaen(true);
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});
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T::regs().cr1().modify(|w| {
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w.set_spe(true);
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});
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T::regs().cr1().modify(|w| {
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w.set_cstart(true);
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});
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}
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join3(tx_f, rx_f, Self::wait_for_idle()).await;
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unsafe {
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T::regs().cfg1().modify(|reg| {
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reg.set_rxdmaen(false);
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reg.set_txdmaen(false);
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});
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T::regs().cr1().modify(|w| {
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w.set_spe(false);
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});
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}
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Ok(())
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}
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async fn wait_for_idle() {
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unsafe {
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while !T::regs().sr().read().txc() {
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// spin
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}
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while T::regs().sr().read().rxplvl().0 > 0 {
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// spin
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}
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}
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}
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}
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impl<'d, T: Instance, Tx, Rx> Drop for Spi<'d, T, Tx, Rx> {
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fn drop(&mut self) {
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unsafe {
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Self::unconfigure_pin(self.sck.block(), self.sck.pin() as _);
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Self::unconfigure_pin(self.mosi.block(), self.mosi.pin() as _);
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Self::unconfigure_pin(self.miso.block(), self.miso.pin() as _);
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}
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}
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}
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impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u8> for Spi<'d, T, NoDma> {
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type Error = Error;
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fn write(&mut self, words: &[u8]) -> Result<(), Self::Error> {
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Self::set_word_size(WordSize::EightBit);
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let regs = T::regs();
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for word in words.iter() {
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while unsafe { !regs.sr().read().txp() } {
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// spin
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}
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unsafe {
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let txdr = regs.txdr().ptr() as *mut u8;
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ptr::write_volatile(txdr, *word);
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regs.cr1().modify(|reg| reg.set_cstart(true));
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}
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loop {
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let sr = unsafe { regs.sr().read() };
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if sr.tifre() {
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return Err(Error::Framing);
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}
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if sr.ovr() {
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return Err(Error::Overrun);
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}
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if sr.crce() {
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return Err(Error::Crc);
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}
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if !sr.txp() {
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// loop waiting for TXE
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}
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}
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}
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Ok(())
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}
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}
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impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u8> for Spi<'d, T, NoDma> {
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type Error = Error;
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fn transfer<'w>(&mut self, words: &'w mut [u8]) -> Result<&'w [u8], Self::Error> {
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Self::set_word_size(WordSize::EightBit);
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let regs = T::regs();
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for word in words.iter_mut() {
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unsafe {
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regs.cr1().modify(|reg| {
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reg.set_ssi(false);
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});
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}
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while unsafe { !regs.sr().read().txp() } {
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// spin
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}
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unsafe {
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let txdr = regs.txdr().ptr() as *mut u8;
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ptr::write_volatile(txdr, *word);
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regs.cr1().modify(|reg| reg.set_cstart(true));
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}
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loop {
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let sr = unsafe { regs.sr().read() };
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if sr.rxp() {
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break;
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}
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if sr.tifre() {
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return Err(Error::Framing);
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}
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if sr.ovr() {
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return Err(Error::Overrun);
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}
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if sr.crce() {
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return Err(Error::Crc);
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}
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}
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unsafe {
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let rxdr = regs.rxdr().ptr() as *const u8;
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*word = ptr::read_volatile(rxdr);
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}
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let sr = unsafe { regs.sr().read() };
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if sr.tifre() {
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return Err(Error::Framing);
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}
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if sr.ovr() {
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return Err(Error::Overrun);
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}
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if sr.crce() {
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return Err(Error::Crc);
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}
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}
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Ok(words)
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}
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}
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impl<'d, T: Instance> embedded_hal::blocking::spi::Write<u16> for Spi<'d, T, NoDma> {
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type Error = Error;
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fn write(&mut self, words: &[u16]) -> Result<(), Self::Error> {
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Self::set_word_size(WordSize::SixteenBit);
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let regs = T::regs();
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for word in words.iter() {
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while unsafe { !regs.sr().read().txp() } {
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// spin
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}
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unsafe {
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let txdr = regs.txdr().ptr() as *mut u16;
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ptr::write_volatile(txdr, *word);
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regs.cr1().modify(|reg| reg.set_cstart(true));
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}
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loop {
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let sr = unsafe { regs.sr().read() };
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if sr.tifre() {
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return Err(Error::Framing);
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}
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if sr.ovr() {
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return Err(Error::Overrun);
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}
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if sr.crce() {
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return Err(Error::Crc);
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}
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if !sr.txp() {
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// loop waiting for TXE
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}
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}
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}
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Ok(())
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}
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}
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impl<'d, T: Instance> embedded_hal::blocking::spi::Transfer<u16> for Spi<'d, T, NoDma> {
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type Error = Error;
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fn transfer<'w>(&mut self, words: &'w mut [u16]) -> Result<&'w [u16], Self::Error> {
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Self::set_word_size(WordSize::SixteenBit);
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let regs = T::regs();
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for word in words.iter_mut() {
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while unsafe { !regs.sr().read().txp() } {
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// spin
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}
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unsafe {
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let txdr = regs.txdr().ptr() as *mut u16;
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ptr::write_volatile(txdr, *word);
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regs.cr1().modify(|reg| reg.set_cstart(true));
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}
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loop {
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let sr = unsafe { regs.sr().read() };
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if sr.rxp() {
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break;
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}
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if sr.tifre() {
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return Err(Error::Framing);
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}
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if sr.ovr() {
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return Err(Error::Overrun);
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}
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if sr.crce() {
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return Err(Error::Crc);
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}
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}
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unsafe {
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let rxdr = regs.rxdr().ptr() as *const u16;
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*word = ptr::read_volatile(rxdr);
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}
|
|
let sr = unsafe { regs.sr().read() };
|
|
if sr.tifre() {
|
|
return Err(Error::Framing);
|
|
}
|
|
if sr.ovr() {
|
|
return Err(Error::Overrun);
|
|
}
|
|
if sr.crce() {
|
|
return Err(Error::Crc);
|
|
}
|
|
}
|
|
|
|
Ok(words)
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Instance, Tx, Rx> traits::Spi<u8> for Spi<'d, T, Tx, Rx> {
|
|
type Error = super::Error;
|
|
}
|
|
|
|
impl<'d, T: Instance, Tx: TxDmaChannel<T>, Rx> traits::Write<u8> for Spi<'d, T, Tx, Rx> {
|
|
#[rustfmt::skip]
|
|
type WriteFuture<'a> where Self: 'a = impl Future<Output = Result<(), Self::Error>> + 'a;
|
|
|
|
fn write<'a>(&'a mut self, data: &'a [u8]) -> Self::WriteFuture<'a> {
|
|
self.write_dma_u8(data)
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Instance, Tx: TxDmaChannel<T>, Rx: RxDmaChannel<T>> traits::Read<u8>
|
|
for Spi<'d, T, Tx, Rx>
|
|
{
|
|
#[rustfmt::skip]
|
|
type ReadFuture<'a> where Self: 'a = impl Future<Output = Result<(), Self::Error>> + 'a;
|
|
|
|
fn read<'a>(&'a mut self, data: &'a mut [u8]) -> Self::ReadFuture<'a> {
|
|
self.read_dma_u8(data)
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Instance, Tx: TxDmaChannel<T>, Rx: RxDmaChannel<T>> traits::FullDuplex<u8>
|
|
for Spi<'d, T, Tx, Rx>
|
|
{
|
|
#[rustfmt::skip]
|
|
type WriteReadFuture<'a> where Self: 'a = impl Future<Output = Result<(), Self::Error>> + 'a;
|
|
|
|
fn read_write<'a>(
|
|
&'a mut self,
|
|
read: &'a mut [u8],
|
|
write: &'a [u8],
|
|
) -> Self::WriteReadFuture<'a> {
|
|
self.read_write_dma_u8(read, write)
|
|
}
|
|
}
|