bors[bot] 01e5376b25 Merge #456 ... 456: Fix L4 clock setup for MSI and PLL to allow RNG operation r=Dirbaio a=lulf Example is tested on STM32L475VG. Co-authored-by: Ulf Lilleengen <lulf@redhat.com>		2021-10-26 11:59:14 +00:00
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src	Merge #456	2021-10-26 11:59:14 +00:00
.pep8	USART codegen	2021-04-25 22:35:51 +02:00
build.rs	Support for STM32L1	2021-09-21 14:50:23 +02:00
Cargo.toml	Changing the casts (code review request)	2021-09-28 18:31:04 +02:00