1000 lines
31 KiB
Rust
1000 lines
31 KiB
Rust
//! Universal Asynchronous Receiver Transmitter (UART) driver.
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//!
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//! The UART driver is provided in two flavors - this one and also [crate::buffered_uarte::BufferedUarte].
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//! The [Uarte] here is useful for those use-cases where reading the UARTE peripheral is
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//! exclusively awaited on. If the [Uarte] is required to be awaited on with some other future,
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//! for example when using `futures_util::future::select`, then you should consider
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//! [crate::buffered_uarte::BufferedUarte] so that reads may continue while processing these
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//! other futures. If you do not then you may lose data between reads.
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//!
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//! An advantage of the [Uarte] has over [crate::buffered_uarte::BufferedUarte] is that less
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//! memory may be used given that buffers are passed in directly to its read and write
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//! methods.
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#![macro_use]
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use core::future::poll_fn;
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use core::marker::PhantomData;
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use core::sync::atomic::{compiler_fence, Ordering};
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use core::task::Poll;
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use embassy_hal_internal::drop::OnDrop;
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use embassy_hal_internal::{into_ref, PeripheralRef};
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use pac::uarte0::RegisterBlock;
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// Re-export SVD variants to allow user to directly set values.
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pub use pac::uarte0::{baudrate::BAUDRATE_A as Baudrate, config::PARITY_A as Parity};
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use crate::chip::{EASY_DMA_SIZE, FORCE_COPY_BUFFER_SIZE};
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use crate::gpio::sealed::Pin as _;
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use crate::gpio::{self, AnyPin, Pin as GpioPin, PselBits};
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use crate::interrupt::typelevel::Interrupt;
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use crate::ppi::{AnyConfigurableChannel, ConfigurableChannel, Event, Ppi, Task};
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use crate::timer::{Frequency, Instance as TimerInstance, Timer};
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use crate::util::slice_in_ram_or;
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use crate::{interrupt, pac, Peripheral};
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/// UARTE config.
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#[derive(Clone)]
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#[non_exhaustive]
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pub struct Config {
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/// Parity bit.
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pub parity: Parity,
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/// Baud rate.
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pub baudrate: Baudrate,
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}
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impl Default for Config {
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fn default() -> Self {
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Self {
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parity: Parity::EXCLUDED,
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baudrate: Baudrate::BAUD115200,
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}
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}
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}
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/// UART error.
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#[derive(Debug, Clone, Copy, PartialEq, Eq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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#[non_exhaustive]
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pub enum Error {
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/// Buffer was too long.
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BufferTooLong,
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/// The buffer is not in data RAM. It's most likely in flash, and nRF's DMA cannot access flash.
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BufferNotInRAM,
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}
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/// Interrupt handler.
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pub struct InterruptHandler<T: Instance> {
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_phantom: PhantomData<T>,
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}
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impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandler<T> {
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unsafe fn on_interrupt() {
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let r = T::regs();
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let s = T::state();
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if r.events_endrx.read().bits() != 0 {
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s.endrx_waker.wake();
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r.intenclr.write(|w| w.endrx().clear());
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}
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if r.events_endtx.read().bits() != 0 {
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s.endtx_waker.wake();
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r.intenclr.write(|w| w.endtx().clear());
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}
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}
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}
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/// UARTE driver.
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pub struct Uarte<'d, T: Instance> {
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tx: UarteTx<'d, T>,
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rx: UarteRx<'d, T>,
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}
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/// Transmitter part of the UARTE driver.
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///
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/// This can be obtained via [`Uarte::split`], or created directly.
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pub struct UarteTx<'d, T: Instance> {
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_p: PeripheralRef<'d, T>,
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}
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/// Receiver part of the UARTE driver.
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///
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/// This can be obtained via [`Uarte::split`], or created directly.
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pub struct UarteRx<'d, T: Instance> {
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_p: PeripheralRef<'d, T>,
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}
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impl<'d, T: Instance> Uarte<'d, T> {
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/// Create a new UARTE without hardware flow control
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pub fn new(
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uarte: impl Peripheral<P = T> + 'd,
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_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
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rxd: impl Peripheral<P = impl GpioPin> + 'd,
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txd: impl Peripheral<P = impl GpioPin> + 'd,
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config: Config,
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) -> Self {
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into_ref!(rxd, txd);
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Self::new_inner(uarte, rxd.map_into(), txd.map_into(), None, None, config)
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}
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/// Create a new UARTE with hardware flow control (RTS/CTS)
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pub fn new_with_rtscts(
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uarte: impl Peripheral<P = T> + 'd,
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_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
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rxd: impl Peripheral<P = impl GpioPin> + 'd,
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txd: impl Peripheral<P = impl GpioPin> + 'd,
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cts: impl Peripheral<P = impl GpioPin> + 'd,
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rts: impl Peripheral<P = impl GpioPin> + 'd,
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config: Config,
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) -> Self {
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into_ref!(rxd, txd, cts, rts);
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Self::new_inner(
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uarte,
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rxd.map_into(),
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txd.map_into(),
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Some(cts.map_into()),
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Some(rts.map_into()),
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config,
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)
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}
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fn new_inner(
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uarte: impl Peripheral<P = T> + 'd,
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rxd: PeripheralRef<'d, AnyPin>,
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txd: PeripheralRef<'d, AnyPin>,
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cts: Option<PeripheralRef<'d, AnyPin>>,
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rts: Option<PeripheralRef<'d, AnyPin>>,
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config: Config,
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) -> Self {
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into_ref!(uarte);
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let r = T::regs();
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rxd.conf().write(|w| w.input().connect().drive().h0h1());
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r.psel.rxd.write(|w| unsafe { w.bits(rxd.psel_bits()) });
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txd.set_high();
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txd.conf().write(|w| w.dir().output().drive().h0h1());
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r.psel.txd.write(|w| unsafe { w.bits(txd.psel_bits()) });
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if let Some(pin) = &cts {
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pin.conf().write(|w| w.input().connect().drive().h0h1());
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}
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r.psel.cts.write(|w| unsafe { w.bits(cts.psel_bits()) });
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if let Some(pin) = &rts {
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pin.set_high();
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pin.conf().write(|w| w.dir().output().drive().h0h1());
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}
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r.psel.rts.write(|w| unsafe { w.bits(rts.psel_bits()) });
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T::Interrupt::unpend();
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unsafe { T::Interrupt::enable() };
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let hardware_flow_control = match (rts.is_some(), cts.is_some()) {
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(false, false) => false,
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(true, true) => true,
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_ => panic!("RTS and CTS pins must be either both set or none set."),
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};
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configure(r, config, hardware_flow_control);
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let s = T::state();
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s.tx_rx_refcount.store(2, Ordering::Relaxed);
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Self {
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tx: UarteTx {
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_p: unsafe { uarte.clone_unchecked() },
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},
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rx: UarteRx { _p: uarte },
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}
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}
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/// Split the Uarte into the transmitter and receiver parts.
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///
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/// This is useful to concurrently transmit and receive from independent tasks.
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pub fn split(self) -> (UarteTx<'d, T>, UarteRx<'d, T>) {
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(self.tx, self.rx)
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}
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/// Split the Uarte into the transmitter and receiver with idle support parts.
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///
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/// This is useful to concurrently transmit and receive from independent tasks.
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pub fn split_with_idle<U: TimerInstance>(
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self,
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timer: impl Peripheral<P = U> + 'd,
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ppi_ch1: impl Peripheral<P = impl ConfigurableChannel + 'd> + 'd,
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ppi_ch2: impl Peripheral<P = impl ConfigurableChannel + 'd> + 'd,
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) -> (UarteTx<'d, T>, UarteRxWithIdle<'d, T, U>) {
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(self.tx, self.rx.with_idle(timer, ppi_ch1, ppi_ch2))
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}
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/// Return the endtx event for use with PPI
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pub fn event_endtx(&self) -> Event {
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let r = T::regs();
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Event::from_reg(&r.events_endtx)
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}
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/// Read bytes until the buffer is filled.
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pub async fn read(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
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self.rx.read(buffer).await
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}
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/// Write all bytes in the buffer.
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pub async fn write(&mut self, buffer: &[u8]) -> Result<(), Error> {
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self.tx.write(buffer).await
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}
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/// Same as [`write`](Uarte::write) but will fail instead of copying data into RAM. Consult the module level documentation to learn more.
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pub async fn write_from_ram(&mut self, buffer: &[u8]) -> Result<(), Error> {
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self.tx.write_from_ram(buffer).await
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}
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/// Read bytes until the buffer is filled.
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pub fn blocking_read(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
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self.rx.blocking_read(buffer)
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}
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/// Write all bytes in the buffer.
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pub fn blocking_write(&mut self, buffer: &[u8]) -> Result<(), Error> {
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self.tx.blocking_write(buffer)
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}
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/// Same as [`blocking_write`](Uarte::blocking_write) but will fail instead of copying data into RAM. Consult the module level documentation to learn more.
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pub fn blocking_write_from_ram(&mut self, buffer: &[u8]) -> Result<(), Error> {
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self.tx.blocking_write_from_ram(buffer)
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}
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}
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fn configure(r: &RegisterBlock, config: Config, hardware_flow_control: bool) {
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r.config.write(|w| {
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w.hwfc().bit(hardware_flow_control);
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w.parity().variant(config.parity);
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w
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});
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r.baudrate.write(|w| w.baudrate().variant(config.baudrate));
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// Disable all interrupts
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r.intenclr.write(|w| unsafe { w.bits(0xFFFF_FFFF) });
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// Reset rxstarted, txstarted. These are used by drop to know whether a transfer was
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// stopped midway or not.
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r.events_rxstarted.reset();
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r.events_txstarted.reset();
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// Enable
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apply_workaround_for_enable_anomaly(&r);
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r.enable.write(|w| w.enable().enabled());
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}
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impl<'d, T: Instance> UarteTx<'d, T> {
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/// Create a new tx-only UARTE without hardware flow control
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pub fn new(
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uarte: impl Peripheral<P = T> + 'd,
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_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
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txd: impl Peripheral<P = impl GpioPin> + 'd,
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config: Config,
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) -> Self {
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into_ref!(txd);
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Self::new_inner(uarte, txd.map_into(), None, config)
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}
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/// Create a new tx-only UARTE with hardware flow control (RTS/CTS)
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pub fn new_with_rtscts(
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uarte: impl Peripheral<P = T> + 'd,
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_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
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txd: impl Peripheral<P = impl GpioPin> + 'd,
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cts: impl Peripheral<P = impl GpioPin> + 'd,
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config: Config,
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) -> Self {
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into_ref!(txd, cts);
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Self::new_inner(uarte, txd.map_into(), Some(cts.map_into()), config)
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}
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fn new_inner(
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uarte: impl Peripheral<P = T> + 'd,
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txd: PeripheralRef<'d, AnyPin>,
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cts: Option<PeripheralRef<'d, AnyPin>>,
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config: Config,
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) -> Self {
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into_ref!(uarte);
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let r = T::regs();
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txd.set_high();
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txd.conf().write(|w| w.dir().output().drive().s0s1());
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r.psel.txd.write(|w| unsafe { w.bits(txd.psel_bits()) });
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if let Some(pin) = &cts {
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pin.conf().write(|w| w.input().connect().drive().h0h1());
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}
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r.psel.cts.write(|w| unsafe { w.bits(cts.psel_bits()) });
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r.psel.rxd.write(|w| w.connect().disconnected());
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r.psel.rts.write(|w| w.connect().disconnected());
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let hardware_flow_control = cts.is_some();
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configure(r, config, hardware_flow_control);
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T::Interrupt::unpend();
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unsafe { T::Interrupt::enable() };
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let s = T::state();
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s.tx_rx_refcount.store(1, Ordering::Relaxed);
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Self { _p: uarte }
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}
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/// Write all bytes in the buffer.
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pub async fn write(&mut self, buffer: &[u8]) -> Result<(), Error> {
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match self.write_from_ram(buffer).await {
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Ok(_) => Ok(()),
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Err(Error::BufferNotInRAM) => {
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trace!("Copying UARTE tx buffer into RAM for DMA");
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let ram_buf = &mut [0; FORCE_COPY_BUFFER_SIZE][..buffer.len()];
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ram_buf.copy_from_slice(buffer);
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self.write_from_ram(&ram_buf).await
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}
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Err(error) => Err(error),
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}
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}
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/// Same as [`write`](Self::write) but will fail instead of copying data into RAM. Consult the module level documentation to learn more.
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pub async fn write_from_ram(&mut self, buffer: &[u8]) -> Result<(), Error> {
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if buffer.len() == 0 {
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return Ok(());
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}
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slice_in_ram_or(buffer, Error::BufferNotInRAM)?;
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if buffer.len() > EASY_DMA_SIZE {
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return Err(Error::BufferTooLong);
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}
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let ptr = buffer.as_ptr();
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let len = buffer.len();
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let r = T::regs();
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let s = T::state();
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let drop = OnDrop::new(move || {
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trace!("write drop: stopping");
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r.intenclr.write(|w| w.endtx().clear());
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r.events_txstopped.reset();
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r.tasks_stoptx.write(|w| unsafe { w.bits(1) });
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// TX is stopped almost instantly, spinning is fine.
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while r.events_endtx.read().bits() == 0 {}
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trace!("write drop: stopped");
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});
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r.txd.ptr.write(|w| unsafe { w.ptr().bits(ptr as u32) });
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r.txd.maxcnt.write(|w| unsafe { w.maxcnt().bits(len as _) });
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r.events_endtx.reset();
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r.intenset.write(|w| w.endtx().set());
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compiler_fence(Ordering::SeqCst);
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trace!("starttx");
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r.tasks_starttx.write(|w| unsafe { w.bits(1) });
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poll_fn(|cx| {
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s.endtx_waker.register(cx.waker());
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if r.events_endtx.read().bits() != 0 {
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return Poll::Ready(());
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}
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Poll::Pending
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})
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.await;
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compiler_fence(Ordering::SeqCst);
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r.events_txstarted.reset();
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drop.defuse();
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Ok(())
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}
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/// Write all bytes in the buffer.
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pub fn blocking_write(&mut self, buffer: &[u8]) -> Result<(), Error> {
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match self.blocking_write_from_ram(buffer) {
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Ok(_) => Ok(()),
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Err(Error::BufferNotInRAM) => {
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trace!("Copying UARTE tx buffer into RAM for DMA");
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let ram_buf = &mut [0; FORCE_COPY_BUFFER_SIZE][..buffer.len()];
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ram_buf.copy_from_slice(buffer);
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self.blocking_write_from_ram(&ram_buf)
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}
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Err(error) => Err(error),
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}
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}
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/// Same as [`write_from_ram`](Self::write_from_ram) but will fail instead of copying data into RAM. Consult the module level documentation to learn more.
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pub fn blocking_write_from_ram(&mut self, buffer: &[u8]) -> Result<(), Error> {
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if buffer.len() == 0 {
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return Ok(());
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}
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slice_in_ram_or(buffer, Error::BufferNotInRAM)?;
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if buffer.len() > EASY_DMA_SIZE {
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return Err(Error::BufferTooLong);
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}
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let ptr = buffer.as_ptr();
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let len = buffer.len();
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let r = T::regs();
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r.txd.ptr.write(|w| unsafe { w.ptr().bits(ptr as u32) });
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r.txd.maxcnt.write(|w| unsafe { w.maxcnt().bits(len as _) });
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r.events_endtx.reset();
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r.intenclr.write(|w| w.endtx().clear());
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compiler_fence(Ordering::SeqCst);
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trace!("starttx");
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r.tasks_starttx.write(|w| unsafe { w.bits(1) });
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while r.events_endtx.read().bits() == 0 {}
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compiler_fence(Ordering::SeqCst);
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r.events_txstarted.reset();
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Ok(())
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}
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}
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impl<'a, T: Instance> Drop for UarteTx<'a, T> {
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fn drop(&mut self) {
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trace!("uarte tx drop");
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let r = T::regs();
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let did_stoptx = r.events_txstarted.read().bits() != 0;
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trace!("did_stoptx {}", did_stoptx);
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// Wait for txstopped, if needed.
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while did_stoptx && r.events_txstopped.read().bits() == 0 {}
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let s = T::state();
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drop_tx_rx(&r, &s);
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}
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}
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impl<'d, T: Instance> UarteRx<'d, T> {
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/// Create a new rx-only UARTE without hardware flow control
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pub fn new(
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uarte: impl Peripheral<P = T> + 'd,
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_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
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rxd: impl Peripheral<P = impl GpioPin> + 'd,
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config: Config,
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) -> Self {
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into_ref!(rxd);
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Self::new_inner(uarte, rxd.map_into(), None, config)
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}
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/// Create a new rx-only UARTE with hardware flow control (RTS/CTS)
|
|
pub fn new_with_rtscts(
|
|
uarte: impl Peripheral<P = T> + 'd,
|
|
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
|
|
rxd: impl Peripheral<P = impl GpioPin> + 'd,
|
|
rts: impl Peripheral<P = impl GpioPin> + 'd,
|
|
config: Config,
|
|
) -> Self {
|
|
into_ref!(rxd, rts);
|
|
Self::new_inner(uarte, rxd.map_into(), Some(rts.map_into()), config)
|
|
}
|
|
|
|
fn new_inner(
|
|
uarte: impl Peripheral<P = T> + 'd,
|
|
rxd: PeripheralRef<'d, AnyPin>,
|
|
rts: Option<PeripheralRef<'d, AnyPin>>,
|
|
config: Config,
|
|
) -> Self {
|
|
into_ref!(uarte);
|
|
|
|
let r = T::regs();
|
|
|
|
rxd.conf().write(|w| w.input().connect().drive().h0h1());
|
|
r.psel.rxd.write(|w| unsafe { w.bits(rxd.psel_bits()) });
|
|
|
|
if let Some(pin) = &rts {
|
|
pin.set_high();
|
|
pin.conf().write(|w| w.dir().output().drive().h0h1());
|
|
}
|
|
r.psel.rts.write(|w| unsafe { w.bits(rts.psel_bits()) });
|
|
|
|
r.psel.txd.write(|w| w.connect().disconnected());
|
|
r.psel.cts.write(|w| w.connect().disconnected());
|
|
|
|
T::Interrupt::unpend();
|
|
unsafe { T::Interrupt::enable() };
|
|
|
|
let hardware_flow_control = rts.is_some();
|
|
configure(r, config, hardware_flow_control);
|
|
|
|
let s = T::state();
|
|
s.tx_rx_refcount.store(1, Ordering::Relaxed);
|
|
|
|
Self { _p: uarte }
|
|
}
|
|
|
|
/// Upgrade to an instance that supports idle line detection.
|
|
pub fn with_idle<U: TimerInstance>(
|
|
self,
|
|
timer: impl Peripheral<P = U> + 'd,
|
|
ppi_ch1: impl Peripheral<P = impl ConfigurableChannel + 'd> + 'd,
|
|
ppi_ch2: impl Peripheral<P = impl ConfigurableChannel + 'd> + 'd,
|
|
) -> UarteRxWithIdle<'d, T, U> {
|
|
let timer = Timer::new(timer);
|
|
|
|
into_ref!(ppi_ch1, ppi_ch2);
|
|
|
|
let r = T::regs();
|
|
|
|
// BAUDRATE register values are `baudrate * 2^32 / 16000000`
|
|
// source: https://devzone.nordicsemi.com/f/nordic-q-a/391/uart-baudrate-register-values
|
|
//
|
|
// We want to stop RX if line is idle for 2 bytes worth of time
|
|
// That is 20 bits (each byte is 1 start bit + 8 data bits + 1 stop bit)
|
|
// This gives us the amount of 16M ticks for 20 bits.
|
|
let baudrate = r.baudrate.read().baudrate().variant().unwrap();
|
|
let timeout = 0x8000_0000 / (baudrate as u32 / 40);
|
|
|
|
timer.set_frequency(Frequency::F16MHz);
|
|
timer.cc(0).write(timeout);
|
|
timer.cc(0).short_compare_clear();
|
|
timer.cc(0).short_compare_stop();
|
|
|
|
let mut ppi_ch1 = Ppi::new_one_to_two(
|
|
ppi_ch1.map_into(),
|
|
Event::from_reg(&r.events_rxdrdy),
|
|
timer.task_clear(),
|
|
timer.task_start(),
|
|
);
|
|
ppi_ch1.enable();
|
|
|
|
let mut ppi_ch2 = Ppi::new_one_to_one(
|
|
ppi_ch2.map_into(),
|
|
timer.cc(0).event_compare(),
|
|
Task::from_reg(&r.tasks_stoprx),
|
|
);
|
|
ppi_ch2.enable();
|
|
|
|
UarteRxWithIdle {
|
|
rx: self,
|
|
timer,
|
|
ppi_ch1: ppi_ch1,
|
|
_ppi_ch2: ppi_ch2,
|
|
}
|
|
}
|
|
|
|
/// Read bytes until the buffer is filled.
|
|
pub async fn read(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
|
|
if buffer.len() == 0 {
|
|
return Ok(());
|
|
}
|
|
if buffer.len() > EASY_DMA_SIZE {
|
|
return Err(Error::BufferTooLong);
|
|
}
|
|
|
|
let ptr = buffer.as_ptr();
|
|
let len = buffer.len();
|
|
|
|
let r = T::regs();
|
|
let s = T::state();
|
|
|
|
let drop = OnDrop::new(move || {
|
|
trace!("read drop: stopping");
|
|
|
|
r.intenclr.write(|w| w.endrx().clear());
|
|
r.events_rxto.reset();
|
|
r.tasks_stoprx.write(|w| unsafe { w.bits(1) });
|
|
|
|
while r.events_endrx.read().bits() == 0 {}
|
|
|
|
trace!("read drop: stopped");
|
|
});
|
|
|
|
r.rxd.ptr.write(|w| unsafe { w.ptr().bits(ptr as u32) });
|
|
r.rxd.maxcnt.write(|w| unsafe { w.maxcnt().bits(len as _) });
|
|
|
|
r.events_endrx.reset();
|
|
r.intenset.write(|w| w.endrx().set());
|
|
|
|
compiler_fence(Ordering::SeqCst);
|
|
|
|
trace!("startrx");
|
|
r.tasks_startrx.write(|w| unsafe { w.bits(1) });
|
|
|
|
poll_fn(|cx| {
|
|
s.endrx_waker.register(cx.waker());
|
|
if r.events_endrx.read().bits() != 0 {
|
|
return Poll::Ready(());
|
|
}
|
|
Poll::Pending
|
|
})
|
|
.await;
|
|
|
|
compiler_fence(Ordering::SeqCst);
|
|
r.events_rxstarted.reset();
|
|
drop.defuse();
|
|
|
|
Ok(())
|
|
}
|
|
|
|
/// Read bytes until the buffer is filled.
|
|
pub fn blocking_read(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
|
|
if buffer.len() == 0 {
|
|
return Ok(());
|
|
}
|
|
if buffer.len() > EASY_DMA_SIZE {
|
|
return Err(Error::BufferTooLong);
|
|
}
|
|
|
|
let ptr = buffer.as_ptr();
|
|
let len = buffer.len();
|
|
|
|
let r = T::regs();
|
|
|
|
r.rxd.ptr.write(|w| unsafe { w.ptr().bits(ptr as u32) });
|
|
r.rxd.maxcnt.write(|w| unsafe { w.maxcnt().bits(len as _) });
|
|
|
|
r.events_endrx.reset();
|
|
r.intenclr.write(|w| w.endrx().clear());
|
|
|
|
compiler_fence(Ordering::SeqCst);
|
|
|
|
trace!("startrx");
|
|
r.tasks_startrx.write(|w| unsafe { w.bits(1) });
|
|
|
|
while r.events_endrx.read().bits() == 0 {}
|
|
|
|
compiler_fence(Ordering::SeqCst);
|
|
r.events_rxstarted.reset();
|
|
|
|
Ok(())
|
|
}
|
|
}
|
|
|
|
impl<'a, T: Instance> Drop for UarteRx<'a, T> {
|
|
fn drop(&mut self) {
|
|
trace!("uarte rx drop");
|
|
|
|
let r = T::regs();
|
|
|
|
let did_stoprx = r.events_rxstarted.read().bits() != 0;
|
|
trace!("did_stoprx {}", did_stoprx);
|
|
|
|
// Wait for rxto, if needed.
|
|
while did_stoprx && r.events_rxto.read().bits() == 0 {}
|
|
|
|
let s = T::state();
|
|
|
|
drop_tx_rx(&r, &s);
|
|
}
|
|
}
|
|
|
|
/// Receiver part of the UARTE driver, with `read_until_idle` support.
|
|
///
|
|
/// This can be obtained via [`Uarte::split_with_idle`].
|
|
pub struct UarteRxWithIdle<'d, T: Instance, U: TimerInstance> {
|
|
rx: UarteRx<'d, T>,
|
|
timer: Timer<'d, U>,
|
|
ppi_ch1: Ppi<'d, AnyConfigurableChannel, 1, 2>,
|
|
_ppi_ch2: Ppi<'d, AnyConfigurableChannel, 1, 1>,
|
|
}
|
|
|
|
impl<'d, T: Instance, U: TimerInstance> UarteRxWithIdle<'d, T, U> {
|
|
/// Read bytes until the buffer is filled.
|
|
pub async fn read(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
|
|
self.ppi_ch1.disable();
|
|
self.rx.read(buffer).await
|
|
}
|
|
|
|
/// Read bytes until the buffer is filled.
|
|
pub fn blocking_read(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
|
|
self.ppi_ch1.disable();
|
|
self.rx.blocking_read(buffer)
|
|
}
|
|
|
|
/// Read bytes until the buffer is filled, or the line becomes idle.
|
|
///
|
|
/// Returns the amount of bytes read.
|
|
pub async fn read_until_idle(&mut self, buffer: &mut [u8]) -> Result<usize, Error> {
|
|
if buffer.len() == 0 {
|
|
return Ok(0);
|
|
}
|
|
if buffer.len() > EASY_DMA_SIZE {
|
|
return Err(Error::BufferTooLong);
|
|
}
|
|
|
|
let ptr = buffer.as_ptr();
|
|
let len = buffer.len();
|
|
|
|
let r = T::regs();
|
|
let s = T::state();
|
|
|
|
self.ppi_ch1.enable();
|
|
|
|
let drop = OnDrop::new(|| {
|
|
self.timer.stop();
|
|
|
|
r.intenclr.write(|w| w.endrx().clear());
|
|
r.events_rxto.reset();
|
|
r.tasks_stoprx.write(|w| unsafe { w.bits(1) });
|
|
|
|
while r.events_endrx.read().bits() == 0 {}
|
|
});
|
|
|
|
r.rxd.ptr.write(|w| unsafe { w.ptr().bits(ptr as u32) });
|
|
r.rxd.maxcnt.write(|w| unsafe { w.maxcnt().bits(len as _) });
|
|
|
|
r.events_endrx.reset();
|
|
r.intenset.write(|w| w.endrx().set());
|
|
|
|
compiler_fence(Ordering::SeqCst);
|
|
|
|
r.tasks_startrx.write(|w| unsafe { w.bits(1) });
|
|
|
|
poll_fn(|cx| {
|
|
s.endrx_waker.register(cx.waker());
|
|
if r.events_endrx.read().bits() != 0 {
|
|
return Poll::Ready(());
|
|
}
|
|
Poll::Pending
|
|
})
|
|
.await;
|
|
|
|
compiler_fence(Ordering::SeqCst);
|
|
let n = r.rxd.amount.read().amount().bits() as usize;
|
|
|
|
self.timer.stop();
|
|
r.events_rxstarted.reset();
|
|
|
|
drop.defuse();
|
|
|
|
Ok(n)
|
|
}
|
|
|
|
/// Read bytes until the buffer is filled, or the line becomes idle.
|
|
///
|
|
/// Returns the amount of bytes read.
|
|
pub fn blocking_read_until_idle(&mut self, buffer: &mut [u8]) -> Result<usize, Error> {
|
|
if buffer.len() == 0 {
|
|
return Ok(0);
|
|
}
|
|
if buffer.len() > EASY_DMA_SIZE {
|
|
return Err(Error::BufferTooLong);
|
|
}
|
|
|
|
let ptr = buffer.as_ptr();
|
|
let len = buffer.len();
|
|
|
|
let r = T::regs();
|
|
|
|
self.ppi_ch1.enable();
|
|
|
|
r.rxd.ptr.write(|w| unsafe { w.ptr().bits(ptr as u32) });
|
|
r.rxd.maxcnt.write(|w| unsafe { w.maxcnt().bits(len as _) });
|
|
|
|
r.events_endrx.reset();
|
|
r.intenclr.write(|w| w.endrx().clear());
|
|
|
|
compiler_fence(Ordering::SeqCst);
|
|
|
|
r.tasks_startrx.write(|w| unsafe { w.bits(1) });
|
|
|
|
while r.events_endrx.read().bits() == 0 {}
|
|
|
|
compiler_fence(Ordering::SeqCst);
|
|
let n = r.rxd.amount.read().amount().bits() as usize;
|
|
|
|
self.timer.stop();
|
|
r.events_rxstarted.reset();
|
|
|
|
Ok(n)
|
|
}
|
|
}
|
|
|
|
#[cfg(not(any(feature = "_nrf9160", feature = "_nrf5340")))]
|
|
pub(crate) fn apply_workaround_for_enable_anomaly(_r: &crate::pac::uarte0::RegisterBlock) {
|
|
// Do nothing
|
|
}
|
|
|
|
#[cfg(any(feature = "_nrf9160", feature = "_nrf5340"))]
|
|
pub(crate) fn apply_workaround_for_enable_anomaly(r: &crate::pac::uarte0::RegisterBlock) {
|
|
// Apply workaround for anomalies:
|
|
// - nRF9160 - anomaly 23
|
|
// - nRF5340 - anomaly 44
|
|
let rxenable_reg: *const u32 = ((r as *const _ as usize) + 0x564) as *const u32;
|
|
let txenable_reg: *const u32 = ((r as *const _ as usize) + 0x568) as *const u32;
|
|
|
|
// NB Safety: This is taken from Nordic's driver -
|
|
// https://github.com/NordicSemiconductor/nrfx/blob/master/drivers/src/nrfx_uarte.c#L197
|
|
if unsafe { core::ptr::read_volatile(txenable_reg) } == 1 {
|
|
r.tasks_stoptx.write(|w| unsafe { w.bits(1) });
|
|
}
|
|
|
|
// NB Safety: This is taken from Nordic's driver -
|
|
// https://github.com/NordicSemiconductor/nrfx/blob/master/drivers/src/nrfx_uarte.c#L197
|
|
if unsafe { core::ptr::read_volatile(rxenable_reg) } == 1 {
|
|
r.enable.write(|w| w.enable().enabled());
|
|
r.tasks_stoprx.write(|w| unsafe { w.bits(1) });
|
|
|
|
let mut workaround_succeded = false;
|
|
// The UARTE is able to receive up to four bytes after the STOPRX task has been triggered.
|
|
// On lowest supported baud rate (1200 baud), with parity bit and two stop bits configured
|
|
// (resulting in 12 bits per data byte sent), this may take up to 40 ms.
|
|
for _ in 0..40000 {
|
|
// NB Safety: This is taken from Nordic's driver -
|
|
// https://github.com/NordicSemiconductor/nrfx/blob/master/drivers/src/nrfx_uarte.c#L197
|
|
if unsafe { core::ptr::read_volatile(rxenable_reg) } == 0 {
|
|
workaround_succeded = true;
|
|
break;
|
|
} else {
|
|
// Need to sleep for 1us here
|
|
}
|
|
}
|
|
|
|
if !workaround_succeded {
|
|
panic!("Failed to apply workaround for UART");
|
|
}
|
|
|
|
let errors = r.errorsrc.read().bits();
|
|
// NB Safety: safe to write back the bits we just read to clear them
|
|
r.errorsrc.write(|w| unsafe { w.bits(errors) });
|
|
r.enable.write(|w| w.enable().disabled());
|
|
}
|
|
}
|
|
|
|
pub(crate) fn drop_tx_rx(r: &pac::uarte0::RegisterBlock, s: &sealed::State) {
|
|
if s.tx_rx_refcount.fetch_sub(1, Ordering::Relaxed) == 1 {
|
|
// Finally we can disable, and we do so for the peripheral
|
|
// i.e. not just rx concerns.
|
|
r.enable.write(|w| w.enable().disabled());
|
|
|
|
gpio::deconfigure_pin(r.psel.rxd.read().bits());
|
|
gpio::deconfigure_pin(r.psel.txd.read().bits());
|
|
gpio::deconfigure_pin(r.psel.rts.read().bits());
|
|
gpio::deconfigure_pin(r.psel.cts.read().bits());
|
|
|
|
trace!("uarte tx and rx drop: done");
|
|
}
|
|
}
|
|
|
|
pub(crate) mod sealed {
|
|
use core::sync::atomic::AtomicU8;
|
|
|
|
use embassy_sync::waitqueue::AtomicWaker;
|
|
|
|
use super::*;
|
|
|
|
pub struct State {
|
|
pub endrx_waker: AtomicWaker,
|
|
pub endtx_waker: AtomicWaker,
|
|
pub tx_rx_refcount: AtomicU8,
|
|
}
|
|
impl State {
|
|
pub const fn new() -> Self {
|
|
Self {
|
|
endrx_waker: AtomicWaker::new(),
|
|
endtx_waker: AtomicWaker::new(),
|
|
tx_rx_refcount: AtomicU8::new(0),
|
|
}
|
|
}
|
|
}
|
|
|
|
pub trait Instance {
|
|
fn regs() -> &'static pac::uarte0::RegisterBlock;
|
|
fn state() -> &'static State;
|
|
fn buffered_state() -> &'static crate::buffered_uarte::State;
|
|
}
|
|
}
|
|
|
|
/// UARTE peripheral instance.
|
|
pub trait Instance: Peripheral<P = Self> + sealed::Instance + 'static + Send {
|
|
/// Interrupt for this peripheral.
|
|
type Interrupt: interrupt::typelevel::Interrupt;
|
|
}
|
|
|
|
macro_rules! impl_uarte {
|
|
($type:ident, $pac_type:ident, $irq:ident) => {
|
|
impl crate::uarte::sealed::Instance for peripherals::$type {
|
|
fn regs() -> &'static pac::uarte0::RegisterBlock {
|
|
unsafe { &*pac::$pac_type::ptr() }
|
|
}
|
|
fn state() -> &'static crate::uarte::sealed::State {
|
|
static STATE: crate::uarte::sealed::State = crate::uarte::sealed::State::new();
|
|
&STATE
|
|
}
|
|
fn buffered_state() -> &'static crate::buffered_uarte::State {
|
|
static STATE: crate::buffered_uarte::State = crate::buffered_uarte::State::new();
|
|
&STATE
|
|
}
|
|
}
|
|
impl crate::uarte::Instance for peripherals::$type {
|
|
type Interrupt = crate::interrupt::typelevel::$irq;
|
|
}
|
|
};
|
|
}
|
|
|
|
// ====================
|
|
|
|
mod eh02 {
|
|
use super::*;
|
|
|
|
impl<'d, T: Instance> embedded_hal_02::blocking::serial::Write<u8> for Uarte<'d, T> {
|
|
type Error = Error;
|
|
|
|
fn bwrite_all(&mut self, buffer: &[u8]) -> Result<(), Self::Error> {
|
|
self.blocking_write(buffer)
|
|
}
|
|
|
|
fn bflush(&mut self) -> Result<(), Self::Error> {
|
|
Ok(())
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Instance> embedded_hal_02::blocking::serial::Write<u8> for UarteTx<'d, T> {
|
|
type Error = Error;
|
|
|
|
fn bwrite_all(&mut self, buffer: &[u8]) -> Result<(), Self::Error> {
|
|
self.blocking_write(buffer)
|
|
}
|
|
|
|
fn bflush(&mut self) -> Result<(), Self::Error> {
|
|
Ok(())
|
|
}
|
|
}
|
|
}
|
|
|
|
#[cfg(feature = "unstable-traits")]
|
|
mod eh1 {
|
|
use super::*;
|
|
|
|
impl embedded_hal_1::serial::Error for Error {
|
|
fn kind(&self) -> embedded_hal_1::serial::ErrorKind {
|
|
match *self {
|
|
Self::BufferTooLong => embedded_hal_1::serial::ErrorKind::Other,
|
|
Self::BufferNotInRAM => embedded_hal_1::serial::ErrorKind::Other,
|
|
}
|
|
}
|
|
}
|
|
|
|
// =====================
|
|
|
|
impl<'d, T: Instance> embedded_hal_1::serial::ErrorType for Uarte<'d, T> {
|
|
type Error = Error;
|
|
}
|
|
|
|
impl<'d, T: Instance> embedded_hal_1::serial::Write for Uarte<'d, T> {
|
|
fn write(&mut self, buffer: &[u8]) -> Result<(), Self::Error> {
|
|
self.blocking_write(buffer)
|
|
}
|
|
|
|
fn flush(&mut self) -> Result<(), Self::Error> {
|
|
Ok(())
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Instance> embedded_hal_1::serial::ErrorType for UarteTx<'d, T> {
|
|
type Error = Error;
|
|
}
|
|
|
|
impl<'d, T: Instance> embedded_hal_1::serial::Write for UarteTx<'d, T> {
|
|
fn write(&mut self, buffer: &[u8]) -> Result<(), Self::Error> {
|
|
self.blocking_write(buffer)
|
|
}
|
|
|
|
fn flush(&mut self) -> Result<(), Self::Error> {
|
|
Ok(())
|
|
}
|
|
}
|
|
|
|
impl<'d, T: Instance> embedded_hal_1::serial::ErrorType for UarteRx<'d, T> {
|
|
type Error = Error;
|
|
}
|
|
}
|