536 lines
15 KiB
Rust
536 lines
15 KiB
Rust
use core::marker::PhantomData;
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use embassy_embedded_hal::SetConfig;
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use embassy_hal_internal::{into_ref, PeripheralRef};
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use crate::dma::NoDma;
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use crate::gpio::sealed::AFType;
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use crate::gpio::Pull;
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use crate::i2c::{Error, Instance, SclPin, SdaPin};
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use crate::pac::i2c;
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use crate::time::Hertz;
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use crate::{interrupt, Peripheral};
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/// Interrupt handler.
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pub struct InterruptHandler<T: Instance> {
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_phantom: PhantomData<T>,
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}
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impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandler<T> {
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unsafe fn on_interrupt() {}
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}
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#[non_exhaustive]
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#[derive(Copy, Clone, Default)]
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pub struct Config {
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pub sda_pullup: bool,
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pub scl_pullup: bool,
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}
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pub struct State {}
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impl State {
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pub(crate) const fn new() -> Self {
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Self {}
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}
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}
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pub struct I2c<'d, T: Instance, TXDMA = NoDma, RXDMA = NoDma> {
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phantom: PhantomData<&'d mut T>,
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#[allow(dead_code)]
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tx_dma: PeripheralRef<'d, TXDMA>,
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#[allow(dead_code)]
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rx_dma: PeripheralRef<'d, RXDMA>,
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}
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impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
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pub fn new(
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_peri: impl Peripheral<P = T> + 'd,
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scl: impl Peripheral<P = impl SclPin<T>> + 'd,
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sda: impl Peripheral<P = impl SdaPin<T>> + 'd,
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_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
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tx_dma: impl Peripheral<P = TXDMA> + 'd,
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rx_dma: impl Peripheral<P = RXDMA> + 'd,
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freq: Hertz,
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config: Config,
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) -> Self {
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into_ref!(scl, sda, tx_dma, rx_dma);
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T::enable();
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T::reset();
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scl.set_as_af_pull(
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scl.af_num(),
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AFType::OutputOpenDrain,
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match config.scl_pullup {
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true => Pull::Up,
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false => Pull::None,
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},
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);
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sda.set_as_af_pull(
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sda.af_num(),
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AFType::OutputOpenDrain,
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match config.sda_pullup {
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true => Pull::Up,
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false => Pull::None,
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},
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);
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T::regs().cr1().modify(|reg| {
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reg.set_pe(false);
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//reg.set_anfoff(false);
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});
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let timings = Timings::new(T::frequency(), freq);
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T::regs().cr2().modify(|reg| {
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reg.set_freq(timings.freq);
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});
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T::regs().ccr().modify(|reg| {
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reg.set_f_s(timings.mode.f_s());
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reg.set_duty(timings.duty.duty());
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reg.set_ccr(timings.ccr);
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});
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T::regs().trise().modify(|reg| {
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reg.set_trise(timings.trise);
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});
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T::regs().cr1().modify(|reg| {
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reg.set_pe(true);
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});
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Self {
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phantom: PhantomData,
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tx_dma,
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rx_dma,
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}
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}
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fn check_and_clear_error_flags(&self) -> Result<i2c::regs::Sr1, Error> {
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// Note that flags should only be cleared once they have been registered. If flags are
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// cleared otherwise, there may be an inherent race condition and flags may be missed.
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let sr1 = T::regs().sr1().read();
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if sr1.timeout() {
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T::regs().sr1().modify(|reg| reg.set_timeout(false));
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return Err(Error::Timeout);
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}
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if sr1.pecerr() {
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T::regs().sr1().modify(|reg| reg.set_pecerr(false));
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return Err(Error::Crc);
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}
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if sr1.ovr() {
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T::regs().sr1().modify(|reg| reg.set_ovr(false));
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return Err(Error::Overrun);
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}
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if sr1.af() {
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T::regs().sr1().modify(|reg| reg.set_af(false));
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return Err(Error::Nack);
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}
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if sr1.arlo() {
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T::regs().sr1().modify(|reg| reg.set_arlo(false));
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return Err(Error::Arbitration);
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}
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// The errata indicates that BERR may be incorrectly detected. It recommends ignoring and
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// clearing the BERR bit instead.
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if sr1.berr() {
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T::regs().sr1().modify(|reg| reg.set_berr(false));
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}
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Ok(sr1)
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}
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fn write_bytes(
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&mut self,
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addr: u8,
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bytes: &[u8],
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check_timeout: impl Fn() -> Result<(), Error>,
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) -> Result<(), Error> {
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// Send a START condition
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T::regs().cr1().modify(|reg| {
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reg.set_start(true);
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});
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// Wait until START condition was generated
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while !self.check_and_clear_error_flags()?.start() {
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check_timeout()?;
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}
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// Also wait until signalled we're master and everything is waiting for us
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while {
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self.check_and_clear_error_flags()?;
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let sr2 = T::regs().sr2().read();
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!sr2.msl() && !sr2.busy()
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} {
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check_timeout()?;
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}
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// Set up current address, we're trying to talk to
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T::regs().dr().write(|reg| reg.set_dr(addr << 1));
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// Wait until address was sent
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// Wait for the address to be acknowledged
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// Check for any I2C errors. If a NACK occurs, the ADDR bit will never be set.
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while !self.check_and_clear_error_flags()?.addr() {
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check_timeout()?;
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}
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// Clear condition by reading SR2
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let _ = T::regs().sr2().read();
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// Send bytes
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for c in bytes {
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self.send_byte(*c, &check_timeout)?;
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}
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// Fallthrough is success
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Ok(())
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}
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fn send_byte(&self, byte: u8, check_timeout: impl Fn() -> Result<(), Error>) -> Result<(), Error> {
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// Wait until we're ready for sending
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while {
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// Check for any I2C errors. If a NACK occurs, the ADDR bit will never be set.
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!self.check_and_clear_error_flags()?.txe()
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} {
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check_timeout()?;
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}
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// Push out a byte of data
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T::regs().dr().write(|reg| reg.set_dr(byte));
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// Wait until byte is transferred
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while {
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// Check for any potential error conditions.
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!self.check_and_clear_error_flags()?.btf()
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} {
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check_timeout()?;
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}
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Ok(())
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}
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fn recv_byte(&self, check_timeout: impl Fn() -> Result<(), Error>) -> Result<u8, Error> {
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while {
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// Check for any potential error conditions.
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self.check_and_clear_error_flags()?;
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!T::regs().sr1().read().rxne()
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} {
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check_timeout()?;
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}
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let value = T::regs().dr().read().dr();
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Ok(value)
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}
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pub fn blocking_read_timeout(
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&mut self,
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addr: u8,
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buffer: &mut [u8],
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check_timeout: impl Fn() -> Result<(), Error>,
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) -> Result<(), Error> {
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if let Some((last, buffer)) = buffer.split_last_mut() {
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// Send a START condition and set ACK bit
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T::regs().cr1().modify(|reg| {
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reg.set_start(true);
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reg.set_ack(true);
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});
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// Wait until START condition was generated
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while !self.check_and_clear_error_flags()?.start() {
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check_timeout()?;
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}
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// Also wait until signalled we're master and everything is waiting for us
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while {
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let sr2 = T::regs().sr2().read();
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!sr2.msl() && !sr2.busy()
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} {
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check_timeout()?;
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}
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// Set up current address, we're trying to talk to
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T::regs().dr().write(|reg| reg.set_dr((addr << 1) + 1));
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// Wait until address was sent
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// Wait for the address to be acknowledged
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while !self.check_and_clear_error_flags()?.addr() {
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check_timeout()?;
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}
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// Clear condition by reading SR2
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let _ = T::regs().sr2().read();
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// Receive bytes into buffer
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for c in buffer {
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*c = self.recv_byte(&check_timeout)?;
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}
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// Prepare to send NACK then STOP after next byte
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T::regs().cr1().modify(|reg| {
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reg.set_ack(false);
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reg.set_stop(true);
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});
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// Receive last byte
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*last = self.recv_byte(&check_timeout)?;
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// Wait for the STOP to be sent.
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while T::regs().cr1().read().stop() {
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check_timeout()?;
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}
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// Fallthrough is success
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Ok(())
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} else {
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Err(Error::Overrun)
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}
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}
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pub fn blocking_read(&mut self, addr: u8, read: &mut [u8]) -> Result<(), Error> {
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self.blocking_read_timeout(addr, read, || Ok(()))
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}
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pub fn blocking_write_timeout(
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&mut self,
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addr: u8,
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write: &[u8],
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check_timeout: impl Fn() -> Result<(), Error>,
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) -> Result<(), Error> {
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self.write_bytes(addr, write, &check_timeout)?;
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// Send a STOP condition
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T::regs().cr1().modify(|reg| reg.set_stop(true));
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// Wait for STOP condition to transmit.
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while T::regs().cr1().read().stop() {
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check_timeout()?;
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}
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// Fallthrough is success
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Ok(())
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}
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pub fn blocking_write(&mut self, addr: u8, write: &[u8]) -> Result<(), Error> {
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self.blocking_write_timeout(addr, write, || Ok(()))
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}
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pub fn blocking_write_read_timeout(
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&mut self,
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addr: u8,
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write: &[u8],
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read: &mut [u8],
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check_timeout: impl Fn() -> Result<(), Error>,
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) -> Result<(), Error> {
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self.write_bytes(addr, write, &check_timeout)?;
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self.blocking_read_timeout(addr, read, &check_timeout)?;
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Ok(())
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}
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pub fn blocking_write_read(&mut self, addr: u8, write: &[u8], read: &mut [u8]) -> Result<(), Error> {
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self.blocking_write_read_timeout(addr, write, read, || Ok(()))
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}
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}
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impl<'d, T: Instance, TXDMA, RXDMA> Drop for I2c<'d, T, TXDMA, RXDMA> {
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fn drop(&mut self) {
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T::disable();
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}
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}
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impl<'d, T: Instance> embedded_hal_02::blocking::i2c::Read for I2c<'d, T> {
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type Error = Error;
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fn read(&mut self, addr: u8, read: &mut [u8]) -> Result<(), Self::Error> {
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self.blocking_read(addr, read)
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}
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}
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impl<'d, T: Instance> embedded_hal_02::blocking::i2c::Write for I2c<'d, T> {
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type Error = Error;
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fn write(&mut self, addr: u8, write: &[u8]) -> Result<(), Self::Error> {
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self.blocking_write(addr, write)
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}
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}
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impl<'d, T: Instance> embedded_hal_02::blocking::i2c::WriteRead for I2c<'d, T> {
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type Error = Error;
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fn write_read(&mut self, addr: u8, write: &[u8], read: &mut [u8]) -> Result<(), Self::Error> {
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self.blocking_write_read(addr, write, read)
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}
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}
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#[cfg(feature = "unstable-traits")]
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mod eh1 {
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use super::*;
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impl embedded_hal_1::i2c::Error for Error {
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fn kind(&self) -> embedded_hal_1::i2c::ErrorKind {
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match *self {
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Self::Bus => embedded_hal_1::i2c::ErrorKind::Bus,
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Self::Arbitration => embedded_hal_1::i2c::ErrorKind::ArbitrationLoss,
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Self::Nack => {
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embedded_hal_1::i2c::ErrorKind::NoAcknowledge(embedded_hal_1::i2c::NoAcknowledgeSource::Unknown)
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}
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Self::Timeout => embedded_hal_1::i2c::ErrorKind::Other,
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Self::Crc => embedded_hal_1::i2c::ErrorKind::Other,
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Self::Overrun => embedded_hal_1::i2c::ErrorKind::Overrun,
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Self::ZeroLengthTransfer => embedded_hal_1::i2c::ErrorKind::Other,
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}
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}
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}
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impl<'d, T: Instance> embedded_hal_1::i2c::ErrorType for I2c<'d, T> {
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type Error = Error;
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}
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impl<'d, T: Instance> embedded_hal_1::i2c::I2c for I2c<'d, T> {
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fn read(&mut self, address: u8, read: &mut [u8]) -> Result<(), Self::Error> {
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self.blocking_read(address, read)
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}
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fn write(&mut self, address: u8, write: &[u8]) -> Result<(), Self::Error> {
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self.blocking_write(address, write)
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}
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fn write_read(&mut self, address: u8, write: &[u8], read: &mut [u8]) -> Result<(), Self::Error> {
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self.blocking_write_read(address, write, read)
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}
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fn transaction(
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&mut self,
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_address: u8,
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_operations: &mut [embedded_hal_1::i2c::Operation<'_>],
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) -> Result<(), Self::Error> {
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todo!();
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}
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}
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}
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enum Mode {
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Fast,
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Standard,
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}
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impl Mode {
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fn f_s(&self) -> i2c::vals::FS {
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match self {
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Mode::Fast => i2c::vals::FS::FAST,
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Mode::Standard => i2c::vals::FS::STANDARD,
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}
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}
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}
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enum Duty {
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Duty2_1,
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Duty16_9,
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}
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impl Duty {
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fn duty(&self) -> i2c::vals::Duty {
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match self {
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Duty::Duty2_1 => i2c::vals::Duty::DUTY2_1,
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Duty::Duty16_9 => i2c::vals::Duty::DUTY16_9,
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}
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}
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}
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struct Timings {
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freq: u8,
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mode: Mode,
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trise: u8,
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ccr: u16,
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duty: Duty,
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}
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impl Timings {
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fn new(i2cclk: Hertz, speed: Hertz) -> Self {
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// Calculate settings for I2C speed modes
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let speed = speed.0;
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let clock = i2cclk.0;
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let freq = clock / 1_000_000;
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assert!((2..=50).contains(&freq));
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// Configure bus frequency into I2C peripheral
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let trise = if speed <= 100_000 {
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freq + 1
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} else {
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(freq * 300) / 1000 + 1
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};
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let mut ccr;
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let duty;
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let mode;
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// I2C clock control calculation
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if speed <= 100_000 {
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duty = Duty::Duty2_1;
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mode = Mode::Standard;
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ccr = {
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let ccr = clock / (speed * 2);
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if ccr < 4 {
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4
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} else {
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ccr
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}
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};
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} else {
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const DUTYCYCLE: u8 = 0;
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mode = Mode::Fast;
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if DUTYCYCLE == 0 {
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duty = Duty::Duty2_1;
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ccr = clock / (speed * 3);
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ccr = if ccr < 1 { 1 } else { ccr };
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// Set clock to fast mode with appropriate parameters for selected speed (2:1 duty cycle)
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} else {
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duty = Duty::Duty16_9;
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ccr = clock / (speed * 25);
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ccr = if ccr < 1 { 1 } else { ccr };
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// Set clock to fast mode with appropriate parameters for selected speed (16:9 duty cycle)
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}
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}
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Self {
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freq: freq as u8,
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trise: trise as u8,
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ccr: ccr as u16,
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duty,
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mode,
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//prescale: presc_reg,
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//scll,
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//sclh,
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//sdadel,
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//scldel,
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}
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}
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}
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impl<'d, T: Instance> SetConfig for I2c<'d, T> {
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type Config = Hertz;
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fn set_config(&mut self, config: &Self::Config) {
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let timings = Timings::new(T::frequency(), *config);
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T::regs().cr2().modify(|reg| {
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reg.set_freq(timings.freq);
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});
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T::regs().ccr().modify(|reg| {
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reg.set_f_s(timings.mode.f_s());
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reg.set_duty(timings.duty.duty());
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reg.set_ccr(timings.ccr);
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});
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T::regs().trise().modify(|reg| {
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reg.set_trise(timings.trise);
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});
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}
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}
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